8430AY-62T

ICS8430-62 500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer DATASHEET General Description The ICS8430-62 is a general purpose, dual output Crystal-to-3.3V, 2.5V Differential LVPECL High HiPerClockS™ Frequency Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8430-62 has a selectable REF_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 500MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. Frequency steps as small as 1MHz can be achieved using a 16MHz crystal or REF_CLK. Features • • • • • • • • • • • Dual differential 3.3V or 2.5V LVPECL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK Output frequency range: 20.83MHz to 500MHz Crystal input frequency range: 14MHz to 27MHz VCO range: 250MHz to 500MHz Parallel or serial interface for programming counter and output dividers RMS period jitter: 5ps (maximum) Cycle-to-cycle jitter: 35ps (maximum) Full 3.3V or 3.3V core/2.5V output supply 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS Block Diagram VCO_SEL Pullup XTAL_SEL Pullup Pin Assignment VCO_SEL nP_LOAD M4 M3 M1 M0 M2 REF_CLK Pulldown 0 OSC XTAL_IN XTAL_OUT 32 31 30 29 28 27 26 25 1 ÷16 ÷1 ÷1.5 ÷2 ÷3 ÷4 ÷6 ÷8 ÷12 M5 M6 M7 M8 N0 N1 N2 FOUT0 nFOUT0 VEE 1 2 3 4 5 6 7 8 9 TEST XTAL_IN 24 23 22 21 20 19 18 17 10 11 12 13 14 15 16 FOUT0 nFOUT1 nFOUT0 VCC FOUT1 VCCO VEE XTAL_OUT REF_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR PLL Phase Detector MR Pulldown VCO ÷M 0 1 FOUT1 nFOUT1 S_LOAD Pulldown S_DATA Pulldown S_CLOCK Pulldown nP_LOAD Pulldown M0:M8 N0:N2 9 3 Configuration Interface Logic TEST ICS8430-62 32 Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8430AY-62 REVISION A JULY 2, 2009 1 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Functional Description NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8430-62 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 500MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8430-62 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hard-wired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fXTAL x M 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 250 ≤ M ≤ 500. The frequency out is defined as follows: fout = fVCO = fXTAL x M N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW S_DATA, Shift Register Input Output of M Divider Do Not Use SERIAL LOADING S_CLOCK S_DATA t T1 S T0 H N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t S_LOAD nP_LOAD t S PARALLEL LOADING M0:M8, N0:N2 nP_LOAD t S M, N t H S_LOAD Time Figure 1. Parallel & Serial Load Operations ICS8430AY-62 REVISION A JULY 2, 2009 2 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number 1, 2, 28, 29, 30, 31, 32 3, 4 5, 7 6 8, 16 9 10 11, 12 13 14, 15 Name M5, M6, M0, M1, M2, M3, M4 M7, M8 N0, N2 N1 VEE TEST VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 Input Input Input Input Power Output Power Output Power Output Type Description Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. Pullup Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS/LVTTL interface levels. Pullup Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Differential output pair for the synthesizer. LVPECL interface levels. Output supply pin for LVPECL outputs. Differential output pair for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to Pulldown go high. When Logic LOW, the internal dividers and the outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Pulldown Pulldown Pulldown Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin. Pullup Selects between crystal oscillator or REF_CLK inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when LOW. LVCMOS/LVTTL interface levels. 17 MR Input 18 19 20 21 22 23 24, 25 26 S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL REF_CLK XTAL_OUT XTAL_IN nP_LOAD Input Input Input Power Input Input Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M Pulldown divider, and when data present at N2:N0 sets the N output divider value. LVCMOS/LVTTL interface levels. Pullup Determines whether synthesizer is in PLL or bypass mode. When LOW, synthesizer is in bypass mode, when HIGH,synthesizer is in PLL mode. LVCMOS/LVTTL interface levels. Input 27 VCO_SEL Input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ ICS8430AY-62 REVISION A JULY 2, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Function Tables Table 3A. Parallel and Serial Mode Function Table Inputs MR H L L L L L L L nP_LOAD X L ↑ H H H H H M X Data Data X X X X X N X Data Data X X X X X S_LOAD X X L L ↑ ↓ L H S_CLOCK X X X ↑ L L X ↑ S_DATA X X X Data Data Data X Data Conditions Reset. Forces true outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don’t care ↑ = Rising edge transition ↓ = Falling edge transition Table 3B. Programmable VCO Frequency Function Table VCO Frequency (MHz) 250 251 252 253 • • 498 499 500 256 M Divide 250 251 252 253 • • 498 499 500 M8 0 0 0 0 • • 1 1 1 128 M7 1 1 1 1 • • 1 1 1 64 M6 1 1 1 1 • • 1 1 1 32 M5 1 1 1 1 • • 1 1 1 16 M4 1 1 1 1 • • 1 1 1 8 M3 1 1 1 1 • • 0 0 0 4 M2 0 0 1 1 • • 0 0 1 2 M1 1 1 0 0 • • 1 1 0 1 M0 0 1 0 1 • • 0 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a REF_CLK or crystal frequency of 16MHz. ICS8430AY-62 REVISION A JULY 2, 2009 4 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Table 3C. Programmable Output Divider Function Table Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divider Value 1 1.5 2 3 4 6 8 12 Output Frequency (MHz) Minimum 250 166.66 125 83.33 62.5 41.66 31.25 20.83 Maximum 500 333.33 250 166.66 125 83.33 62.5 41.66 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC+ 0.5V 50mA 100mA 65.7°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage 2.375 Power Supply Current Analog Supply Current 2.5 2.625 130 14 V mA mA Test Conditions Minimum 3.135 VCC – 0.14 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 Units V V V ICS8430AY-62 REVISION A JULY 2, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage M[0:6], N0, N2, MR, S_CLOCK, REF_CLK, S_DATA, S_LOAD, nP_LOAD M7, M8, N1, XTAL_SEL, VCO_SEL M[0:6], N0, N2, MR, S_CLOCK, REF_CLK, S_DATA, S_LOAD, nP_LOAD M7, M8, N1, XTAL_SEL, VCO_SEL VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 Units V V IIH Input High Current VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA IIL Input Low Current VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V VCCO = 3.3V±% VCCO = 2.5V±5% -150 2.6 1.8 0.5 µA V V V TEST; NOTE 1 VCCO = 3.3V±5% or 2.5V±5% NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, TA = 0°C to 70°C Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO – 1.4 VCCO– 2.0 0.6 Typical Maximum VCCO – 0.9 VCCO – 1.7 1.0 Units µA µA V NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. Table 4D. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C to 70°C Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO – 1.4 VCCO– 2.0 0.4 Typical Maximum VCCO – 0.9 VCCO – 1.5 1.0 Units µA µA V NOTE 1: Outputs terminated with 50Ω to VCCO – 2V. ICS8430AY-62 REVISION A JULY 2, 2009 6 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Table 5. Input Characteristics, VCC = 3.3V±5%, VCCO = 3.3V±5% or 2.5V±5%, TA = 0°C to 70°C Symbol Parameter REF_CLK; NOTE 1 fIN Input Frequency XTAL_IN, XTAL_OUT; NOTE 1 S_CLOCK Input Rise/Fall Time REF_CLK S_CLOCK, S_DATA, S_LOAD nP_LOAD 6 50 Test Conditions Minimum 14 14 Typical Maximum 27 27 50 5 Units MHz MHz MHz ns ns ns tR / tF NOTE 1: For the input crystal and REF_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 ≤ M ≤ 511. Using the maximum input frequency of 27MHz, valid values of M are 149 ≤ M ≤ 296. Table 6. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 14 Test Conditions Minimum Typical Fundamental 27 50 7 MHz Maximum Units Ω pF ICS8430AY-62 REVISION A JULY 2, 2009 7 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER AC Electrical Characteristics Table 7A. AC Characteristics, VCC = VCCO = 3.3V±5%, TA = 0°C to 70°C Symbol fOUT tjit(cc) tjit(per) tsk(o) tR / tF tS Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 2 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD odc tLOCK Output Duty Cycle PLL Lock time Even N Dividers Odd N Dividers 20% to 80% 200 5 5 5 5 5 5 48 43 52 57 10 N ≠ 1.5 N = 1.5 N ≠ 1.5 Test Conditions Minimum 20.83 Typical Maximum 500 35 200 5 20 700 Units MHz ps ps ps ps ps ns ns ns ns ns ns % % ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. ICS8430AY-62 REVISION A JULY 2, 2009 8 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Table 7B. AC Characteristics, VCC = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C to 70°C Symbol fOUT tjit(cc) tjit(per) tsk(o) tR / t F tS Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 2 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD odc tLOCK Output Duty Cycle PLL Lock time Even N Dividers Odd N Dividers 20% to 80% 200 5 5 5 5 5 5 48 43 52 57 10 N ≠ 1.5 N = 1.5 N ≠ 1.5 Test Conditions Minimum 20.83 Typical Maximum 500 35 200 6 20 700 Units MHz ps ps ps ps ps ns ns ns ns ns ns % % ms NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. ICS8430AY-62 REVISION A JULY 2, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2.8V±0.04V 2V 2V 2V 2.8V±0.04V VCC, VCCO Qx VCCA SCOPE VCC VCCO VCCA Qx SCOPE LVPECL nQx VEE VEE LVPECL nQx -1.3V±0.165V -0.5V±0.125V 3.3/3.3V LVPECL Output Load AC Test Circuit 3.3V/2.5V LVPECL Output Load AC Test Circuit nFOUTx FOUTx VOH VREF VOL nFOUTy FOUTy t sk(o) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) Output Skew Period Jitter nFOUTx FOUTx nFOUTx FOUTx t PW t cycle n ➤ t cycle n+1 ➤ t t jit(cc) = |t cycle n – t cycle n+1| 1000 Cycles Cycle-to-Cycle Jitter ICS8430AY-62 REVISION A JULY 2, 2009 ➤ ➤ PERIOD odc = t PW t PERIOD x 100% Output Duty Cycle/Pulse Width/Period 10 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information, continued nFOUTx 80% 80% VSW I N G FOUTx 20% tR tF 20% Output Rise/Fall Time Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8430-62 provides separate power supplies to isolate any high frequency switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VCC .01µF VCCA .01µF 10µF 10Ω Figure 2. Power Supply Filtering ICS8430AY-62 REVISION A JULY 2, 2009 11 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Crystal Input Interface The ICS8430-62 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p Figure 3. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VCC VCC R1 Ro Rs 50Ω 0.1µf XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface ICS8430AY-62 REVISION A JULY 2, 2009 12 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. Outputs: TEST Output The unused TEST output can be left floating. There should be no trace attached. LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. REF_CLK Input For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω 1 RTT = * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input _ LVPECL Zo = 50Ω R1 84Ω R2 84Ω Input Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination ICS8430AY-62 REVISION A JULY 2, 2009 13 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Termination for 2.5V LVPECL Outputs Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50Ω + 50Ω – 50Ω – R3 250 50Ω + VCC = 2.5V 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 6A. 2.5V LVPECL Driver Termination Example Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 6C. 2.5V LVPECL Driver Termination Example ICS8430AY-62 REVISION A JULY 2, 2009 14 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Schematic Example The schematic of the ICS8430-62 layout example used in this layout guideline is shown in Figure 7A. The ICS8430-62 recommended PCB board layout for this example is shown in Figure 7B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. C1 U1 32 31 30 29 28 27 26 25 X1 C2 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL_IN VCC 24 23 22 21 20 19 18 17 R7 10 VCCA C11 0.01u C16 10u VCC=3.3V SP = Spare Pads 1 2 3 4 5 6 7 8 M5 M6 M7 M8 N0 N1 N2 VEE XTAL_OUT REF_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR Logic Input Pin Examples VCC 9 10 11 12 13 14 15 16 TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE VCC R1 125 R3 125 Set Logic Input to '1' RU1 1K VCC Set Logic Input to '0' RU2 SP VCC C14 0.1u Zo = 50 Ohm RD1 SP To Logic Input pins RD2 1K To Logic Input pins C15 0.1u + Zo = 50 Ohm - R2 84 R4 84 Figure 7A. ICS8430-62 Schematic of Recommended Layout ICS8430AY-62 REVISION A JULY 2, 2009 15 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA pin as possible. • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace.Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. Clock Traces and Termination The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. Crystal The crystal X1 should be located as close as possible to the pins 24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. GND C1 C2 VCC VIA X1 U1 PIN 1 C11 R7 C16 VCCA Close to the input pins of the receiver C14 TL1N C15 TL1 R1 R2 TL1N TL1 TL1, TL21N are 50 Ohm traces and equal length R3 R4 Figure 7B. PCB Board Layout for ICS8430-62 ICS8430AY-62 REVISION A JULY 2, 2009 16 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8430-62. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430-62 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 450.45mW + 60mW = 510.45mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 65.7°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.510W * 65.7°C/W = 103.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 65.7°C/W 1 55.9°C/W 2.5 52.4°C/W ICS8430AY-62 REVISION A JULY 2, 2009 17 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 8. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS8430AY-62 REVISION A JULY 2, 2009 18 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 9. θJA vs. Air Flow Table for a 32 Lead LQFP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 65.7°C/W 1 55.9°C/W 2.5 52.4°C/W Transistor Count The transistor count for ICS8430-62 is: 4258 ICS8430AY-62 REVISION A JULY 2, 2009 19 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 10. Package Dimensions for 32 Lead LQFP JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS8430AY-62 REVISION A JULY 2, 2009 20 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 11. Ordering Information Part/Order Number 8430AY-62 8430AY-62T 8430AY-62LF 8430AY-62LFT Marking ICS8430AY-62 ICS8430AY-62 ICS8430AY62L ICS8430AY62L Package 32 Lead LQFP 32 Lead LQFP “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8430AY-62 REVISION A JULY 2, 2009 21 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER Revision History Sheet Rev A Table Page 1 Description of Change Block Diagram - output labels were cut-off. Date 7/2/09 ICS8430AY-62 REVISION A JULY 2, 2009 22 ©2009 Integrated Device Technology, Inc. ICS8430-62 Datasheet 500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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