8430S10BYI-03LFT

Clock Generator for Cavium Processors ICS8430S10I-03 DATA SHEET General Description The ICS8430S10I-03 is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the DDR reference clocks, the PCI/PCI-X bus clocks, and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN30XX/CN31XX/CN38XX/CN58XX processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The extended temperature range of the ICS8430S10I-03 supports telecommunication, networking, and storage requirements. Features • • • • • • • • • One selectable differential output pair for DDR 533/400/667, LVPECL, LVDS interface levels Nine LVCMOS/ LVTTL outputs, 23Ω typical output impedance Selectable external crystal or differential input source Crystal oscillator interface designed for 25MHz, parallel resonant crystal Differential input pair (PCLK, nPCLK) accepts LVPECL, LVDS, CML, SSTL input levels Internal resistor bias on nPCLK pin allows the user to drive PCLK input with external single-ended (LVCMOS/ LVTTL) input levels Power supply modes: CORE / OUTPUT 3.3V / 3.3V LVDS, LVPECL, LVCMOS 3.3V / 2.5V LVCMOS -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Applications • • • • • • • • • Systems using Cavium Processors CPE Gateway Design Home Media Servers 802.11n AP or Gateway Pin Assignment QREF2 GND VDDO_REF nLVDS_SEL GND QE VDDO_REF nOE_E GND QREF0 QREF1 Soho Secure Gateway Soho SME Gateway Wireless Soho and SME VPN Solutions Wired and Wireless Network Security Web Servers and Exchange Servers VDD nOE_D GND nPLL_ SEL XTAL_IN XTAL _ OUT nXTAL _ SEL PCLK nPCLK nOE_C nOE_B GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 ICS8430S10I-03 33 48-Pin TQFP,E- Pad 32 48 TQFP, E-Pad 5 7mm x 7mm package 31 6 7mm x 7mm x 1mmx 1mm body 7 package body 30 Y Package 8 29 Y Package Top View 9 28 Top View 10 27 26 11 12 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 SPI_SEL0 PCI_SEL1 PCI_SEL0 DDR_SEL 1 DDR_SEL0 nQA QA VDD VDDA nOE_A SPI_SEL1 VDD VDDO_E VDDO_CD QC QD0 QD1 CORE_SEL GND GND nOE_REF VDDO_B QB0 QB1 VDDO_B ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 1 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Block Diagram Pulldown Pulldown Pulldown Pullup/Pulldown Pulldown 2 Pulldown Pulldown 2 2 Pulldown nLVDS_SEL Pulldown Pulldown ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 2 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 1. Pin Descriptions Number 1, 13, 23 2 3, 12, 30, 31, 39, 42, 46 4 5, 6 7 8 9 Name VDD nOE_D Power Input Pulldown Type Description Core supply pins. Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. Power supply ground. Pulldown PLL bypass. When LOW, PLL is enabled. When HIGH, PLL is bypassed. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown Pulldown Pullup/ Pulldown Pulldown Selects XTAL input when LOW. Selects differential clock (PCLK, nPCLK) input when HIGH. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Internal resistor bias to VDD/2. Active LOW output enable for Bank C output. When logic HIGH, the output is high impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL interface levels. Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are high impedance (HI-Z). When logic LOW, the outputs are enabled. LVCMOS/LVTTL interface levels. Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels. Selects the SPI PLL clock reference frequency. See Table 3D. Selects the PCI, PCI-X reference clock output frequency. See Table 3C. LVCMOS/LVTTL interface levels. Selects the DDR reference clock output frequency. See Table 3B. LVCMOS/LVTTL interface levels. Differential output pair. Selectable between LVPECL and LVDS interface levels. Analog supply pin. Bank B output supply pins. 3.3 V or 2.5V supply. Single-ended Bank B outputs. LVCMOS/LVTTL interface levels. Pulldown Active LOW output enabled. When logic HIGH, the QREF[2:0] outputs are high impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled. LVCMOS/ LVTTL interface levels. Selects the processor core clock output frequency. The output frequency is 50MHz when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL interface levels. Single-end Bank D outputs. LVCMOS/LVTTL interface levels. Single-end Bank C output. LVCMOS/LVTTL interface levels. Bank C and Bank D output supply pin. 3.3 V or 2.5V supply. GND nPLL_SEL XTAL_IN, XTAL_OUT nXTAL_SEL PCLK nPCLK Power Input Input Input Input Input 10 nOE_C Input 11 14 15, 16 17, 18 19, 20 21, 22 24 25, 28 26, 27 29 nOE_B nOE_A SPI_SEL1, SPI_SEL0 PCI_SEL1, PCI_SEL0 DDR_SEL1, DDR_SEL0 nQA, QA VDDA VDDO_B QB1, QB0 nOE_REF Input Input Input Input Input Output Power Power Output Input Pulldown Pulldown Pulldown Pulldown Pulldown 32 33, 34 35 36 CORE_SEL QD1, QD0 QC VDDO_CD Input Output Output Power Pulldown Pin descriptions continue on the next page. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 3 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Number 37 38 40 41, 48 43, 44, 45 47 Name VDDO_E QE nLVDS_SEL VDDO_REF QREF2, QREF1, QREF0 nOE_E Power Output Input Power Output Type Description Bank E output supply pin. 3.3 V or 2.5V supply. Single-end Bank E output. LVCMOS/LVTTL interface levels. Pulldown Selects between LVDS and LVPECL interface levels on differential output pair QA and nQA. When LOW, LVDS levels are selected. When HIGH, LVPECL levels are selected. See Table 3E. Bank QREF output supply pins. 3.3 V or 2.5V supply. Single-ended reference clock outputs. LVCMOS/LVTTL interface levels. Active LOW output enable for Bank E output. When logic HIGH, the output is high impedance (HI-Z). When logic LOW, the output is enabled. LVCMOS/LVTTL interface levels. Input Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN CPD RPULLUP RPULLDOWN Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor QB[0:1], QC, QD[0:1], QE QREF[0:2] QB[0:1], QC, QD[0:1], QE QREF[0:2] VDDO_X = 3.465V VDD, VDDO_X = 3.465V VDD = 3.465V, VDDO_X = 2.625V Test Conditions Minimum Typical 2 10 10 51 51 23 Maximum Units pF pF pF kΩ kΩ Ω ROUT Output Impedance VDDO_X = 2.625V 26 Ω NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 4 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Function Tables Table 3A. Control Input Function Table Input CORE_SEL 0 1 Output Frequency QB[0:1] 50MHz (default) 33.333MHz Table 3B. Control Input Function Table Inputs DDR_SEL1 0 0 1 1 DDR_SEL0 0 1 0 1 Output Frequency QA, nQA 133.333MHz (default) 100.000MHz 83.333MHz 125.000MHz Table 3C. Control Input Function Table Inputs PCI_SEL1 0 0 1 1 PCI_SEL0 0 1 0 1 Output Frequency QC 133.333MHz (default) 100.000MHz 66.6667MHz 33.333MHz Table 3D. Control Input Function Table Inputs SPI_SEL1 0 0 1 SPI_SEL0 0 1 0 Output Frequency QD[0:1] 100.000MHz (default) 125.000MHz 80.000MHz Table 3E. Control Input Function Table Input nLVDS_SEL 0 1 Output Levels QA, nQA LVDS (default) LVPECL ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 5 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI XTAL_IN Other Inputs Outputs, VO (LVCMOS) Outputs, IO (LVDS) Continuous Current Surge Current Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V 0V to VDD -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 10mA 15mA 50mA 100mA 33.1°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. LVCMOS Power Supply DC Characteristics, VDD = VDDO_X = 3.3V ± 5%, TA = -40°C to 85°C Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load, nLVDS_SEL = 0 Test Conditions Minimum 3.135 VDD – 0.20 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 150 20 39 Units V V V mA mA mA NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. Table 4B. LVCMOS Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 2.5V ± 5%, TA = -40°C to 85°C Symbol VDD VDDA VDDO_X IDD IDDA IDDO_X Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load, nLVDS_SEL = 0 Test Conditions Minimum 3.135 VDD – 0.20 2.375 Typical 3.3 3.3 2.5 Maximum 3.465 VDD 2.625 150 20 27 Units V V V mA mA mA NOTE: VDDO_X denotes VDDO_B, VDDO_CD and VDDO_REF. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 6 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 4C. LVPECL Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VDD VDDA IGND IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current nLVDS_SEL = 1 Test Conditions Minimum 3.135 VDD – 0.20 Typical 3.3 3.3 Maximum 3.465 VDD 186 20 Units V V mA mA Table 4D. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current nLVDS_SEL = 0 Test Conditions Minimum 3.135 VDD – 0.20 Typical 3.3 3.3 Maximum 3.465 VDD 150 20 Units V V mA mA Table 4E. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL DDR_SEL[0:1], nPLL_SEL, nLVDS_SEL, PCI_SEL[0:1], nOE_REF, SPI_SEL[0:1], nOE_[A:E], nXTAL_SEL, CORE_SEL Test Conditions Minimum 2.2 -0.3 Typical Maximum VDD + 0.3 0.8 Units V V IIH Input High Current VDD = VIN = 3.465V 150 µA IIL Input Low Current VDD = 3.465V, VIN = 0V -10 µA VOH Output High Voltage VDDO_X = 3.465V, IOH = -12mA VDDO_X = 2.625V, IOH = -12mA VDDO_X = 3.465V, IOL = 12mA VDDO_X = 2.625V, IOL = 12mA 2.6 1.8 0.65 0.55 V V V V VOL Output Low Voltage NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 7 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Table 4F. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol IIH IIL VPP VCMR VOH VOL VSWING Parameter Input High Current Input Low Current nPCLK Peak-to-Peak Voltage Common Mode Input Voltage; NOTE 1 Output High Voltage; NOTE 2 Output Low Voltage; NOTE 2 Peak-to-Peak Output Voltage Swing PCLK, nPCLK PCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.3 GND + 1.5 VDD – 1.4 VDD – 2.0 0.6 1.0 VDD VDD – 0.9 VDD – 1.7 1.0 Minimum Typical Maximum 150 Units µA µA µA V V V V V NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: Outputs terminated with 50Ω to VDD – 2V. Table 4G. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol VOD ∆VOD VOS ∆VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.04 1.14 Test Conditions Minimum 300 Typical Maximum 600 50 1.24 50 Units mV mV V mV Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. Test Conditions Minimum Typical Fundamental 25 50 7 MHz Maximum Units Ω pF ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 8 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter QA, nQA QA, nQA QA, nQA QA, nQA QBx QBx QC fOUT Output Frequency QC QC QC QDx QDx QDx QE QREFx tsk(b) tsk(pp) tjit(Ø) Bank Skew; NOTE 1, 2 Part-to-Part Skew; NOTE 2, 3 RMS Phase Jitter, (Random); NOTE 5 QREFx QREFx QREFx QE Using PCLK, nPCLK Using PCLK, nPCLK 25MHz (10kHz to 5MHz) 125MHz (1.875MHz to 20MHz) 133.33MHz; NOTE 6 100MHz; NOTE 7 QA, nQA 133.33MHz; NOTE 8 100MHz; NOTE 9 83.33MHz; NOTE 10 50MHz; NOTE 6 50MHz; NOTE 7 QBx tjit(per) Period Jitter (pk-pk); NOTE 4, 11 QC 50MHz; NOTE 8 50MHz; NOTE 9 50MHz; NOTE 10 133.33MHz; NOTE 6 133.33MHz; NOTE 9 100MHz; NOTE 7 QDx 125MHz; NOTE 8 125MHz; NOTE 10 125MHz; NOTE 6 QE 125MHz; NOTE 8 125MHz; NOTE 9 125MHz; NOTE 10 Continued on next page. 0.637 0.557 115 115 115 115 115 95 95 95 95 95 90 90 95 95 95 90 90 90 90 Test Conditions DDR_SEL[1:0] = 00 DDR_SEL[1:0] = 01 DDR_SEL[1:0] = 10 DDR_SEL[1:0] = 11 CORE_SEL = 0 CORE_SEL = 1 PCI_SEL[1:0] = 00 PCI_SEL[1:0] = 01 PCI_SEL[1:0] = 10 PCI_SEL[1:0] = 11 SPI_SEL[1:0] = 00 SPI_SEL[1:0] = 01 SPI_SEL[1:0] = 10 Minimum Typical 133.333 100 83.333 125 50 33.333 133.333 100 66.667 33.333 100 125 80 125 25 25 350 Maximum Units MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 9 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Symbol Parameter Test Conditions 133.33MHz; NOTE 6 100MHz; NOTE 7 Minimum Typical Maximum 30 30 30 30 30 Units ps ps ps ps ps ps ps % % % ms tjit(hper) RMS Half-Period Jitter; NOTE 2, 4 QA, nQA 133.33MHz; NOTE 8 100MHz; NOTE 9 83.33MHz; NOTE 10 QA, nQA tR / tF Output Rise/Fall Time QBx, QC, QDx, QE, QREFx QA, nQA odc Output Duty Cycle QBx, QC, QE, QREFx QDx tLOCK Lock Time 10% to 90% 150 200 48 48 48 350 900 52 52 52 55 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at maximum fOUT, unless noted otherwise. NOTE: All parameters are characterized using crystal input, unless noted otherwise. NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF. NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_REF/2. NOTE 4: This parameter is measured at the crosspoint for differential and VDDO_X /2 single-ended signals. NOTE 5: Refer to the phase noise plot. NOTE 6: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz. NOTE 7: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = OFF, QDx = 100MHz, QE = OFF and QREFx = 25MHz. NOTE 8: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz. NOTE 9: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz. NOTE 10: DDR_SEL[1:0] = 10: QA, nQA = 83.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz. NOTE 11: This parameter is measured at 10K cycles. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 10 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Typical Phase Noise at 125MHz (QE output) Noise Power dBc Hz Offset Frequency (Hz) ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 11 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Typical Phase Noise at 25MHz (QREF output) Noise Power dBc Hz Offset Frequency (Hz) ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 12 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information 1.65V±5% 1.65V±5% 2.05V±5% 1.25V±5% 2.05V±5% VDD, VDDO_X VDDA SCOPE VDD SCOPE VDDO_X VDDA Qx Qx GND GND -1.65V±5% -1.25V±5% 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit 2V 2V 3.3V Core/2.5V LVCMOS Output Load AC Test Circuit VDD VDDA Qx SCOPE 3.3V±5% POWER SUPPLY + Float GND – SCOPE VDD VDDA Qx LVPECL nQx GND nQx -1.3V±0.165V 3.3V Core/3.3V LVPECL Output Load AC Test Circuit 3.3V Core/3.3V LVDS Output Load AC Test Circuit VDD Part 1 V DDO_X nPCLK V PP QREFx Cross Points V 2 Part 2 V DDO_X CMR PCLK QREFy GND 2 t sk(pp) Differential Input Level LVCMOS Part-to-Part Skew ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 13 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information, continued VOH nQA VREF VOL QA t half period n ➤ 1 fo t jit (pk-pk) Reference Point (Trigger Edge) Histogram t jit(hper) = t half period n — 1 Mean Period (First edge after trigger) 10,000 cycles Period Jitter, Peak-to-Peak Half Period Jitter nQA QA QBx, QC, QDx, QE, QREFx t PW t PERIOD t PW t PERIOD odc = t PW t PERIOD x 100% odc = t PW t PERIOD Differential Output Duty Cycle/Pulse Width/Period LVCMOS Output Duty Cycle/Pulse Width/Period Phase Noise Plot Noise Power VDDO_X 2 QREF{0:2] QREF{0:2] VDDO_X 2 t sk(b) f1 Offset Frequency f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter LVCMOS Bank Skew ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 14 ©2011 Integrated Device Technology, Inc. ➤ ➤ ➤ t half period n+1 ➤ ➤ 2*fo V DDO_X 2 x 100% ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Parameter Measurement Information, continued nQA nQA 90% 90% VOD 10% QA 90% 90% VSW I N G 10% tF QA 10% tR tF 10% tR LVDS Output Rise/Fall Time LVPECL Output Rise/Fall Time 90% QBx, QC, QDx, QE, QREFx 90% 10% tR tF 10% LVCMOS Output Rise/Fall Time Lock Time VDD VDD out ➤ DC Input LVDS out ➤ out Offset Voltage Setup Differential Output Voltage Setup ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 15 ©2011 Integrated Device Technology, Inc. ➤ VOS/∆ VOS ➤ DC Input LVDS 100 VOD/∆ VOD ➤ out ➤ ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Applications Information Recommendations for Unused Input and Output Pins Inputs: PCLK/nPCLK Inputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. Outputs: LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. The unused LVDS output pair can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 16 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 3.3V LVPECL Differential Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. The differential signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V R3 84 Zo = 50Ω C1 PCLK Zo = 50Ω C2 nPCLK R5 100 - 200 R6 100 - 200 R1 125 R2 125 Zo = 50Ω R4 84 3.3V Zo = 50Ω 3.3V 3.3V R3 125Ω R4 125Ω PCLK 3.3V LVPECL LVPECL Input nPCLK LVPECL R1 84Ω R2 84Ω LVPECL Input Figure 2A. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2B. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V Zo = 50Ω C1 PCLK R5 100Ω Zo = 50Ω C2 VBB nPCLK R1 1k R2 1k Zo = 60Ω Zo = 60Ω 2.5V 2.5V 3.3V R3 120Ω R4 120Ω PCLK LVDS LVPECL Input SSTL nPCLK R1 120Ω C3 0.1µF R2 120Ω LVPECL Input Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVDS Driver Figure 2D. PCLK/nPCLK Input Driven by a 3.3V SSTL Driver 3.3V 3.3V 3.3V R1 50Ω Zo = 50Ω PCLK Zo = 50Ω nPCLK R2 50Ω CML LVPECL Input Figure 2E. PCLK/nPCLK Input Driven by a CML Driver ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 17 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. VCC XTAL_OUT R1 100 Ro Rs Zo = 50 ohms C1 XTAL_IN R2 100 .1uf Zo = Ro + Rs LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT Zo = 50 ohms C2 XTAL_IN Zo = 50 ohms .1uf LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 18 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential output pair is low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input LVPECL Zo = 50Ω R1 84Ω R2 84Ω _ Input Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination LVDS Driver Termination A general LVDS interface is shown in Figure 5. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 5 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver 100Ω LVDS Receiver – 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 19 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. SOLDER PIN EXPOSED HEAT SLUG SOLDER PIN SOLDER PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 20 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Application Schematic Figure 7 shows an example of ICS8430S10I-03 application schematic. In this example, the device is operated at VDD = VDDA = VDDO_B = VDDO_CD = VDDO_E = VDDO_REF = 3.3V. An 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 18pF and C2 = 18pF are recommended for frequency accuracy. Depending on the parasitics of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2. For this device, the crystal load capacitors are required for proper operation. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8430S10I-03 provides separate power supplies to isolate from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. QREF0 R1 Zo = 50 27 Receiv er Logic Control Input Examples VDD RU1 1K RU2 Not Install VDDO_REF LVDS_SEL nOE_E Set Logic Input to '1' VDD Set Logic Input to '0' VDDO To Logic Input pins RD1 Not Install RD2 1K To Logic Input pins QE U1 VDD 48 47 46 45 44 43 42 41 40 39 38 37 R2 Zo = 50 27 Receiv er C1 18pF X1 25MHz8 p F 1 C2 18pF VDD R3 125 R4 125 nOE_D nPLL_SEL XTAL_IN XTAL_OUT nXTAL_SEL nOE_C nOE_B 1 2 3 4 5 6 7 8 9 10 11 12 VDD O_REF nOE_E GN D QR EF0 QR EF1 QR EF2 GN D VDD O_REF LVD S_SEL GN D QE VD D O_E VDD nOE_D GND nPLL_SEL XTAL_IN XTAL_OUT nXTAL_SEL PCLK nPCLK nOE_C nOE_B GND VD D nOE_A SPI_SEL1 SPI_SEL0 PC I_SEL1 PC I_SEL0 D DR _SEL1 D DR _SEL0 nQA QA VD D VD D A VDDO_CD QC QD0 QD1 CORE_SEL GND GND nOE_REF VDDO_B QB0 QB1 VDDO_B 36 35 34 33 32 31 30 29 28 27 26 25 CORE_SEL nOE_REF VDD= VDDO_B = 3.3V VDDO_CD = VDDO_E= VDDO_REF = 3.3V 3.3V R5 133 QA0 Zo = 50 Ohm + nQA0 Zo = 50 Ohm R6 133 nCLK Zo = 50 R7 84 R8 84 13 14 15 16 17 18 19 20 21 22 23 24 LVPECL Driv er nOE_A SPI_SEL1 SPI_SEL0 PCI_SEL1 PCI_SEL0 DDR_SEL1 DDR_SEL0 3.3V 1 C5 0.1uF 3.3V 1 C9 0.1uF 3.3V 1 C14 0.1uF BLM18BB221SN1 2 VDDO_REF (U1:41) Ferrite Bead C6 C7 10uF 0.1uF (U1:48) C8 0.1uF VDDO_REF QA0 49 PAD Zo = 50 CLK VDDA C3 0.01u R9 10 VDD R10 82.5 R11 82.5 C4 10u LVPECL Termination nQA0 QA0 Zo = 50 Ohm + Zo = 50 Ohm R12 100 - BLM18BB221SN2 2 Ferrite Bead C10 VDD (U1:1) C11 10uF 0.1uF (U1:13) (U1:23) VDD C12 0.1uF C13 0.1uF nQA0 BLM18BB221SN3 2 VDDO Ferrite Bead C15 (U1:25) C16 10uF 0.1uF (U1:28) C17 0.1uF (U1:36) (U1:37) C18 0.1uF C19 0.1uF VDDO LVDS Termination Figure 7. ICS8430S10I-03 Schematic Example Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 21 good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Power Considerations (LVCMOS/LVDS Outputs) This section provides information on power dissipation and junction temperature for the ICS8430S10I-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430S10I-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVDS Output Power Dissipation • Power (core, LVDS) = VDD_MAX * (IDD + IDDA) = 3.465V * (150mA + 20mA) = 589.05mW LVCMOS Output Power Dissipation • Dynamic Power Dissipation at 133.33MHz Power (133.33MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133.33MHz * (3.465V)2 = 16mW per output Total Power (133.33MHz) = 16mW * 1 = 16mW Power(125MHz) = 10pF * 125MHz * (3.465V)2 = 15mW per output Total Power (125MHz) = 15mW * 3 = 45mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Power (50MHz) = CPD * Frequency * (VDDO)2 = 10pF * 50MHz * (3.465V)2 = 6mW per output Total Power (50MHz) = 6mW * 2 = 12mW • • Total Power Dissipation • Total Power = Power (core, LVDS) + Total Power (133.33MHz) + Total Power (125MHz) + Total Power (25MHz) + Total Power (50MHz) = 589.05mW + 16mW + 45mW + 9mW + 12mW = 671.05mW ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 22 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.671W * 33.1°C/W = 107.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 7A. Thermal Resistance θJA for 48 Lead TQFP, EPAD Forced Convection θJA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 33.1°C/W 1 27.2°C/W 2.5 25.7°C/W ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 23 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Power Considerations (LVCMOS/LVPECL Outputs) This section provides information on power dissipation and junction temperature for the ICS8430S10I-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430S10I-03 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation • • Power (core)_MAX = VDD_MAX * IEE_MAX = 3.465V * 186mA = 644.49mW Power (output)_MAX = 30mW/Loaded Output Pair LVCMOS Output Power Dissipation • Dynamic Power Dissipation at 133.33MHz Power (133.33MHz) = CPD * Frequency * (VDDO)2 = 10pF * 133.33MHz * (3.465V)2 = 16mW per output Total Power (133.33MHz) = 16mW * 1 = 16mW Power(125MHz) = 10pF * 125MHz * (3.465V)2 = 15mW per output Total Power (125MHz) = 15mW * 3 = 45mW Dynamic Power Dissipation at 25MHz Power (25MHz) = CPD * Frequency * (VDDO)2 = 10pF * 25MHz * (3.465V)2 = 3mW per output Total Power (25MHz) = 3mW * 3 = 9mW Power (50MHz) = CPD * Frequency * (VDDO)2 = 10pF * 50MHz * (3.465V)2 = 6mW per output Total Power (50MHz) = 6mW * 2 = 12mW • • Total Power Dissipation • Total Power = Power (core, LVPECL) + Total Power (133.33MHz) + Total Power (125MHz) + Total Power (25MHz) + Total Power (50MHz) = 644.49mW + 16mW + 45mW + 9mW + 12mW = 726.49mW ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 24 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 33.1°C/W per Table 7B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.727W * 33.1°C/W = 109.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board. Table 7B. Thermal Resistance θJA for 48 Lead TQFP, EPAD Forced Convection θJA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 33.1°C/W 1 27.2°C/W 2.5 25.7°C/W ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 25 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. The LVPECL output driver circuit and termination are shown in Figure 8. VDD Q1 VOUT RL 50Ω VDD - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VDD – 2V. • • For logic high, VOUT = VOH_MAX = VDD_MAX – 0.9V (VDD_MAX – VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VDD_MAX – 1.7V (VDD_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/RL] * (VDD_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/RL] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/RL] * (VDD_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 26 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Reliability Information Table 8. θJA vs. Air Flow Table for a 48 Lead TQFP, EPAD θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 33.1°C/W 1 27.2°C/W 2.5 25.7°C/W Transistor Count The transistor count for ICS8430S10I-03 is: 9,291 ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 27 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Package Outline and Package Dimensions Package Outline - Y Suffix for 48 Lead TQFP, EPAD -HD VERSION EXPOSED PAD DOWN 0.20 TAB -TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR Table 9. Package Dimensions 48L TQFP, EPAD JEDEC Variation: ABC - HD All Dimensions in Millimeters Minimum Nominal Maximum 48 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 9.00 Basic 7.00 Basic 5.50 Ref. 3.5 0.5 Basic 0.45 0.60 0.75 0° 7° 0.08 Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L θ ccc Reference Document: JEDEC Publication 95, MS-026 ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 28 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Ordering Information Table 10. Ordering Information Part/Order Number 8430S10BYI-03LF 8430S10BYI-03LFT Marking ICS0S10BI03L ICS0S10BI03L Package “Lead-Free” 48 TQFP, EPAD “Lead-Free” 48 TQFP, EPAD Shipping Packaging Tray 1000 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 29 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS Revision History Sheet Rev A Table T6 Page 9 14 Description of Change AC Characteristics Table - deleted Cycle-to-Cycle Jitter specs. Parameter Measurement Information, deleted Cycle-to-Cycle Jitter diagrams. Date 2/22/11 ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011 30 ©2011 Integrated Device Technology, Inc. ICS8430S10I-03 Data Sheet CLOCK GENERATOR FOR CAVIUM PROCESSORS We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.