8536AG-02T

Low Skew, 1-to-6, Dual Crystal/LVCMOS-to3.3V, 2.5V LVPECL Fanout Buffer ICS8536-02 DATA SHEET General Description The ICS8536-02 is a low skew, high performance 1-to-6, Dual Crystal or LVCMOS Input-to-3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-02 has selectable crystal or single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVPECL levels. The output enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8536-02 ideal for those applications demanding well defined performance and repeatability. Features • • • • • • • • • • • • Six 3.3V, 2.5V differential LVPECL output pairs Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input Maximum output frequency: 266MHz Crystal frequency range: 14MHz – 40MHz Output skew: 55ps (maximum) Part-to-part skew: 500ps (maximum) Propagation delay: 1.85ns (maximum), 3.3V Additive phase jitter, RMS: 0.149ps (typical) Full 3.3V or 2.5V supply modes 0°C to 70°C ambient operating temperature Industrial temperature information available upon request Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Block Diagram CLK_EN Pullup D Q CLK_SEL0 Pulldown CLK_SEL1 Pulldown LE Pin Assignment nQ2 Q2 VCC nQ1 Q1 VEE nQ0 Q0 CLK_SEL0 XTAL_IN0 XTAL_OUT0 CLK_EN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 VCC Q4 nQ4 VCC Q5 nQ5 CLK_SEL1 XTAL_OUT1 XTAL_IN1 CLK0 XTAL_IN0 OSC XTAL_OUT0 XTAL_IN1 00 Q0 nQ0 6 LVPECL Outputs OSC XTAL_OUT1 CLK0 Pulldown 01 Q5 1X nQ5 ICS8536-02 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View ICS8536AG-02 REVISION A JULY 21, 2010 1 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Table 1. Pin Descriptions Number 1, 2 3, 19, 22 4, 5 6 7, 8 9, 16 10, 11 12 13 14, 15 17, 18 20, 21 23, 24 Name nQ2, Q2 VCC nQ1, Q1 VEE nQ0, Q0 CLK_SEL0, CLK_SEL1 XTAL_IN0, XTAL_OUT0 CLK_EN CLK0 XTAL_IN1, XTAL_OUT1 nQ5, Q5 nQ4, Q4 nQ3, Q3 Output Power Output Power Output Input Input Input Input Input Output Output Output Pullup Pulldown Pulldown Type Description Differential output pair. LVPECL interface levels. Power supply pins. Differential output pair. LVPECL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B. Parallel resonant crystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, the outputs are disabled. LVCMOS / LVTTL interface levels. See Table 3A. Single-ended clock input. LVCMOS/LVTTL interface levels. Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ ICS8536AG-02 REVISION A JULY 21, 2010 2 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Function Tables Table 3. Control Input Function Table Inputs CLK_EN 0 0 0 1 1 1 CLK_SEL1 0 0 1 0 0 1 CLK_SEL0 0 1 X 0 1 X Selected Source XTAL0 XTAL1 CLK0 XTAL0 XTAL1 CLK0 Q[0:5] Disabled Disabled Disabled Enabled Enabled Enabled Outputs nQ[0:5] Disabled Disabled Disabled Enabled Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the selected clock input. Disabled Enabled CLK0, XTAL0, XTAL1 CLK_EN nQ[0:5] Q[0:5] Figure 1. CLK_EN Timing Diagram ICS8536AG-02 REVISION A JULY 21, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI XTAL_IN Other Input Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V 0V to VCC -0.5V to VCC + 0.5V 50mA 100mA 87.8°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 89 Units V mA Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 84 Units V mA Table 4C. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C Symbol VIH Parameter Input High Voltage Test Conditions VCC = 3.3V VCC = 2.5V Input Low Voltage Input High Current CLK0, CLK_SEL[0:1] CLK_EN CLK0, CLK_SEL[0:1] IIL Input Low Current CLK_EN VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V -5 -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 5 Units V V V V µA µA µA µA VIL IIH ICS8536AG-02 REVISION A JULY 21, 2010 4 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VC C – 1.4 VCC – 2.0 0.6 Typical Maximum VCC – 0.9 VCC – 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Table 4E. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC – 1.4 VCC – 2.0 0.4 Typical Maximum VCC – 0.9 VCC – 1.5 1.0 Units V V V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. Table 5. Crystal Characteristics Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NOTE: Characterized using an 18pF parallel resonant crystal. 14 Test Conditions Minimum Typical Fundamental 40 50 7 MHz Maximum Units Ω pF ICS8536AG-02 REVISION A JULY 21, 2010 5 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER AC Electrical Characteristics Table 6A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol fOUT tPD tjit tsk(o) tsk(pp) t R / tF odc MUX_ISOLATION Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; NOTE 2 Output skew; NOTE 3, 4 Part-to-Part skew; NOTE 4, 5 Output Rise/Fall Time Output Duty Cycle MUX Isolation; NOTE 6 ƒ = 150MHz ƒ = 250MHz 20% to 80% 200 47 48 45 155.52MHz, Integration Range: 12kHz – 20MHz 1.35 0.149 55 500 700 53 Test Conditions Minimum Typical Maximum 266 1.85 Units MHz ns ps ps ps ps % dB dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point. NOTE 2: Driving CLK0 input. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: Measured on either XTAL0 or XTAL1 when single-ended CLK0 switching at 150MHz or 250MHz. Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol fOUT tPD tjit tsk(o) tsk(pp) t R / tF odc MUX_ISOLATION Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; NOTE 2 Output skew; NOTE 3, 4 Part-to-Part skew; NOTE 4, 5 Output Rise/Fall Time Output Duty Cycle MUX Isolation; NOTE 6 ƒ = 150MHz ƒ = 250MHz 20% to 80% 200 47 40 40 155.52MHz, Integration Range: 12kHz – 20MHz 1.4 0.149 55 500 700 53 Test Conditions Minimum Typical Maximum 266 1.9 Units MHz ns ps ps ps ps % dB dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at fOUT unless noted otherwise. NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point. NOTE 2: Driving CLK0 input. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: Measured on either XTAL0 or XTAL1 when single-ended CLK0 switching at 150MHz or 250MHz. ICS8536AG-02 REVISION A JULY 21, 2010 6 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 155.52MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.149ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator "SMA 100 Generator 9kHz – 6GHz as external input to an Agilent 8133A 3HGz Pulse Generator”. ICS8536AG-02 REVISION A JULY 21, 2010 7 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx SCOPE LVPECL nQx VEE LVPECL nQx VEE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit Par t 1 nQx nQx Qx Qx nQy Qy Par t 2 nQy Qy t sk(pp) t sk(o) Part-to-Part Skew Output Skew nQ[0:5] VCC CLK0 nQ[0:5] Q[0:5] 2 Q[0:5] t PW t PERIOD tPD odc = t PW t PERIOD x 100% Propagation Delay Output Duty Cycle/Pulse Width/Period ICS8536AG-02 REVISION A JULY 21, 2010 8 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Parameter Measurement Information, continued Spectrum of Output Signal Q A0 Amplitude (dB) MUX selects active input clock signal nQ[0:5] 80% 80% VSW I N G MUX_ISOL = A0 – A1 Q[0:5] 20% tR tF 20% A1 MUX selects static input ƒ (fundamental) Frequency Output Rise/Fall Time MUX_ISOLATION Application Information Recommendations for Unused Input and Output Pins Inputs: Crystal Inputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. Outputs: LVPECL Outputs The unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK0 Input For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK0 input to ground. LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS8536AG-02 REVISION A JULY 21, 2010 9 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Crystal Input Interface The ICS8536-02 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. C1 33pF X1 18pF Parallel Crystal XTAL_OUT C2 27pF XTAL_IN Figure 2. Crystal Input Interface Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, 3.3V 3.3V R1 100 Ro ~ 7 Ohm RS Driv er_LVCMOS 43 Zo = 50 Ohm C1 XTAL_IN R2 100 0.1uF XTAL_OUT matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. Cry stal Input Interf ace Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V Zo = 50 Ohm C1 XTAL_IN R1 50 0.1uF XTAL_OUT Zo = 50 Ohm LVPECL R2 50 Cry stal Input Interf ace R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS8536AG-02 REVISION A JULY 21, 2010 10 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input LVPECL Zo = 50Ω R1 84Ω R2 84Ω _ Input Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination ICS8536AG-02 REVISION A JULY 21, 2010 11 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V 2.5V VCCO = 2.5V R1 250 50Ω + R3 250 2.5V VCCO = 2.5V 50Ω + 50Ω 50Ω – – 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 5C. 2.5V LVPECL Driver Termination Example ICS8536AG-02 REVISION A JULY 21, 2010 12 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8536-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8536-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 89mA = 308.385mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.3V, with all outputs switching) = 308.385mW + 180mW = 488.385mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 87.8°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.488W * 87.8°C/W = 112.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resitance θJA for 24 Lead TSSOP, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 87.8°C/W 1 83.5°C/W 2.5 81.3°C/W ICS8536AG-02 REVISION A JULY 21, 2010 13 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 6. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX (VCC_MAX – 2V))/R ] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW L Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS8536AG-02 REVISION A JULY 21, 2010 14 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Reliability Information Table 8. θJA vs. Air Flow Table for a 24 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 87.8°C/W 1 83.5°C/W 2.5 81.3°C/W Transistor Count The transistor count for ICS8536-02 is: 467 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 9. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8536AG-02 REVISION A JULY 21, 2010 15 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER Ordering Information Table 10. Ordering Information Part/Order Number 8536AG-02 8536AG-02T 8536AG-02LF 8536AG-02LFT Marking ICS8536AG-02 ICS8536AG-02 ICS8536AG-02L ICS8536AG-02L Package 24 Lead TSSOP 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8536AG-02 REVISION A JULY 21, 2010 16 ©2010 Integrated Device Technology, Inc. ICS8536-02 Data Sheet 1-TO-6, DUALCRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FANOUT BUFFER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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