8624BYIT

ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER GENERAL DESCRIPTION The ICS8624I is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer. The ICS8624I has two selectable clock input pairs. The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most standard differential input levels. The VCO operates at a frequency range of 250MHz to 630MHz. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 630MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support reduntant clock or multiple reference applications.. FEATURES • Fully integrated PLL • Five differential HSTL compatible outputs • Selectable differential CLKx, nCLKx input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 630MHz • Input frequency range: 31.25MHz to 630MHz • VCO range: 250MHz to 630MHz • External feedback for “zero delay” clock regeneration • Cycle-to-cycle jitter: 35ps (maximum) • Output skew: 50ps (maximum) • Static phase offset: 30ps ±125ps • 3.3V core, 1.8V output operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM Q0 nQ0 PLL_SEL ÷4, ÷8 0 1 1 Q3 nQ3 Q1 nQ1 0 Q2 nQ2 PIN ASSIGNMENT PLL_SEL GND GND VDDO VDDA nQ4 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN 32 31 30 29 28 27 26 25 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD nFB_IN FB_IN GND GND nQ0 Q0 VDDO VDD Q4 24 23 22 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO PLL Q4 nQ4 ICS8624I 21 20 19 18 17 SEL0 SEL1 MR 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View 8624BYI www.idt.com 1 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6 7 Name SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL Input Input Input Input Input Input Input Type Pulldown Pulldown Pulldown Pullup Pulldown Pullup Pulldown Description Determines the input and output frequency range noted in Table 3. LVCMOS / LVTTL interface levels. Determines the input and output frequency range noted in Table 3. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Core supply pins. Feedback input to phase detector for regenerating clocks with "zero delay". Feedback input to phase detector for regenerating clocks with "zero delay". Power supply ground. Differential clock outputs. 50Ω typical output impedance. HSTL interface levels. Output supply pins. Differential clock outputs. 50Ω typical output impedance. HSTL interface levels. Differential clock outputs. 50Ω typical output impedance. HSTL interface levels. Differential clock outputs. 50Ω typical output impedance. HSTL interface levels. Differential clock outputs. 50Ω typical output impedance. HSTL interface levels. Analog supply pin. Selects between the PLL and clock as the input to the dividers. Pullup When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values. 8 9, 32 10 11 12, 13 28, 29 14, 15 16, 17, 24, 25 18, 19 20, 21 22, 23 26, 27 30 31 MR VDD nFB_IN FB_IN GND nQ0, Q0 VDDO nQ1, Q1 nQ2, Q2 nQ3, Q3 nQ4, Q4 VDDA PLL_SEL Input Power Input Input Power Output Power Output Output Output Output Power Input Pulldown Pullup Pulldown NOTE 1: Pullup and Pulldown refer 8624BYI www.idt.com 2 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Reference Frequency Range (MHz)* 250 - 630 125 - 315 62.5 - 157.5 31.25 - 78.75 Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q4, nQ0:nQ4 ÷1 ÷1 ÷1 ÷1 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. TABLE 3B. PLL BYPASS FUNCTION TABLE Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q4, nQ0:nQ4 ÷4 ÷4 ÷4 ÷8 8624BYI www.idt.com 3 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 50mA 100mA 47.9°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current No Load 0 Test Conditions Minimum 3.135 3.135 1.6 Typical 3.3 3.3 1.8 Maximum 3.465 3.465 2.0 120 15 Units V V V mA mA mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current SEL0, SEL1, CLK_SEL, MR PLL_SEL SEL0, SEL1, CLK_SEL, MR PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V µA µA µA µA IIL Input Low Current TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 0.5 VCMR NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8624BYI www.idt.com 4 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER TABLE 4D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol VOH VOL VOX Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2 Test Conditions Minimum 1.0 0 40 0.6 Typical Maximum 1.4 0.4 60 1.1 Units V V % V VSWING Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 630 630 Units MHz MHz TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol fMAX tPD t(Ø) Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter; NOTE 5, 6 Phase Jitter; NOTE 4, 5, 6 PLL Lock Time Output Rise Time Output Fall Time 20% to 80% 20% to 80% 300 300 ƒ ≤ 630MHz PLL_SEL = 3.3V 3.4 -95 3.9 30 Test Conditions Minimum Typical Maximum 630 4.5 155 50 35 ±50 1 700 700 Units MHz ns ps ps ps ps ms ps ps ps t sk(o) t jit(cc) t jit(Ø) tL tR tF tPW Output Pulse Width tPeriod/2 - 85 tPeriod/2 tPeriod/2+ 85 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Cycle-to-Cycle Jitter; NOTE 1 Test Conditions Minimum Typical Maximum 40 Units ps t jit(cc) NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. 8624BYI www.idt.com 5 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V±5% or 10% 1.8V±0.2V VDD VDD, VDDA Qx SCOPE nCLK0, nCLK1 VDDO HSTL nQx V CLK0, CLK1 PP Cross Points V CMR G ND GND = 0V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx nQ nQy Qy nQx Qx tcycle n ➤ t sk(o) t jit(cc) = tcycle n –tcycle n+1 1000 Cycles OUTPUT SKEW nCLK0, nCLK1 CLK0, CLK1 nFB_IN FB_IN ➤ t (Ø) VOH VOL VOH VOL CYCLE-TO-CYCLE JITTER 80% Clock Outputs 20% tR tF t jit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) PHASE JITTER nQ0:nQ4 Q0:Q4 AND STATIC PHASE OFFSET VDDO 2 VDDO 2 OUTPUT RISE/FALL TIME nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4 VDDO 2 Pulse Width t PERIOD tPD OUTPUT PULSE WIDTH/PERIOD 8624BYI PROPAGATION DELAY www.idt.com 6 REV. C JULY 30, 2010 ➤ ➤ ➤ tcycle n+1 ➤ 80% VOD 20% ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8624I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω r esistor along with a 10 μ F and a .01 μ F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF VDDA .01μF 10μ F 10 Ω FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8624BYI www.idt.com 7 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. HSTL OUTPUT All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LAYOUT GUIDELINE The schematic of the ICS8624I layout example is shown in Figure 3A. The ICS8624I recommended PCB board layout for this example is shown in Figure 3B. This layout example is used as a general guideline. The layout in the actual system VDD will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. SP = Space (i.e. not intstalled) VDDA RU2 SP RU3 1K RU4 1K RU5 SP R7 10 VDD VDD=3.3V CLK_SEL PLL_SEL SEL0 SEL1 C11 0.01u VDDO=1.8V DIV_SEL[1:0] = 01 PLL_SEL C16 10u 155.5 MHz Zo = 50 Ohm + RD2 1K RD3 SP RD4 SP RD5 1K VDD VDDO Zo = 50 Ohm - LVHSTL_input U1 3.3V 32 31 30 29 28 27 26 25 (155.5 MHz) Zo = 50 Ohm SEL0 SEL1 Zo = 50 Ohm CLK_SEL 3.3V PECL Driver R8 50 R9 50 1 2 3 4 5 6 7 8 VDD PLL_SEL VDDA GND GND Q4 nQ4 VDDO R4A 50 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO 24 23 22 21 20 19 18 17 R4B 50 VDD nFB_IN FB_IN GND GND nQ0 Q0 VDDO SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK2 CLK_SEL MR Bypass capacitor located near the power pins (U1-9) VDD C1 0.1uF (U1-32) C6 0.1uF 9 10 11 12 13 14 15 16 8624 R10 50 R2B 50 R2A 50 (U1-16) C2 0.1uF VDDO (U1-17) C4 0.1uF (U1-24) C5 0.1uF (U1-25) C7 0.1uF FIGURE 3A. ICS8624I HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE 8624BYI www.idt.com 8 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The differential 50Ω output traces should have same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. • Make sure no other signal traces are routed between the clock trace pair. • The matching termination resistors should be located as close to the receiver input pins as possible. POWER AND GROUNDING Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the GND R7 C16 C11 C7 C6 C5 VDDO VDD VDDA U1 Pin 1 VIA 50 Ohm Traces C4 C1 C2 FIGURE 3B. PCB BOARD LAYOUT FOR ICS8624I 8624BYI www.idt.com 9 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8624I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8624I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 32.8mW = 164mW Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 164mW = 631.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.632W * 42.1°C/W = 111.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8624BYI www.idt.com 10 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. VDDO Q1 VOUT RL 50Ω FIGURE 4. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V OH_MIN /R ) * (V L DDO_MAX -V -V DDO_MAX ) ) OL_MAX OH_MIN Pd_L = (V OL_MAX /R ) * (V L Pd_H = (1V/50Ω) * (2V - 1V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW 8624BYI www.idt.com 11 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8624I is: 1565 8624BYI www.idt.com 12 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 9. PACKAGE DIMENISIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L θ 0.45 0° 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.60 0.75 7° 0.10 REV. C JULY 30, 2010 MINIMUM NOMINAL 32 MAXIMUM 1.60 0.15 1.40 0.37 1.45 0.45 0.20 ccc Reference Document: JEDEC Publication 95, MS-026 8624BYI www.idt.com 13 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number 8624BYI 8624BYIT 8624BYILF 8624BYILFT Marking ICS8624BYI ICS8624BYI ICS8624BYILF ICS8624BYILF Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments 8624BYI www.idt.com 14 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER REVISION HISTORY SHEET Rev A T1 T3A A T4A 4 13 T2 B T4D T6B 3 4 5 5 1 8 10-11 14 14 16 Table Page 11 - 12 2 3 Description of Change Revised Figures 3A & 3B. Pin Description Table - revised VDD description to Core supply pins from Positive supply pins. Control Input Function Table - corrected note to read ...250MHz to 630MHz from ...250 to 700MHz. Power Supply Table - revised VDD Parameter description to read Core Supply Voltage from Positive Supply Voltage. Corrected power dissipation equation. Replaced VOH_MIN with VOH_MAX. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - updated Output rating. HSTL DC Characteristics Table - changed VOX to 40% min. - 60% max. and added note. Added Table 6B AC Characteristics Table with VDD = VDDA = 3.3V±10%. Changed LVHSTL to HSTL throughout the data sheet. Added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. Ordering Information Table - added lead-free par t number and note. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Par t/Order Number column. Added Contact Page. Date 8/13/02 10/8/02 2/19/04 B T10 C T10 11/15/05 7/30/10 8624BYI www.idt.com 15 REV. C JULY 30, 2010 ICS8624I LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8624BYI www.idt.com 16 REV. C JULY 30, 2010