874003AG-04LF

PCI EXPRESS™ Jitter Attenuator ICS874003-04 DATA SHEET General Description The ICS874003-04 is a high performance Differential-to-LVDS Jitter Attenuator designed for use HiPerClockS™ in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-04 has a bandwidth of 6.8MHz. The 6.8MHz provides a high bandwidth that can easily track triangular spread profiles, while providing jitter attenuation. Features • • • • • • • • • • • Three differential LVDS output pairs One differential clock input CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Input frequency range: 98MHz to 128MHz Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Supports PCI-Express Spread-Spectrum Clocking High PLL bandwidth allows for better input tracking Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS The ICS874003-04 uses IDT’s 3rd Generation FemtoClock™ PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. Pin Assignment F_SEL[2:0] Function Table Inputs F_SEL2 0 1 0 1 0 1 0 1 F_SEL1 0 0 1 1 0 0 1 1 F_SEL0 0 0 0 0 1 1 1 1 Outputs QA[0:1], nQA[0:1] ÷2 ÷5 ÷4 ÷2 ÷2 ÷5 ÷4 ÷4 QB, nQB0 ÷2 ÷2 ÷2 ÷4 ÷5 ÷4 ÷5 ÷4 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003-04 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS874003AG-04 REVISION A NOVEMBER 4, 2009 1 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Block Diagram OEA Pullup F_SEL2:0 Pulldown 3 QA0 ÷5 ÷4 ÷2 (default) CLK Pulldown nQA0 QA1 nCLK Pullup Phase Detector VCO 490 - 640MHz 3 nQA1 M = ÷5 (fixed) ÷5 ÷4 ÷2 (default) QB0 nQB0 MR Pulldown OEB Pullup ICS874003AG-04 REVISION A NOVEMBER 4, 2009 2 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number 1, 20 2, 19 3, 4 Name QA1, nQA1 VDDO QA0, nQA0 Output Power Output Type Description Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Frequency select pin for QAx, nQAx and QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pin. Pullup Pulldown Pullup Output enable pin for QA pins. When HIGH, the QAx, nQAx outputs are active. When LOW, the QAx, nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active. When LOW, the QB0, nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. 5 MR Input Pulldown 6, 9, 16 7 8 10 11 12 13 14 15 17, 18 F_SEL0, F_SEL1, F_SEL2 nc VDDA VDD OEA CLK nCLK GND OEB nQB0, QB0 Input Unused Power Power Input Input Input Power Input Output Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF kΩ kΩ Table 3. Output Enable Function Table Inputs OEx 0 1 Outputs Qx[0:1], nQx[0:1] Hi-Impedance Enabled ICS874003AG-04 REVISION A NOVEMBER 4, 2009 3 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 86.7°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD – 0.16 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 74 16 76 Units V V V mA mA mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage OEA, OEB Input High Current F_SEL0, F_SEL1, F_SEL2, MR OEA, OEB IIL Input Low Current F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V µA µA µA µA ICS874003AG-04 REVISION A NOVEMBER 4, 2009 4 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol IIH Parameter CLK Input High Current nCLK CLK IIL Input Low Current nCLK VPP VCMR Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD – 0.85 Minimum Typical Maximum 150 5 Units µA µA µA µA V V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol VOD ∆VOD VOS ∆VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.20 1.35 Test Conditions Minimum 275 Typical 375 Maximum 485 50 1.50 50 Units mV mV V mV Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol fMAX tjit(cc) tsk(o) tsk(b) tR / tF odc Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE 1 Output Skew; NOTE 1, 2 Bank Skew; NOTE 1, 3 Output Rise/Fall Time Output Duty Cycle Bank A 20% to 80% 215 47 Test Conditions Minimum 98 Typical Maximum 320 35 135 50 550 53 Units MHz ps ps ps ps % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ICS874003AG-04 REVISION A NOVEMBER 4, 2009 5 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – nCLK V PP VDD, VDDO Qx CLK Cross Points V CMR DDA LVDS V nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQA0 QA0 nQA1 QA1 nQAx, nQB0 QAx, QB0 t cycle n ➤ t jit(cc) = |t cycle n – t cycle n+1| 1000 Cycles t sk(b) Bank Skew Cycle-to-Cycle Jitter nQx Qx nQy Qy nQAx, nQB0 QAx, QB0 t PW t PERIOD t sk(o) odc = t PW t PERIOD Output Skew Output Duty Cycle/Pulse Width/Period ICS874003AG-04 REVISION A NOVEMBER 4, 2009 6 ©2009 Integrated Device Technology, Inc. ➤ ➤ t cycle n+1 ➤ x 100% ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VDD nQAx, nQB0 80% 80% VOD DC Input out ➤ QAx, QB0 20% tR tF 20% LVDS out ➤ VOS/∆ VOS ➤ Output Rise/Fall Time Offset Voltage Setup VDD ➤ ➤ out DC Input LVDS ➤ 100 VOD/∆ VOD out Differential Output Voltage Setup ICS874003AG-04 REVISION A NOVEMBER 4, 2009 7 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The ICS874003-04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF VDDA .01µF 10µF 10Ω Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input ICS874003AG-04 REVISION A NOVEMBER 4, 2009 8 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK Zo = 50Ω Zo = 50Ω nCLK nCLK CLK 3.3V LVPECL HiPerClockS Input R1 50 R2 50 HiPerClockS Input LVHSTL IDT HiPerClockS LVHSTL Driver R1 50 R2 50 R2 50 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V Zo = 50Ω CLK Zo = 50Ω nCLK Zo = 50Ω R1 100 nCLK CLK R3 125 R4 125 3.3V Zo = 50Ω 3.3V LVPECL R1 84 R2 84 HiPerClockS Input LVDS Receiver Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 2.5V 3.3V 2.5V Zo = 60Ω CLK Zo = 50Ω nCLK Zo = 60Ω CLK R3 120 R4 120 3.3V *R3 33 Zo = 50Ω nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input SSTL R1 120 R2 120 HiPerClockS *Optional – R3 and R4 can be 0Ω Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver ICS874003AG-04 REVISION A NOVEMBER 4, 2009 9 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V 50Ω LVDS Driver R1 100Ω + – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ICS874003AG-04 REVISION A NOVEMBER 4, 2009 10 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Schematic Example Figure 5 shows an example of ICS874003-04 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. Two examples of LVDS terminations are shown in this schematic. The input is driven either by a 3.3V LVPECL driver or a 3.3V LVCMOS. ICS874003-04 Figure 5. ICS874003-04 Schematic Example ICS874003AG-04 REVISION A NOVEMBER 4, 2009 11 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS874003-04. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS74003-04 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (74mA + 16mA) = 311.85mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 76mA = 263.34mW Total Power_MAX = 311.85mW + 263.34mW = 575.19mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.575W * 86.7°C/W = 119.9°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 86.7°C/W 1 82.4°C/W 2.5 80.2°C/W ICS874003AG-04 REVISION A NOVEMBER 4, 2009 12 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 86.7°C/W 1 82.4°C/W 2.5 80.2°C/W Transistor Count The transistor count for ICS874003-04 is: 1,416 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874003AG-04 REVISION A NOVEMBER 4, 2009 13 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874003AG-04 874003AG-04T 874003AG-04LF 874003AG-04LFT Marking ICS874003A04 ICS874003A04 ICS74003A04L ICS74003A04L Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS874003AG-04 REVISION A NOVEMBER 4, 2009 14 ©2009 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.