87951AYILFT

ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER GENERAL DESCRIPTION The ICS87951I is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Cock Generator. The CS87951I has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87951I contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. FEATURES • Fully integrated PLL • Nine single ended 3.3V LVCMOS/LVTTL outputs • Selectable single ended CLK0 or differential CLK1, nCLK1 inputs • The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels • CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Output frequency range: 25MHz to 180MHz • VCO range: 200MHz to 480MHz • External feedback for ”zero delay” clock regeneration • Cycle-to-cycle jitter: ±100ps (typical) • Output skew: 375ps (maximum) • PLL reference zero delay: 350ps window (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages PIN ASSIGNMENT CLK_SEL PLL_SEL CLK0 GND GND VDDO QB QA 32 31 30 29 28 27 26 25 VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nCLK1 MR/nOE VDDO QD4 GND QD3 VDDO QD2 24 23 22 QC0 VDDO QC1 GND QD0 VDDO QD1 GND ICS87951I 21 20 19 18 17 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View 87951AYI www.idt.com 1 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER BLOCK DIAGRAM DIV_SELA Internal Pulldown PLL_SEL Internal Pulldown CLK0 Internal Pulldown CLK_SEL Internal Pulldown nCLK1 CLK1 Internal Pulldown/ Pullup 1 0 PHASE DETECTOR VCO 200-480MHz 0 1 ÷2 ÷4 ÷8 0 QA 1 0 LPF 1 EXT_FB Internal Pullup DIV_SELB Internal Pulldown QB 0 1 QC0 QC1 DIV_SELC Internal Pulldown MR/nOE Internal Pulldown POWER-ON RESET 0 1 DIV_SELD Internal Pulldown QD0 QD1 QD2 QD3 QD4 87951AYI www.idt.com 2 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5 6 7, 13, 17, 21, 25, 29 8 9 10 11, 15, 19, 23, 27 12, 14, 16, 18, 20 22, 24 26 28 30 31 32 Name VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 nCLK1 MR/nOE Type Power Input Input Input Input Input Power Input Input Input Pullup Pullup Pulldown Pulldown Pulldown Pulldown Description Analog supply pin. Feedback input to phase detector for regenerating clocks with "zero delay". LVCMOS / LVTTL interface levels. Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. Power supply ground. Non-inver ting differential clock input. Pulldown Inver ting differential clock input. Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated Pulldown (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Output supply pins. Bank D clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank B clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL phase detector reference clock input. Selects between the PLL and the reference clock as the input to the Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. VDDO QD4, QD3, QD2, QD1, QD0 QC1, QC0 QB QA CLK0 PLL_SEL CLK_SEL Power Output Output Output Output Input Input Input NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 5 VDDA, VDDO = 3.47V Test Conditions Minimum Typical 4 25 51 51 7 12 Maximum Units pF pF KΩ KΩ Ω 87951AYI www.idt.com 3 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Inputs MR/nOE 1 0 QA HiZ Enabled QB HiZ Enabled Outputs QC0, QC1 HiZ Enabled QD0:QD4 HiZ Enabled TABLE 3B. OPERATING MODE FUNCTION TABLE Inputs PLL_SEL 0 1 Operating Mode Bypass PLL TABLE 3C. PLL INPUT FUNCTION TABLE Inputs CLK_SEL 0 1 PLL Input CLK1, nCLK1 CLK0 TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE Inputs DIV_SELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DIV_SELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DIV_SELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIV_SELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 QB VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 Outputs QCx VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 QDx VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 87951AYI www.idt.com 4 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, θJA Storage Temperature, TSTG 4.6V -0.5V to VDDA + 0.5 V -0.5V to VDDO + 0.5V 42.1°C/W (0 lfpm) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol VDDA VDDO IDDO IDDA Parameter Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current All VDD pins Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 115 20 Units V V mA mA TABLE 4B. DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE Test Conditions Minimum 2 2 -0.3 -0.3 300 GND + 0.5 IOH = -40mA IOL = 40mA 2.4 0.5 ±120 Typical Maximum VDD + 0.3 VDD + 0.3 1.3 0.8 1000 VDD - 0.85 Units V V V V mV V V V µA VIH Input High Voltage VIL Input Low Voltage VPP VCMR VOH VOL Peak-to-Peak CLK1, nCLK1 Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage Output Low Voltage IIN Input Current NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is VDDA+ 0.3V. 87951AYI www.idt.com 5 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fREF Parameter Input Reference Frequency Test Conditions Minimum Typical Maximum 100 Units MHz TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fMAX fVCO t(Ø) Parameter Output Frequency PLL VCO Lock Range CLK0 Static Phase Offset; CLK1, NOTE 1,3 nCLK1 Output Skew; NOTE 2, 3 fREF = 50MHz, Feedback = VCO/8 Same Frequencies Test Conditions QA ÷2 QA/QB ÷4 QB ÷8 200 -185 -445 15 -265 Minimum Typical Maximum 180 120 60 480 165 -95 375 500 750 ±100 10 0.8 to 2V 0.8 to 2V 0.1 0.1 tcycle/2 - 1000 1.0 1.0 tcycle/2 + 1000 6 7 Units MHz MHz MHz MHz ps ps ps ps ps ps mS ns ns ps ns ns tsk(o) Different Frequencies QAfMAX < 150MHz QAfMAX > 150MHz tjit(cc) tLOCK tR tF tPW tPZL tPLZ, tPHZ Cycle-to-Cycle Jitter ; NOTE 3 PLL Lock Time; NOTE 3 Output Rise Time Output Fall Time Output Pulse Width Output Enable Time Output Disable Time All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 87951AYI www.idt.com 6 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% V DD VDDA, VDDO SCOPE nCLK1 Qx V PP LVCMOS GND Cross Points V CMR CLK1 GND -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL V DDO V DDO V DDO V tcycle n ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER 2V 0.8V tR Clock Outputs ➤ t (Ø) OUTPUT RISE/FALL TIME VDDO VDDO 2 t PW t PERIOD VDDO 2 tjit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) QA, QB, QCx, QDx 2 odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 87951AYI PHASE JITTER www.idt.com 7 AND ➤ ➤ ➤ QA, QB, QCx, QDx 2 2 2 DDO Qx 2 tcycle n+1 ➤ V Qy DDO 2 t sk(o) OUTPUT SKEW nCLK1 VOH VOL VOH VDDO 2V CLK0, CLK1 0.8V tF EXT_FB VOL 2 STATIC PHASE OFFSET REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. F igure 2 i llustrates how a 10 Ω r esistor along with a 10 μ F and a .01 μ F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF VDDA .01 μF 10μF 10 Ω FIGURE 2. POWER SUPPLY FILTERING 87951AYI www.idt.com 8 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK1 /nCLK1 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK1/nCLK1 input driven by the most common driver types. The input interfaces suggested 3.3V 1.8V Zo = 50 Ohm here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 3C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 87951AYI LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. www.idt.com 9 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87951I is: 2674 87951AYI www.idt.com 10 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L θ ccc 0.45 0° --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7° 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 87951AYI www.idt.com 11 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number 87951AYI 87951AYIT 87951AYILF 87951AYILFT Marking ICS87951AYI ICS87951AYI ICS87951AYIL ICS87951AYIL Package 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuraiton and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 87951AYI www.idt.com 12 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER Rev Table T1 T2 Page 3 3 5 8 9 1 9 12 12 14 REVISION HISTORY SHEET Description of Change Pin Description Table - revised MR/nOE description. Pin Characteristics Table - changed CIN 4pf max. to 4pf typical. Added ROUT row. DC Characteristics - changed VIH CLK0 from 3.6V max to VDD + 0.3V and added VIL CLK0 row. Updated Single Ended Signal Driving Differential Input diagram. Added CLK/nCLK Input Interface section. Features Section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking, and note. Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Date B 7/10/03 11/23/05 T9 C T9 7/17/10 87951AYI www.idt.com 13 REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 87951AYI www.idt.com 14 REV. C JULY 17, 2010