89HP0504PB

4 Channel 5Gbps PCIe® Signal Repeater ® 89HP0504PB Data Sheet Device Overview The IDT 89HP0504PB (P0504PB) is a 5Gbps PCIe® Repeater device featuring IDT EyeBoost™ technology that compensates for cable and board trace attenuations and ISI jitter, thereby extending connection reach. The device is optimized for PCIe Gen1 and Gen2 high speed serial data streams and contains four data channels, each able to process 5Gbps transmission rates. Each channel consists of an input equalizer and amplifier, signal detection with glitch filter, as well as programmable output swing and de-emphasis. Allowing for application specific optimization, the P0504PB, with its configurable receiver and transmitter features, is ideal for PCIe applications using a wide combination of cables and board trace materials. All modes of active data transfer are designed with minimized power consumption. In full shutdown mode, the part consumes less than 40mW in worst case environmental conditions. Features Compensates for cable and PCB trace attenuation and ISI jitter Programmable receiver equalization up to 24db Programmable transmitter swing and de-emphasis Recovers data stream even when the differential signal eye is completely closed due to trace attenuation and ISI jitter Full PCIe protocol support Configurable via external pins Leading edge power minimization in active and shutdown modes No external bias resistors or reference clocks required Channel mux mode, demux mode, 1 to 2 channels multicast, and Z-switch function mode Available in a 36-pin QFN package (4.0 x 7.5mm with 0.5mm pitch) Applications Blade servers, rack servers PCIe instrumentation Storage systems Cabled PCIe devices Benefits Extends maximum cable length to over 8 meters and trace length over 48 inches in PCIe applications Minimizes BER Typical Application Server Backplane Server Chipset PCIe gen1,2 (Trace, eg. FR4) IDT Repeater PCIe gen1,2 (Trace) IDT Repeater PCIe gen1,2 (Trace, eg. FR4) Chipset Figure 1 IDT Repeaters in Blade Servers IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 © 2011 Integrated Device Technology, Inc February 8, 2011 IDT 89HP0504PB Data Sheet PCIe Compliance The device was designed to provide end users with features needed to comply with PCIe system application requirements: – Receiver Detection Support, PCIe Beacon Support – Receiver supports high impedance mode for PCIe – Jitter, eye opening, and all other key AC and DC specifications. Block Diagram The P0504PB contains four high speed channels as shown in Figure 2. Each channel can be routed to different outputs. Depending on user configuration via mode selections, input traffic can be muxed or demuxed. Powerdown (PDB) and Receiver Detection Reset (RSTB) are provided for state and channel control. Figure 2 Block Diagram 2 February 8, 2011 Table of Contents Device Overview ................................................................................................................................ 1 Applications........................................................................................................................................ 1 Features............................................................................................................................................. 1 Benefits .............................................................................................................................................. 1 Typical Application ............................................................................................................................. 1 PCIe Compliance ............................................................................................................................... 2 Block Diagram.................................................................................................................................... 2 Functional Description ....................................................................................................................... 5 Power-Up................................................................................................................................... 6 Power Sequencing..................................................................................................................... 6 IDT EyeBoost™ Technology ..................................................................................................... 6 Eye Diagram Parameters .......................................................................................................... 7 Receiver Impedance.................................................................................................................. 7 Transmitter Impedance.............................................................................................................. 7 PCIe Receiver Detection Support.............................................................................................. 8 Modes of Operation ................................................................................................................... 8 Channel Muxing......................................................................................................................... 9 Electrical Specifications ................................................................................................................... 13 Absolute Maximum Ratings ..................................................................................................... 13 Recommended Operating Conditions...................................................................................... 13 Power Consumption ................................................................................................................ 14 Package Thermal Considerations............................................................................................ 14 DC Specifications .................................................................................................................... 15 AC Specifications..................................................................................................................... 15 Pin Description................................................................................................................................. 20 Package Pinout — 36-QFN Signal Pinout ....................................................................................... 22 Pin Diagram ..................................................................................................................................... 23 QFN Package Dimension ................................................................................................................ 24 Revision History ............................................................................................................................... 25 Ordering Information........................................................................................................................ 26 3 February 8, 2011 IDT 89HP0504PB Data Sheet PAGE INTENTIONALLY LEFT BLANK 4 February 8, 2011 IDT 89HP0504PB Data Sheet Functional Description The P0504PB has 4 channels, each with the individually programmable features listed below. Figure 3 diagrams the channel and Table 1 summarizes key configuration options. Electrical Idle detection with glitch filter Channel power-down Programmable equalizer + _ Input termination 100 ohm Programmable Transmitter De-emphasis: 0 to -6.5dB Voltage swing: 500mV to 950mV 0 to 14dB Up to 10dB Auto-boost Output termination 100 ohm + _ Receiver detection Figure 3 Channel Block Diagram with Channel Features Per-channel programmable features used at the Receive side. – Input equalization with 3 levels: 2 to 14dB compensation for high frequency signal attenuation due to cables and board traces. Additionally, up to 10dB boost is added automatically by the equalizer for applications using long cables. The total equalization range is between 2dB and 24dB. – Input high impedance control via channel enable: disabled (active mode) and hi-Z (power-down). Per-channel programmable features used at the Transmit side. – Output de-emphasis with 8 levels: 0 to -6.5dB. The de-emphasis boosts the magnitude of higher frequencies sent by the transmitter to compensate for high frequency losses travelling through output side cable or output side board traces. This ensures that the final received signal has a wider eye opening. – Output differential swing with 3 levels: 0.5V to 0.95V (peak-to-peak). – Receiver detection: enable or disable. This function is activated following an RSTB pulse. • With receiver detection enabled, if A0 and A1 channels do not detect at least one receiver, then the P0504PB on-chip Rx termination on A0 and A1 is set to hi-Z as shown in Table 2. • With receiver detection enabled, if B0 and B1 channels do not detect at least one receiver, then the P0504PB on-chip Rx termination on B0 and B1 is set to hi-Z as shown in Table 2. – Electrical idle detection: When the incoming differential peak-peak amplitude falls below 110mV, the device enters electrical idle mode and the corresponding transmitter stops toggling, maintains its common mode voltage level, and meets all electrical idle specifications described in the AC Specifications section of this data sheet. In addition, the device contains global configuration of the data path: – Transfer modes: direct connect, cross-connect, multicast. 5 February 8, 2011 IDT 89HP0504PB Data Sheet Power-Up After the power supplies reach their minimum required levels, the P0504PB powers up by setting all input and output pins to known states: All the device's input configuration pins are set internally to VSS or VDD for 2-level pins and to VDD/2 for 3-level pins. High speed differential input and output pins depend on various conditions described below: – High speed differential input and output pins are in high impedance if any of the following conditions is true: • Powerdown is set (PDB pin = 0V) or • No receiver termination was detected at TX outputs In all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impedance. Also refer to Table 4, Power Reducing Modes, Table 2, Receiver Impedance, and Table 3, Transmitter Impedance. The power ramp up time for the P0504PB should be less than 1ms. Power Sequencing There are no power sequencing constraints for the P0504PB. IDT EyeBoost™ Technology IDT EyeBoost™ technology is a method of data stream recovery even when the differential signal eye is completely closed due to cable or trace attenuation and ISI jitter. With IDT EyeBoost™, the system designer can both recover the incoming data and retransmit it to target device with a maximized eye width and amplitude. An example of IDT EyeBoost™ technology usage in a system application and eye diagram results are shown in Figure 4. In this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch FR4 connection from signal source and the (b) diagram shows differential signal at the output of repeater maximized eye opening with IDT EyeBoost™ technology. (a) Figure 4 Eye Diagram (b) 6 February 8, 2011 IDT 89HP0504PB Data Sheet Eye Diagram Parameters Parameter Names for Programming via Pins A0RXEQ, A1RXEQ, B0RXEQ, B1RXEQ Range: 0dB to 14dB (plus additional autoboost up to 10dB for long connections) A0TXSW, A1TXSW, B0TXSW, B1TXSW Range: 0.5V to 0.95V for swing Range: 0 to -6.5dB for de-emphasis Feature Input equalization Feature Type Main eye optimization Output differential signal swing (peak-to-peak) and output de-emphasis Main eye optimization Table 1 Quick Reference: Parameters Used for Eye Optimization Receiver Impedance The table below shows how the receiver impedance changes based on input and output pin states. Mode Full IC Power-down Channel Enabled Channel Enabled Control Inputs PDB [A,B]RXDETEN RSTB Rx Terminations Hi-Z 50Ω 50Ω Description Receiver terminations placed in Hi-Z. Receiver detect disabled. Receiver terminations set to 50Ω. Receiver detect enabled. Valid receiver detected. Receiver terminations set to 50Ω. 0 1 1 X 0 1 X 1 1 Table 2 Receiver Impedance Transmitter Impedance The table below shows how the transmitter impedance changes based on input and output pin states. Mode Full IC Power-down Channel Enabled Control Inputs [A,B]RXDETEN RSTB Tx Terminations 1kΩ 50Ω Description Receiver terminations placed in Hi-Z. Rx signal not detected. Receiver detect disabled. Receiver terminations set to Hi-Z. X 0 X 1 Table 3 Transmitter Impedance (Part 1 of 2) 7 February 8, 2011 IDT 89HP0504PB Data Sheet Mode Channel Enabled Channel Enabled but inactive Control Inputs [A,B]RXDETEN RSTB Tx Terminations 50Ω Description Rx signal detected. Receiver detect disabled. Receiver terminations set to 50Ω. TX output is squelched. A valid receiver was detected. Receiver terminations set to 50Ω. Output common-mode is held at its active value. TX output is active. A valid receiver was detected. Receiver terminations set to 50Ω. 0 1 1 1 50Ω Channel Enabled and active 1 1 50Ω Table 3 Transmitter Impedance (Part 2 of 2) PCIe Receiver Detection Support The P0504PB transmitter fully supports PCIe Receiver Detection requirements. Receiver detection is enabled for channels A0 and A1 by asserting pin ARXDETEN and for channels B0 and B1 by asserting pin BRXDETEN. For receiver detection to occur, a low pulse (minimum 200ns) must be applied at pin RSTB. The rising edge of the RSTB signal starts the receiver detection procedure. Neither ARXDETEN nor BRXDETEN can be toggled during the receiver detection procedure, i.e., they must be kept high for at least 200ns before the RSTB rising edge and they cannot go to low sooner than 2ms from the time the RSTB goes high. The receiver detection takes place once per RSTB pulse. RXDETEN T3 >0ns T4 >= 2ms T0 >= 200 ns RSTB T1 = 800us VDD VCM T2 = 1.5us RxDetStat (i t l) Figure 5 Receiver Detection Timing Modes of Operation The device supports several data transfer modes, electrical idle mode, and several power reducing modes. Electrical Idle Mode In electrical idle mode, the transmitter stops toggling and maintains its common-mode voltage level. The device enters electrical idle mode when the envelope of the incoming signal on a given channel has fallen below a programmable threshold level. Power Reducing Modes The Repeater supports five power-down states and one active state as shown in Table 4. The user can choose between full chip power-down, channel based power-down, and electrical idle modes. Power reducing modes can be selected via PDB and RSTB. 8 February 8, 2011 IDT 89HP0504PB Data Sheet Required Signal Values Power Reducing Mode PowerDown Control PDB Full IC power-down 0 Receiver Detect Start RSTB X All channels are powered-down Receiver detect reset Rx termination is set to Hi-Z Tx termination is set to 1kΩ Tx common-mode is at VDD Receiver detect state machine Receiver terminations placed in Hi-Z Tx termination is set to 1kΩ Tx common-mode is at VDD Tx output is squelched No receiver was Detected Receiver terminations placed in Hi-Z Tx termination is set to 1kΩ Tx common-mode is at VDD Tx output is squelched A valid receiver was detected Receiver terminations set to 50Ω Output common-mode is held at its active value Tx termination is set to 50Ω Tx output is active A valid receiver was detected Receiver terminations set to 50Ω Transmitter terminations set to 50Ω State Description Receiver Detect reset 1 0 Channel enabled but inactive (electrical idle). Rx and Tx set to hi-Z 1 1 Channel enabled but inactive (electrical idle). Rx and Tx set to 50 Ohms 1 1 Channel enabled and active. No power-down 1 1 Table 4 Power Reducing Modes Channel Muxing The P0504PB repeater permits a variety of muxing, demuxing, and switching configurations, and it can mux/de-mux 1 or 2 bi-directional PCIe lanes (4 PCIe channels) into 2 target devices. These configurations require the selection of specific pins for input and output ports. In the following sections, each configuration is described in terms of pin connectivity to external upstream and downstream devices. The configurations shown are those often used in system designs: – Uni-directional 2:1 Mux (1 or 2 instances) – Uni-directional 1:2 De-Mux (1 or 2 instances) – Bi-directional 2:1 Mux/De-Mux – Bi-directional Z-function (also called Partial Cross Function) The P0504PB supports channel muxing in both upstream and downstream channel directions via the CHSEL pin, as shown below. Figure 6 shows the channel/reference muxing modes and Table 5 shows how CHSEL (Channel transfer selection) pin allows for various modes of data transfers: Multicast mode, Direct-connect, and Cross-connect. Both Direct-connect, and Cross-connect modes are used to build uni-directional and bi-directional 2:1 mux and Z-switch functions. 9 February 8, 2011 IDT 89HP0504PB Data Sheet Figure 6 Diagram of Channel/Reference Muxing Modes Input Pins CHSEL A0RX[P,N] A1RX[P,N] B0RX[P,N] B1RX[P,N] A0TX[P,N] Output Pins A1TX[P,N] B0TX[P,N] B1TX[P,N] CHSEL=VSS (Multicast Mode) CHSEL=Open (Direct-Connect Mode) CHSEL=VDD (Cross-Connect Mode) A0 DATA A0 DATA X A1 DATA B0 DATA B0 DATA X B1 DATA A0 DATA A0 DATA A0 DATA A1 DATA B0 DATA B0 DATA B0 DATA B1 DATA A0 DATA X B0 DATA X Squelched A0 DATA Squelched B0 DATA Table 5 Description of Channel Muxing/De-Muxing Functionality Uni-directional 2:1 Mux or Two Instances of Unidirectional 2:1 Mux This function can be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 7. 10 February 8, 2011 IDT 89HP0504PB Data Sheet Device #1 A0RX(P,N) A OUT B A1TX(P,N) Device #3 Device #2 A1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 7 Implementation of Unidirectional 2:1 Mux As an alternative, different chip channels can also be selected as shown in Figure 8. This solution can be combined with the previous one to obtain two instances of Uni-directional 2:1 Mux. Device #1 or #4 B0RX(P,N) A OUT B B1TX(P,N) Device #3 or #6 Device #2 or #5 B1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 8 Implementation of Second Instance of Unidirectional 2:1 Mux Uni-directional 1:2 De-Mux or Two Instances of Unidirectional 1:2 De-Mux This function can be achieved by using CHSEL pin as a de-mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 9. A A0RX(P,N) IN B A0TX(P,N) Device #2 Device #1 A1TX(P,N) Device #3 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 9 Implementation of Unidirectional 1:2 De-Mux As an alternative, different chip channels can also be selected as shown in Figure 10. This solution can be combined with the previous one to obtain two instances of Uni-directional 1:2 De-Mux. 11 February 8, 2011 IDT 89HP0504PB Data Sheet B0TX(P,N) A Device #1 or #4 B0RX(P,N) IN B Device #2 or #5 B1TX(P,N) Device #3 or #6 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 10 Implementation of Second Instance of Unidirectional 1:2 De-Mux Bi-directional 2:1 Mux/De-Mux The bi-directional Mux and De-Mux function can also be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 11. Device #1 A0RX(P,N) B1TX(P,N) A I/O B A1TX(P,N) B0RX(P,N) Device #3 Device #2 A1RX(P,N) B0TX(P,N) CHSEL CHSEL = VDD: I/O = A CHSEL = OPEN: I/O = B Figure 11 Implementation of Bi--directional 2:1 Mux/De-Mux Bi-directional Z-function (also called Partial Cross Function) This function can also be achieved by using the CHSEL pin as a flow control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 12. Device #1 A0TX(P,N) B1RX(P,N) CHSEL=OPEN D VD L= E A0RX(P,N) B1TX(P,N) Device #3 S CH Device #2 A1TX(P,N) B0RX(P,N) CHSEL=OPEN A1RX(P,N) B0TX(P,N) Device #4 Figure 12 Implementation of Z-function 12 February 8, 2011 IDT 89HP0504PB Data Sheet Electrical Specifications Absolute Maximum Ratings Note: All voltage values, except differential voltages, are measured with respect to ground pins. Parameter Supply voltage range VDD Voltage range Differential I/O Control I/O ESD requirements: Electrostatic discharge Human body model ESD requirements: Charged-Device Model (CDM) ESD requirements: Machine model Storage ambient temperature Value –0.5 to 1.35 –0.5 to VDD +0.5 –0.5 to VDD + 0.5 ±2000 ±500 ±125 -55 to 150 Unit V V V V V V °C Table 6 Absolute Maximum Ratings Warning: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Notes Min Typical Max Unit Power Supply Pin Requirements VDD 1.2V DC analog supply voltage (specified at bump pins) 1.14 1.2 1.26 V °C °C °C Temperature Requirements TA TJUNCTION Ambient operating temperature - Commercial Ambient operating temperature - Industrial Junction operating temperature Table 7 Operating Conditions 0 -40 0 — — — 70 85 125 13 February 8, 2011 IDT 89HP0504PB Data Sheet Power Consumption Table 8 below lists power consumption values under typical and maximum operating conditions. Parameter Notes Min Typical Max Unit Active Mode IVDD PD PD-ch Current into VDD supply Full chip power1 Power per channel1 Full chip standby Table 8 Power Consumption 1. — 330 400 100 30 500 600 150 40 mA mW mW mW Standby Mode Maximum power under all conditions. Power is reduced by selecting smaller de-emphasis settings (closer or equal to 0dB). Package Thermal Considerations The data in Table 9 below contains information that is relevant to the thermal performance of the 36-pin QFN package. Parameter TJ(max) TA(max) Description Junction Temperature Ambient Temperature Value 125 70 85 41.8 36.1 35.3 34.3 33.7 33.2 Conditions Maximum Maximum for commercial-rated products Maximum for industrial-rated products Zero air flow 1 m/S air flow 2 m/S air flow 3 m/S air flow 4 m/S air flow 5 m/S air flow NA NA Units oC oC o C oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W θJA(effective) Effective Thermal Resistance, Junction-to-Ambient θJB θJC Thermal Resistance, Junction-to-Board Thermal Resistance, Junction-to-Case 14.5 37.2 Table 9 Thermal Specifications for P0504PB, 4.0x7.5mm 36-QFN Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 9. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 9), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). 14 February 8, 2011 IDT 89HP0504PB Data Sheet DC Specifications Parameter VIL VIM VIH VHYS IIL IIH IIL1 IIH1 RWEAK_PD_2L RWEAK_PU_2L RWEAK_PD_3L RWEAK_PU_3L 1. Description Digital Input Signal Voltage Low Level1 Digital Input Signal Voltage Mid Level2 Digital Input Signal Voltage High Level1 Hysteresis of Schmitt Trigger Input Input Current3 Input Current4 Input Current2 Input Current2 Internal weak pull-down resistor at 2-level input pads4 Internal weak pull-up resistor at 2-level input pads3 Internal weak pull-down resistor at all 3-level input pads Internal weak pull-up resistor at all 3-level input pads Table 10 DC Specification Min -0.3 0.25*VDD+ 0.1 0.75*VDD+ 0.1 0.1 — — — — 11 11 6.3 6.3 Typ — Max 0.25*VDD-0.1 0.75*VDD-0.1 VDD+ 0.3 — 100 100 180 180 — — — — Unit V V V V µA µA µA µA K ohm K ohm K ohm K ohm Applies to all input pins. Applies only to 2-level input pins with default values set to VDD in the Pin Description table (Table 14). Applies only to 2-level input pins with default values set to VSS in the Pin Description table (Table 14). 2. Applies to all 3-level input pins. 3. 4. AC Specifications Latency Specification Parameter Latency Description Input to output signal propagation device Table 11 Latency Specification Min — Typical 300 Max — Unit ps 15 February 8, 2011 IDT 89HP0504PB Data Sheet Receiver Specifications Parameter Receiver Input Jitter Specifications TRX-DDJ TRX-TJ TRX-EYE Receive Input Signal Data Dependent Jitter (Inter-Symbol Interference). Receive Input Signal Total Jitter Receiver eye time opening (can recover from closed eye due to trace attenuation and ISI jitter) Receiver Differential Peak-Peak Voltage1 Receiver DC Common Mode Voltage Receiver AC Common Mode Voltage Receiver Differential Return Loss (0 - 1.25GHz) Receiver Differential Return Loss (1.25 - 2.5GHz) Receiver Common-Mode DC Return Loss Receive Impedance (singled-ended) DC differential impedance DC Input Common-Mode Receive High Impedance for Input Voltage from 0V to 200mV DC Input Common-Mode Receive High Impedance for Input Voltage from 0V to -200mV Differential Receive High Impedance for Input Voltage from 0V to 200mV Differential Receive High Impedance for Input Voltage from 0V to -200mV Electrical Idle Signal Detect Threshold Unexpected Electrical Idle Enter Detect Threshold Integration Time Signal Detect Valid Signal Attack Time (Turn-on time) Signal Detect Valid Signal Decay Time (Turn-off time) Signal Detect Attack / Decay Time Mismatch — — 0 — — — >1 >1 — UI UI UI Description Min Typical Max Unit Receiver Input Eye Specification VRX-DIFF-PP-DC VRX-CM-DC VRX-CM-AC-P RLRX-DIFF-F1 RLRX-DIFF-F2 RLRX-CM ZRX-DC ZRX-DIFF-DC ZRX-HIGH-IMP-DC-POS ZRX-HIGH-IMP-DC-NEG ZDIFF-HIZ-POS ZDIFF-HIZ-NEG 0 — — — — — 40 80 50k 1k 200k 4k — 0 — — — — 50 100 — — — — 2000 — 150 -10 -8 -6 60 120 — — — — mV mV mV dB dB dB Ohm Ohm Ohm Ohm Ohm Ohm Receiver Return Loss Receiver DC Impedance Receiver Signal Detection VRX-IDLE-DET-DIFFp-p TRX-IDLE-DET-DIFF-ENTERTIME 70 — — — — 110 — — — — 150 10 15 15 5 mV ms ns ns ns TSIGDET-ATTACK TSIGDET-DECAY TSIGDET-ATT-DECAY-MIS Table 12 Receiver Electrical Specifications 1. The minimum value of 0 mV represents the case when Eye is completely closed. 16 February 8, 2011 IDT 89HP0504PB Data Sheet Transmitter Specifications Parameter Description Min Typical Max Unit Output Eye and Common Voltage Specification VTX-DIFF-PP Differential Transmitter swing [A:B]xTXSW=1 [A:B]xTXSW=open Low power differential p-p Transmitter swing [A:B]xTXSW=0 Output De-emphasis. Defined as 20log(VTX-DE-EMP / VTXDIFF) [dB] Tx de-emphasis level ratio [A:B]xTXSW=open Tx de-emphasis level [A:B]xTXSW=1 Rise/Fall Time Tx rise/fall mismatch Residual Deterministic Jitter at output pins (1 inch FR4 trace before receiver input pins, 5Gbps)1 Residual Deterministic Jitter at output pins (40 inch FR4 trace before receiver input pins, 5Gbps1 Pk-Pk AC Common Mode Voltage Variation Tx AC common mode voltage (2.5 GT/s) RMS AC Common Mode Voltage Variation Transmitter DC common-mode voltage Absolute Delta of DC Common Mode Voltage between P and N AC Coupling Capacitor Transmitter Output Differential DC Impedance2 Transmitter short-circuit current limit Transmitter Differential Return Loss (0 - 1.25GHz) Transmitter Differential Return Loss (1.25 - 2.5GHz) Transmitter Common-Mode DC Return Loss Idle Output Voltage Maximum Common-Mode Step Entering/Exiting Electrical Idle Mode 800 700 400 -6.5 950 800 500 — 1100 950 650 0 mV VTX-DIFF-PP-LOW DTX-DEEMP VTX-DE-RATIO-3.5dB VTX-DE-RATIO-6dB TTX-RISE-FALL TRF-MISMATCH TRES-DJ-5GBPS-1 TRES-DJ-5GBPS-2 VTX-CM-AC-PP VTX-CM-AC-P VTX-CM-RMS-AC VTX-DC-CM VTX-CM-DC-LINEDELTA CTX ZTX-DIFF-DC ITX-SHORT RLTX-DIFF-F1 RLTX-DIFF-F2 RLTX-CM Electrical Idle VTX-IDLE VCM-DELTA-SQUELCH mV dB -4.0 -6.5 0.125 — — — — — — 0 0 75 80 — — — — — — — — — — — 0.15 — — — — — — 100 — — — — — — -3.0 -5.5 — 0.1