89HP0604SB

4 Channel 6Gbps SAS/SATA Signal Repeater ® 89HP0604SB Data Sheet Device Overview The IDT 89HP0604SB (P0604SB) is a 6Gbps SAS/SATA® Repeater device featuring IDT EyeBoost™ technology that compensates for cable and board trace attenuations and ISI jitter, thereby extending connection reach. The device is optimized for SAS/SATA high speed serial data streams and contains four data channels, each able to process 6Gbps transmission rates. Each channel consists of an input equalizer and amplifier, signal detection with glitch filter, as well as programmable output swing and de-emphasis. Allowing for application specific optimization, the P0604SB, with its configurable receiver and transmitter features, is ideal for SAS/SATA applications using a wide combination of cables and board trace materials. All modes of active data transfer are designed with minimized power consumption. In full shutdown mode, the part consumes less than 40mW in worst case environmental conditions. Features Compensates for cable and PCB trace attenuation and ISI jitter Programmable receiver equalization up to 24db Programmable transmitter swing and de-emphasis Recovers data stream even when the differential signal eye is completely closed due to trace attenuation and ISI jitter Full SAS/SATA protocol support Configurable via external pins Leading edge power minimization in active and shutdown modes No external bias resistors or reference clocks required Channel mux mode, demux mode, 1 to 2 channels multicast, and Z-switch function mode Available in a 36-pin QFN package (4.0 x 7.5mm with 0.5mm pitch) Applications Blade servers, rack servers SAS/SATA instrumentation Storage systems Cabled SAS/SATA devices Benefits Extends maximum cable length to over 8 meters and trace length over 48 inches in SAS/SATA applications Minimizes BER Typical Application Figure 1 IDT Repeaters in Blade Servers IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 © 2011 Integrated Device Technology, Inc February 8, 2011 IDT 89HP0604SB Data Sheet SAS/SATA Compliance The device was designed to provide end users with features needed to comply with SAS/SATA system application requirements: – SAS/SATA Out-of-Band (OOB) Support – Jitter, eye opening, and all other AC and DC specifications. Block Diagram The P0604SB contains four high speed channels as shown in Figure 2. Each channel can be routed to different outputs. Depending on user configuration via mode selections, input traffic can be muxed or demuxed. Powerdown (PDB) is provided for state and channel control. Figure 2 Block Diagram 2 February 8, 2011 Table of Contents Device Overview ................................................................................................................................ 1 Applications........................................................................................................................................ 1 Features............................................................................................................................................. 1 Benefits .............................................................................................................................................. 1 Typical Application ............................................................................................................................. 1 SAS/SATA Compliance ..................................................................................................................... 2 Block Diagram.................................................................................................................................... 2 Functional Description ....................................................................................................................... 5 Power-Up................................................................................................................................... 6 Power Sequencing..................................................................................................................... 6 IDT EyeBoost™ Technology ..................................................................................................... 6 Eye Diagram Parameters .......................................................................................................... 7 Modes of Operation ................................................................................................................... 7 Electrical Specifications ................................................................................................................... 11 Absolute Maximum Ratings ..................................................................................................... 11 Recommended Operating Conditions...................................................................................... 11 Power Consumption ................................................................................................................ 12 Package Thermal Considerations............................................................................................ 12 DC Specifications .................................................................................................................... 13 AC Specifications..................................................................................................................... 13 Pin Description................................................................................................................................. 17 Package Pinout — 36-QFN Signal Pinout ....................................................................................... 19 Pin Diagram ..................................................................................................................................... 19 QFN Package Dimension ................................................................................................................ 20 Revision History ............................................................................................................................... 21 Ordering Information........................................................................................................................ 22 3 February 8, 2011 IDT 89HP0604SB Data Sheet PAGE INTENTIONALLY LEFT BLANK 4 February 8, 2011 IDT 89HP0604SB Data Sheet Functional Description The P0604SB has 4 channels, each with the individually programmable features listed below. Figure 3 diagrams the channel and Table 1 summarizes key configuration options. OOB/LOS detection with glitch filter Channel power-down Programmable equalizer + _ Input termination 100 ohm Programmable Transmitter De-emphasis: 0 to -6.5dB Voltage swing: 500mV to 950mV Output termination 100 ohm + _ 0 to 14dB Up to 10dB Auto-boost Figure 3 Channel Block Diagram with Channel Features Per-channel programmable features used at the Receive side. – Input equalization with 3 levels: 2 to 14dB compensation for high frequency signal attenuation due to cables and board traces. Additionally, up to 10dB boost is added automatically by the equalizer for applications using long cables. The total equalization range is between 2dB and 24dB. – Input high impedance control via channel enable: disabled (active mode) and hi-Z (power-down). Per-channel programmable features used at the Transmit side. – Output de-emphasis with 8 levels: 0 to -6.5dB. The de-emphasis boosts the magnitude of higher frequencies sent by the transmitter to compensate for high frequency losses travelling through output side cable or output side board traces. This ensures that the final received signal has a wider eye opening. – Output differential swing with 3 levels: 0.5V to 0.95V (peak-to-peak). – Loss of signal detection: When the incoming differential peak-peak amplitude falls below 110mV, the device enters loss of signal mode and the corresponding transmitter stops toggling, maintains its common mode voltage level, and meets all loss of signal specifications described in the AC Specifications section of this data sheet. In addition, the device contains global configuration of the data path: – Transfer modes: direct connect, cross-connect, multicast. 5 February 8, 2011 IDT 89HP0604SB Data Sheet Power-Up After the power supplies reach their minimum required levels, the P0604SB powers up by setting all input and output pins to known states: All the device's input configuration pins are set internally to VSS or VDD for 2-level pins and to VDD/2 for 3-level pins. High speed differential input and output pins depend on various conditions described below: – High speed differential input and output pins are in high impedance if any of the following conditions is true: • Powerdown is set (PDB pin = 0V) or • No receiver termination was detected at TX outputs In all other cases, high speed differential input and output pins are set to 50 ohms per pin, with 100 ohms differential impedance. Also refer to Table 2, Power Reducing Modes. The power ramp up time for the P0604SB should be less than 1ms. Power Sequencing There are no power sequencing constraints for the P0604SB. IDT EyeBoost™ Technology IDT EyeBoost™ technology is a method of data stream recovery even when the differential signal eye is completely closed due to cable or trace attenuation and ISI jitter. With IDT EyeBoost™, the system designer can both recover the incoming data and retransmit it to target device with a maximized eye width and amplitude. An example of IDT EyeBoost™ usage in a system application and eye diagram results are shown in Figure 4. In this figure, the (a) diagram shows incoming differential signal (closed eye) after 62 inch FR4 connection from signal source and the (b) diagram shows differential signal at the output of repeater maximized eye opening with IDT EyeBoost™. (a) Figure 4 Eye Diagram (b) 6 February 8, 2011 IDT 89HP0604SB Data Sheet Eye Diagram Parameters Parameter Names for Programming via Pins A0RXEQ, A1RXEQ, B0RXEQ, B1RXEQ Range: 0dB to 14dB (plus additional autoboost up to 10dB for long connections) A0TXSW, A1TXSW, B0TXSW, B1TXSW Range: 0.5V to 0.95V for swing Range: 0 to -6.5dB for de-emphasis Feature Input equalization Feature Type Main eye optimization Output differential signal swing (peak-to-peak) and output de-emphasis Main eye optimization Table 1 Quick Reference: Parameters Used for Eye Optimization Modes of Operation The device supports several data transfer modes, loss of signal mode, and one power reducing mode. Loss of Signal Mode When the input signal is lost, the transmitter stops toggling and maintains its common-mode voltage level. The device detects loss-of-signal (LOS) when the envelope of the incoming signal on a given channel has fallen below a programmable threshold level. Power Reducing Modes The Repeater supports five power-down states and one active state as shown in Table 2. The user can choose between full chip power-down or channel based power-down. Power reducing modes are selected via PDB and channel enable pins (A0EN, A1EN, etc.). Power Reducing Mode Full IC powerdown Required Signal Values PDB 0 State Description All channels are powered-down Rx termination is set to Hi-Z Tx termination is set to 1kΩ Tx common-mode is at VDD Tx output is active Receiver terminations set to 50Ω Transmitter terminations set to 50Ω Channel enabled and active. No power-down 1 Table 2 Power Reducing Modes 7 February 8, 2011 IDT 89HP0604SB Data Sheet Channel Muxing The P0604SB repeater permits a variety of muxing, demuxing, and switching configurations, and it can mux/de-mux 1 or 2 bi-directional SAS/ SATA lanes (4 SAS/SATA channels) into 2 target devices. These configurations require the selection of specific pins for input and output ports. In the following sections, each configuration is described in terms of pin connectivity to external upstream and downstream devices. The configurations shown are those often used in system designs: – Uni-directional 2:1 Mux (1 or 2 instances) – Uni-directional 1:2 De-Mux (1 or 2 instances) – Bi-directional 2:1 Mux/De-Mux – Bi-directional Z-function (also called Partial Cross Function) The P0604SB supports channel muxing in both upstream and downstream channel directions via the CHSEL pin, as shown below. Figure 5 shows the channel/reference muxing modes and Table 3 shows how CHSEL (Channel transfer selection) pin allows for various modes of data transfers: Multicast mode, Direct-connect, and Cross-connect. Both Direct-connect, and Cross-connect modes are used to build uni-directional and bi-directional 2:1 mux and Z-switch functions. Figure 5 Diagram of Channel/Reference Muxing Modes Input Pins CHSEL A0RX[P,M] A1RX[P,M] B0RX[P,M] B1RX[P,M] A0TX[P,M] Output Pins A1TX[P,M] B0TX[P,M] B1TX[P,M] CHSEL=VSS (Multicast Mode) CHSEL=Open (Direct-Connect Mode) CHSEL=VDD (Cross-Connect Mode) A0 DATA A0 DATA X A1 DATA B0 DATA B0 DATA X B1 DATA A0 DATA A0 DATA A0 DATA A1 DATA B0 DATA B0 DATA B0 DATA B1 DATA A0 DATA X B0 DATA X Squelched A0 DATA Squelched B0 DATA Table 3 Description of Channel Muxing/De-Muxing Functionality 8 February 8, 2011 IDT 89HP0604SB Data Sheet Uni-directional 2:1 Mux or Two Instances of Unidirectional 2:1 Mux This function can be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 6. Device #1 A0RX(P,N) A OUT B A1TX(P,N) Device #3 Device #2 A1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 6 Implementation of Unidirectional 2:1 Mux As an alternative, different chip channels can also be selected as shown in Figure 7. This solution can be combined with the previous one to obtain two instances of Uni-directional 2:1 Mux. Device #1 or #4 B0RX(P,N) A OUT B B1TX(P,N) Device #3 or #6 Device #2 or #5 B1RX(P,N) CHSEL CHSEL = VDD: OUT = A CHSEL = OPEN: OUT = B Figure 7 Implementation of Second Instance of Unidirectional 2:1 Mux Uni-directional 1:2 De-Mux or Two Instances of Unidirectional 1:2 De-Mux This function can be achieved by using CHSEL pin as a de-mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 8. A A0RX(P,N) IN B A0TX(P,N) Device #2 Device #1 A1TX(P,N) Device #3 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 8 Implementation of Unidirectional 1:2 De-Mux 9 February 8, 2011 IDT 89HP0604SB Data Sheet As an alternative, different chip channels can also be selected as shown in Figure 9. This solution can be combined with the previous one to obtain two instances of Uni-directional 1:2 De-Mux. B0TX(P,N) A Device #1 or #4 B0RX(P,N) IN B Device #2 or #5 B1TX(P,N) Device #3 or #6 CHSEL CHSEL = OPEN: A = IN CHSEL = VDD: B = IN Figure 9 Implementation of Second Instance of Unidirectional 1:2 De-Mux Bi-directional 2:1 Mux/De-Mux The bi-directional Mux and De-Mux function can also be achieved by using the CHSEL pin as a mux control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 10. Device #1 A0RX(P,N) B1TX(P,N) A I/O B A1TX(P,N) B0RX(P,N) Device #3 Device #2 A1RX(P,N) B0TX(P,N) CHSEL CHSEL = VDD: I/O = A CHSEL = OPEN: I/O = B Figure 10 Implementation of Bi--directional 2:1 Mux/De-Mux Bi-directional Z-function (also called Partial Cross Function) This function can also be achieved by using the CHSEL pin as a flow control signal. CHSEL should be set to either VDD or OPEN. The ports should be configured as shown in Figure 11. Device #1 A0TX(P,N) B1RX(P,N) CHSEL=OPEN D VD L= E A0RX(P,N) B1TX(P,N) Device #3 S CH Device #2 A1TX(P,N) B0RX(P,N) CHSEL=OPEN A1RX(P,N) B0TX(P,N) Device #4 Figure 11 Implementation of Z-function 10 February 8, 2011 IDT 89HP0604SB Data Sheet Electrical Specifications Absolute Maximum Ratings Note: All voltage values, except differential voltages, are measured with respect to ground pins. Parameter Supply voltage range VDD Voltage range Differential I/O Control I/O ESD requirements: Electrostatic discharge Human body model ESD requirements: Charged-Device Model (CDM) ESD requirements: Machine model Storage ambient temperature Value –0.5 to 1.35 –0.5 to VDD +0.5 –0.5 to VDD + 0.5 ±2000 ±500 ±125 -55 to 150 Unit V V V V V V °C Table 4 Absolute Maximum Ratings Warning: Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Notes Min Typical Max Unit Power Supply Pin Requirements VDD 1.2V DC analog supply voltage (specified at bump pins) 1.14 1.2 1.26 V °C °C °C Temperature Requirements TA TJUNCTION Ambient operating temperature - Commercial Ambient operating temperature - Industrial Junction operating temperature 0 -40 0 — — — 70 85 125 Table 5 P0604SB Operating Conditions 11 February 8, 2011 IDT 89HP0604SB Data Sheet Power Consumption Table 6 below lists power consumption values under typical and maximum operating conditions. Parameter Notes Min Typical Max Unit Active Mode IVDD PD PD-ch Current into VDD supply Full chip power1 Power per channel1 Full chip standby Table 6 Power Consumption 1. — 330 400 100 30 500 600 150 40 mA mW mW mW Standby Mode Maximum power under all conditions. Power is reduced by selecting smaller de-emphasis settings (closer or equal to 0dB). Package Thermal Considerations The data in Table 7 below contains information that is relevant to the thermal performance of the 36-pin QFN package. Symbol θJA(effective) θJB θJC Parameter Value 49.8 Conditions Zero air flow 1 m/S air flow 2 m/S air flow NA NA Units oC/W oC/W o Effective Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Board Thermal Resistance, Junction-to-Case 44.8 42.2 39.3 34.5 C/W oC/W oC/W Table 7 Thermal Specifications for 36-QFN Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 7. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 7), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). 12 February 8, 2011 IDT 89HP0604SB Data Sheet DC Specifications Parameter VIL VIM VIH VHYS IIL IIH IIL1 IIH1 RWEAK_PD_2L RWEAK_PU_2L RWEAK_PD_3L RWEAK_PU_3L 1. Description Digital Input Signal Voltage Low Level1 Digital Input Signal Voltage Mid Level2 Digital Input Signal Voltage High Level1 Hysteresis of Schmitt Trigger Input Input Current3 Input Current4 Input Current2 Input Current2 Internal weak pull-down resistor at 2-level input pads4 Internal weak pull-up resistor at 2-level input pads3 Internal weak pull-down resistor at all 3-level input pads Internal weak pull-up resistor at all 3-level input pads Table 8 DC Specification Min -0.3 0.25*VDD+ 0.1 0.75*VDD+ 0.1 0.1 — — — — 11 11 6.3 6.3 Typ — Max 0.25*VDD-0.1 0.75*VDD-0.1 VDD+ 0.3 — 100 100 180 180 — — — — Unit V V V V µA µA µA µA K ohm K ohm K ohm K ohm Applies to all input pins. Applies only to 2-level input pins with default values set to VDD in the Pin Description table (Table 12). Applies only to 2-level input pins with default values set to VSS in the Pin Description table (Table 12). 2. Applies to all 3-level input pins. 3. 4. AC Specifications Latency Specification Parameter TPD TSIGDET-ATTACK TSIGDET-DECAY TSIGDET-ATT-DECAY-MIS Description Input to output signal propagation device Signal Detect Valid Signal Attack Time (Turn-on time) Signal Detect Valid Signal Decay Time (Turn-off time) Signal Detect Attack / Decay Time Mismatch Min — — — — Typical 300 — — — Max — 15 15 5 Unit ps ns ns ns Table 9 P0604SB Latency Specification Receiver Specifications Parameter Receiver Input Jitter Specification TRX-DJ TRX-TJ TRX-EYE Receive input, Data Dependant Jitter (Inter-SymbolInterference) Receive input, Total Jitter Receiver eye time opening (can recover from closed eye due to trace/cable jitter) — — 0 — — — >1 >1 — UI UI UI Description Min Typical Max Unit Table 10 P0604SB Receiver Electrical Specifications (Part 1 of 2) 13 February 8, 2011 IDT 89HP0604SB Data Sheet Parameter Receiver Input Eye Specification VDIFF-RX tskew-RX VCM-AC-RX Vthresh RLDD11,RX Description Receiver Differential Peak-Peak Voltage1 RX Differential Skew Receiver AC Common Mode Voltage OOB Signal Detection Threshold RX Differential Mode Return Loss 0 MHz - 150 MHz 150 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz Min Typical Max Unit 0 — — 50 — — — 110 2000 30 100 160 mV ps mVp-p mVppd Receiver Return Loss 18 18 14 10 8 3 1 — — 5 5 2 1 1 — 85 20 — — — — — — — -13 6 — — — — — — — — — — — — — — — — — — — — — — — 115 40 Ohm Ohm dB/dec GHz dB dB RLRXslope RLRX-freq-max RLCC11,RX Slope of RX Differential Mode Return Loss (From 300MHz) RX Differential Mode Return Loss Max Frequency RX Common Mode Return Loss 0 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz Receiver DC Impedance ZDIFF-RX ZCM-RX Differential impedance , RX pair Common-Mode Receive Impedance Table 10 P0604SB Receiver Electrical Specifications (Part 2 of 2) 1. The minimum value of 0 mV represents the case when Eye is completely closed. Transmitter Specifications Parameter Description Min Typical Max Unit Output Eye and Common Voltage Specification VTX-DIFF-PP Differential Transmitter swing [A:B]xTXSW=1 [A:B]xTXSW=open Low power differential p-p Transmitter swing [A:B]xTXSW=0 800 700 400 950 800 500 1100 950 650 mV VTX-DIFF-PP-LOW mV Table 11 P0604SB Transmitter Electrical Requirements (Part 1 of 2) 14 February 8, 2011 IDT 89HP0604SB Data Sheet Parameter VTX-DE-RATIO VTX-DE-RATIO-3.5dB VTX-DE-RATIO-6dB TRES-DJ-6.25GBPS-1 TRES-DJ-6.25GBPS-2 T20-80TX TskewTX R/Fbal AMPbal VCM,AC-TX-PP VTX-CM-RMS-AC CTX ZTX-DIFF-DC ITX-SHORT RLDD11,TX RLTXslope RLCC11,TX Description Tx de-emphasis level ratio Tx de-emphasis level ratio [A:B]xTXSW=open Tx de-emphasis level [A:B]xTXSW=1 Residual Deterministic Jitter at output pins (1 inch FR4 trace before receiver input pins, 6.25Gbps)1 Residual Deterministic Jitter at output pins (40 inch FR4 trace before receiver input pins, 6.25Gbps)1 TX Rise/Fall Time (20-80%) TX Differential Skew TX Rise/Fall Imbalance TX Amplitude Balance Tx AC Common Mode Voltage (Peak to peak) RMS AC Common Mode Voltage Variation AC Coupling Capacitor Transmitter Output Differential DC Impedance Transmitter short-circuit current limit DC TX Differential Mode Return Loss DC TX Differential Mode Return Loss (FBAUD/2) Slope of TX Differential Mode Return Loss (From 300MHz) TX Common Mode Return Loss (measured at 3.0 Gbps) 0 MHz - 300 MHz 300 MHz - 600 MHz 600 MHz - 1.2 GHz 1.2 GHz - 2.4 GHz 2.4 GHz - 3.0 GHz 3.0 GHz - 5.0 GHz Min -6.5 -4.0 -6.5 — — 33 — — — — — 12 85 — 14 6 — Typical Max 0 Unit dB dB dB UI UI ps ps % % mVp-p mV nF Ohm mA dB dB/dec — — — 0.18 — — — — — — — 100 — — — -13 -3.0 -5.5