89HPES12NT3

12-lane 3-Port Non-Transparent PCI Express® Switch ® 89HPES12NT3 Data Sheet Preliminary Information* Device Overview The 89HPES12NT3 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides high-performance I/O connectivity and switching functions between a PCIe® upstream port, a transparent downstream port, and a non-transparent downstream port. With non-transparent bridging (NTB) functionality, the PES12NT3 can be used standalone or as a chipset with IDT PCIe System Interconnect Switches in multi-host and intelligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required. Features ◆ High Performance PCI Express Switch – Twelve PCI Express lanes (2.5Gbps), three switch ports – Delivers 48 Gbps (6 GBps) of aggregate switching capacity – Low latency cut-through switch architecture – Support for Max Payload size up to 2048 bytes – Supports one virtual channel and eight traffic classes – PCI Express Base specification Revision 1.0a compliant Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation (x4, x2, or x1) – Static lane reversal on all ports – Automatic polarity inversion on all lanes – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Non-Transparent Port – Crosslink support on NTB port – Four mapping windows supported • Each may be configured as a 32-bit memory or I/O window • May be paired to form a 64-bit memory window – Interprocessor communication • Thirty-two inbound and outbound doorbells • Four inbound and outbound message registers • Two shared scratchpad registers – Allows up to sixteen masters to communicate through the nontransparent port – No limit on the number of supported outstanding transactions through the non-transparent bridge – Completely symmetric non-transparent bridge operation allows similar/same configuration software to be run – Supports direct connection to a transparent or non-transparent port of another switch ◆ Block Diagram 3-Port Switch Core Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer NonTransparent Bridge Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer ... ... ... SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes 12 PCI Express Lanes x4 Upstream Port and Two x4 Downstream Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.Inc. 1 of 29 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice April 11, 2007 DSC 6929 IDT 89HPES12NT3 Data Sheet Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Upstream port can be dynamically swapped with non-transparent downstream port to support failover applications – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC pass-through in transparent and non-transparent ports – Supports Hot-Swap ◆ Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) – Unused SerDes are disabled ◆ Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is also used by an external Hot-Plug I/O expander – Master and slave interfaces may be tied together so the switch can act as both master and slave ◆ Eight General Purpose Input/Output pins ◆ Packaged in 19x19mm 324-ball BGA with 1mm ball spacing ◆ management. This includes round robin port arbitration, guaranteeing bandwidth allocation and/or latency for critical traffic classes in applications such as high throughput 10 GbE I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES12NT3 is a three port switch that contains 12 PCI Express lanes. Each of the three ports is statically allocated 4 lanes with ports labeled as A, B and C. Port A is the upstream port, port B is the transparent downstream port, and port C is the non-transparent downstream port. During link training, link width is automatically negotiated. Each PES12NT3 port is capable of independently negotiating to a x4, x2 or x1 width. Thus, the PES12NT3 may be used in virtually any three port switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.). The PES12NT3 supports static lane reversal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space register, serial EEPROM, or the SMBus. Product Description Utilizing standard PCI Express interconnect, the PES12NT3 provides the most efficient high-performance I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-transparent bridging, the PES12NT3, as a standalone switch or as a chipset with IDT PCIe System Interconnect Switches, enables multi-host and intelligent I/O applications requiring inter-domain communication. The PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES12NT3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES12NT3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource 2 of 29 *Notice: The information in this document is subject to change without notice April 11, 2007 IDT 89HPES12NT3 Data Sheet CPU PES12NT3 CPU PES12NT3 CPU PES12NT3 PCIe System Interconnect Switch PCIe System Interconnect Switch Embedded CPU Embedded CPU SATA / SAS Embedded CPU GbE / 10GigE FC Figure 2 PCIe System Interconnect Architecture Block Diagram Controller 1 CPU Controller 2 CPU PES12N3 Cache Maint. & Possible Data Flow x4 PCIe x4 PCIe PES12N3 x4 PCIe FC Controller FC Controller Storage To Server FC 2Gb/s and 4Gb/s FC 2Gb/s and 4Gb/s To Server Figure 3 Dual Host Storage System 3 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal PEALREV Type I Name/Description PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modifying the value of the PALREV bit in the PA_SWCTL register. PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PCI Express Port A Serial Data Transmit. Differential PCI Express transmit pairs for port A PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of PCI Express Port B are reversed. This value may be overridden by modifying the value of the PBLREV bit in the PA_SWCTL register. PCI Express Port B Serial Data Receive. Differential PCI Express receive pairs for port B. PCI Express Port B Serial Data Transmit. Differential PCI Express transmit pairs for port B PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modifying the value of the PCLREV bit in the PA_SWCTL register. PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PCI Express Port C Serial Data Transmit. Differential PCI Express transmit pairs for port C PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. PCI Express Reference Clock Mode Select. These signals select the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 1 PCI Express Interface Pins PEARP[3:0] PEARN[3:0] PEATP[3:0] PEATN[3:0] PEBLREV I O I PEBRP[3:0] PEBRN[3:0] PEBTP[3:0] PEBTN[3:0] PECLREV I O I PECRP[3:0] PECRN[3:0] PECTP[3:0] PECTN[3:0] PEREFCLKP[1:0] PEREFCLKN[1:0] I O I REFCLKM I Signal MSMBADDR[4:1] MSMBCLK Type I I/O Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 2 SMBus Interface Pins (Part 1 of 2) MSMBDAT I/O 4 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type I I/O I/O Name/Description Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 2 SMBus Interface Pins (Part 2 of 2) Signal GPIO[0] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PEBRSTN Alternate function pin type: Output Alternate function: Reset output for downstream port B General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PECRSTN Alternate function pin type: Output Alternate function: Reset output for downstream port C General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PALINKUPN Alternate function pin type: Output Alternate function: Port A link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PBLINKUPN Alternate function pin type: Output Alternate function: Port B link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCLINKUPN Alternate function pin type: Output Alternate function: Port C link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: FAILOVERP Alternate function pin type: Input Alternate function: NTB upstream port failover General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins GPIO[1] I/O GPIO[2] I/O GPIO[3] I/O GPIO[4] I/O GPIO[5] I/O GPIO[6] GPIO[7] I/O I/O 5 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signal CCLKDS Type I Name/Description Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Non-Transparent Bridge Reset. Assertion of this signal indicates a reset on the external side of the non-transparent bridge. This signal is only used when the switch mode selects a non-transparent mode and has no effect otherwise. Fundamental Reset. Assertion of this signal resets all logic inside the PES12NT3 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12NT3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES12NT3 switch operating mode. 0x0 - Reserved 0x1 - Reserved 0x2 - Non-transparent mode 0x3 - Non-transparent mode with serial EEPROM initialization 0x4 - Non-transparent failover mode 0x5 - Non-transparent failover mode with serial EEPROM initialization 0x6 through 0xF - Reserved Table 4 System Pins CCLKUS I MSMBSMODE I PENTBRSTN I PERSTN RSTHALT I I SWMODE[3:0] I Signal JTAG_TCK Type I Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 5 Test Pins (Part 1 of 2) JTAG_TDI I 6 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signal JTAG_TDO Type O Name/Description JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins (Part 2 of 2) JTAG_TMS JTAG_TRST_N I I Signal VDDCORE VDDIO VDDPE VDDAPE VTTPE VSS Type I I I I I I Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 6 Power and Ground Pins 7 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Pin Characteristics Note: Some input pads of the PES12NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface Pin Name PEALREV PEARN[3:0] PEARP[3:0] PEATN[3:0] PEATP[3:0] PEBLREV PEBRN[3:0] PEBRP[3:0] PEBTN[3:0] PEBTP[3:0] PECLREV PECRN[3:0] PECRP[3:0] PECTN[3:0] PECTP[3:0] PEREFCLKN[1:0] PEREFCLKP[1:0] REFCLKM Type I I I O O I I I O O I I I O O I I I I I/O I/O I I/O I/O I/O Buffer LVTTL CML I/O Type Input Serial link Internal Resistor pull-down Notes LVTTL CML Input Serial link pull-down LVTTL CML Input Serial link pull-down LVPECL/ CML LVTTL LVTTL Diff. Clock Input Input Input STI pull-down pull-up Refer to Table 8 SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Input STI pull-up General Purpose I/O GPIO[7:0] LVTTL Input, High Drive pull-up Table 7 Pin Characteristics (Part 1 of 2) 8 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Function System Pins Pin Name CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0] JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type I I I I I I I I I O I I Low Drive STI pull-up pull-up External pulldown LVTTL STI pull-down pull-up pull-up pull-up Buffer LVTTL I/O Type Input Internal Resistor pull-up pull-up pull-down Notes Table 7 Pin Characteristics (Part 2 of 2) 9 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Logic Diagram — PES12NT3 Reference Clock PEREFCLKP PEREFCLKN REFCLKM 2 2 PEALREV PEARP[0] PEARN[0] PEATP[0] PEATN[0] PEATP[1] PEATN[1] ... PCI Express Switch SerDes Input Port A PEARP[1] PEARN[1] PCI Express Switch SerDes Output Port A ... PEARP[3] PEARN[3] PEATP[3] PEATN[3] PEBLREV PEBRP[0] PEBRN[0] PEBTP[0] PEBTN[0] PEBTP[1] PEBTN[1] ... PCI Express Switch SerDes Input Port B PEBRP[1] PEBRN[1] PCI Express Switch SerDes Output Port B ... PEBRP[3] PEBRN[3] PEBTP[3] PEBTN[3] PECLREV PECRP[0] PECRN[0] PES12NT3 PECTP[0] PECTN[0] PECTP[1] PECTN[1] ... PCI Express Switch SerDes Input Port C PECRP[1] PECRN[1] PCI Express Switch SerDes Output Port C ... PECRP[3] PECRN[3] PECTP[3] PECTN[3] Master SMBus Interface MSMBADDR[4:1] MSMBCLK MSMBDAT 4 8 GPIO[7:0] General Purpose I/O Slave SMBus Interface SSMBADDR[5,3:1] SSMBCLK SSMBDAT 4 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins PENTBRSTN MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[3:0] 4 System Pins VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE Power/Ground Figure 4 PES12NT3 Logic Diagram 10 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter RefclkFREQ RefclkDC2 TR, TF VSW Tjitter 1. Description Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing4 Input clock jitter (cycle-to-cycle) Min 100 40 Typical Max 1251 Unit MHz % RCUI3 V ps 50 60 0.2*RCUI 0.6 1.6 125 Table 8 Input Clock Requirements The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. AC coupling required. 2. ClkIn 3. 4. AC Timing Characteristics Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER Description Min1 Typical1 Max1 Units Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median D+ / D- Tx output rise/fall time Minimum time in idle Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Max time spend in idle before initiating a RX detect sequence Transmitter data skew between any 2 lanes 399.88 0.7 400 .9 400.12 ps UI 0.15 50 50 20 20 20 500 100 1300 90 UI ps UI UI UI ms ps TTX-RISE, TTX-FALL TTX- IDLE-MIN TTX-IDLE-SET-TOIDLE TTX-IDLE-TO-DIFFDATA TTX-IDLE-RCV-DETMAX TTX-SKEW PCIe Receive UI TRX-EYE (with jitter) Unit Interval Minimum Receiver Eye Width (jitter tolerance) 399.88 0.4 400 400.12 ps UI Table 9 PCIe AC Timing Characteristics (Part 1 of 2) 11 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Parameter TRX-EYE-MEDIUM TO MAX JITTER Description Max time between jitter median & max deviation Unexpected Idle Enter Detect Threshold Integration Time Lane to lane input skew Min1 Typical1 Max1 0.3 10 20 Units UI ms ns TRX-IDLE-DET-DIFFENTER TIME TRX-SKEW 1. Table 9 PCIe AC Timing Characteristics (Part 2 of 2) Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a Signal GPIO GPIO[7:0]1 1. Symbol Reference Min Max Unit Edge Timing Diagram Reference Tpw_13b2 None 50 — ns Table 10 GPIO AC Timing Characteristics GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. for this symbol were determined by calculation, not by testing. 2. The values Signal JTAG JTAG_TCK Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a Thigh_16a, Tlow_16a none 50.0 10.0 — 25.0 — — 20 20 — ns ns ns ns ns ns ns See Figure 5. JTAG_TMS1, JTAG_TDI JTAG_TDO Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2 JTAG_TCK rising 2.4 1.0 JTAG_TCK falling — — JTAG_TRST_N 1. none 25.0 Table 11 JTAG AC Timing Characteristics The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. The values for this symbol were determined by calculation, not by testing. 2. 12 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform Tdz_16c Tper_16a Recommended Operating Supply Voltages Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.0 0.9 0.9 1.425 0 Table 12 PES12NT3 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.6 1.1 1.1 1.575 0 Unit V V V V V V Recommended Operating Temperature Grade Commercial Temperature 0°C to +70°C Ambient Table 13 PES12NT3 Operating Temperatures 13 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES12NT3, the power-up sequence must be as follows: 1. 2. 3. VDDI/O — 3.3V VDDCore, VDDPE, VDDAPE — 1.0V VTTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence. Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow. Core (Watts) (1.0V supply) Typ Max PCIe Digital (Watts) (1.0V supply) Typ Max PCIe Analog (Watts) (1.0V supply) Typ Max PCIe Termination (Watts) (1.5V supply) Typ Max I/O (Watts) (3.3V supply) Typ Max Number of Connected Lanes: Port-A/Port-B/Port-C Total (Watts) Typ Max 1/1/1 4/1/1 4/4/4 0.52 0.56 0.65 0.67 0.76 0.89 0.27 0.47 0.68 0.36 0.58 0.81 0.13 0.19 0.21 0.16 0.21 0.25 0.11 0.22 0.38 0.13 0.26 0.51 0.01 0.01 0.01 0.01 0.01 0.01 1.04 1.44 1.92 1.33 1.81 2.47 Table 14 PES12NT3 Power Consumption 14 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Serial Link Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta Description Min1 Typ1 Max1 Unit Conditions Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits) 800 -3 -0.1 1 1200 -4 3.7 20 100 25 20 600 mV dB V mV mV mV mV mV dB dB VTX-CM-DC-linedelta VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC ZRX-COMM-HIGHZ-DC 12 6 80 40 505 800 100 50 650 950 120 60 Ω Ω mV mV Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance Powered down input common mode impedance (DC) Electrical idle detect threshold 175 1200 150 mV mV dB dB 15 6 80 40 200k 65 100 50 350k 175 120 60 Ω Ω Ω mV VRX-IDLE-DETDIFFp-p PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 15 DC Electrical Characteristics (Part 1 of 2) 15 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs 1. Parameter Description Min1 Typ1 Max1 Unit Conditions — — — — -0.3 2.0 -0.3 2.0 — — — — 2.5 -5.5 12.0 -20.0 — — — — — — — — — — — — 0.8 VDDIO + 0.5 0.8 VDDIO + 0.5 8.5 + 10 + 10 + 80 mA mA mA mA V V V V pF VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V — — — — — VDDI/O (max) VDDI/O (max) VDDI/O (max) μA μA μA Table 15 DC Electrical Characteristics (Part 2 of 2) Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. 16 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES12NT3 The following table lists the pin numbers and signal names for the PES12NT3 device. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 VSS VSS PEARP03 VDDCORE PEATN03 VDDCORE PEATP02 VDDCORE PEARN02 VDDCORE PEARP01 VDDCORE PEATP01 VDDCORE VDDCORE PEATN00 VSS VSS VDDCORE VDDCORE PEARN03 VSS PEATP03 VSS PEATN02 VSS PEARP02 VSS PEARN01 VSS PEATN01 VSS VSS PEATP00 Function Alt Pin E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G7 Function VDDPE VSS VDDPE VSS VDDCORE VDDAPE VSS PECTP03 PECTN03 VDDCORE VSS VDDCORE VDDAPE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VSS VDDPE VSS VDDIO VSS VSS VDDCORE PEBTP01 PEBTN01 VSS VDDPE VDDAPE VSS VSS Alt Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 Function VDDCORE VSS VTTPE VDDCORE VDDPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDPE VTTPE VSS VDDCORE PEBRN02 PEBRP02 VSS VDDPE VSS VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VSS VDDPE VSS Alt Pin P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 Function VDDIO VDDIO VDDIO VDDIO VDDIO VSS VTTPE VSS VDDCORE PEBTN03 PEBTP03 VSS VDDIO VSS VDDCORE MSMBDAT SSMBADDR_5 PEALREV SWMODE_2 RSTHALT GPIO_04 VDDCORE VSS VDDIO VSS PECTP00 PECTN00 VDDCORE VSS VSS JTAG_TCK JTAG_TDO MSMBADDR_1 MSMBCLK 1 Alt Table 16 PES12NT3 324-pin Signal Pin-Out (Part 1 of 3) 17 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Pin B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 Function VDDCORE VDDCORE PEBRP00 PEBRN00 VSS VDDCORE VSS VTTPE VSS VTTPE VSS VTTPE VSS VTTPE VDDCORE PEARP00 PEARN00 VDDCORE PECRN03 PECRP03 VDDCORE VSS VSS VDDCORE VSS VDDAPE VSS VDDAPE VSS VDDAPE VSS VDDAPE VSS VDDCORE VSS VSS VSS Alt Pin G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J7 J8 Function VDDIO VSS VDDIO VSS VDDCORE VSS VDDAPE VDDPE VSS PECTN02 PECTP02 VDDCORE VSS VTTPE VDDAPE VSS VSS VDDCORE VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDAPE VDDPE VTTPE VSS VDDCORE PEBRP01 PEBRN01 VSS VDDPE VSS VDDCORE VSS VSS Alt Pin L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 Function PECRP01 PECRN01 VDDCORE VSS VSS VDDAPE VSS VDDCORE VSS VSS VDDCORE VDDCORE VSS VSS VDDCORE VSS VDDAPE VSS VSS VDDCORE PEBTP02 PEBTN02 VTTPE VDDAPE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDAPE VTTPE PECTN01 Alt Pin T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 Function SSMBADDR_2 CCLKDS SWMODE_1 PERSTN GPIO_03 GPIO_07 VSS REFCLKM VSS VSS VDDCORE PEBRP03 PEBRN03 VSS JTAG_TDI JTAG_TMS MSMBADDR_2 MSMBADDR_4 SSMBADDR_3 CCLKUS SWMODE_0 PECLREV GPIO_00 GPIO_02 GPIO_06 MSMBSMODE VSS PECRN00 PECRP00 VDDCORE VSS PEREFCLKP1 PEREFCLKN1 JTAG_TRST_N MSMBADDR_3 SSMBADDR_1 SSMBCLK 1 1 Alt Table 16 PES12NT3 324-pin Signal Pin-Out (Part 2 of 3) 18 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Pin D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 Function VDDCORE PEBTN00 PEBTP00 VDDCORE VSS VDDCORE VSS VSS VDDPE VSS Alt Pin J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 Function VDDCORE VDDCORE VSS VSS VDDCORE VSS VDDCORE VSS PECRP02 PECRN02 Alt Pin N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 Function PECTP01 VDDCORE VSS VTTPE VSS VDDIO VDDIO VDDIO VDDIO VDDIO Alt Pin V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Function SSMBDAT PEBLREV SWMODE_3 PENTBRSTN GPIO_01 GPIO_05 PEREFCLKP2 PEREFCLKN2 VSS VDDCORE 1 Alt Table 16 PES12NT3 324-pin Signal Pin-Out (Part 3 of 3) Alternate Signal Functions Pin U13 T12 R12 V14 GPIO GPIO[2] GPIO[3] GPIO[4] GPIO[5] Alternate IOEXPINTN PAABN PAAIN PAPIN Table 17 PES12NT3 Alternate Signal Functions 19 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Power Pins VDDCore A4 A6 A8 A10 A12 A14 A15 B1 B2 B17 B18 C4 C13 C16 D1 D4 D14 D18 E3 E5 E14 F1 VDDCore F3 F6 F8 F10 F18 G12 H1 H7 H9 H10 H12 H18 J6 J9 J10 J13 J15 K1 K4 K18 L6 L7 Table 18 PES12NT3 Power Pins VDDCore L8 L9 L10 L11 L12 L13 M1 M6 M9 M10 M13 M18 P1 P18 R6 R13 T1 T18 V1 V18 VDDIO F15 G8 G10 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 R4 R15 VDDPE E8 E10 E12 F13 G4 G15 H15 J4 K5 K15 L4 L15 VDDAPE D6 D8 D10 D12 E15 F4 G5 G14 H4 H14 M4 M15 N4 N15 VTTPE C6 C8 C10 C12 H3 H16 K3 K16 N3 N16 P3 P16 20 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Ground Pins Vss A1 A2 A17 A18 B4 B6 B8 B10 B12 B14 B15 C3 C5 C7 C9 C11 D2 D3 D5 D7 D9 D11 D13 D15 Vss D16 D17 E4 E6 E7 E9 E11 E13 E16 F2 F5 F7 F9 F11 F12 F14 F16 F17 G3 G6 G7 G9 G11 G13 Vss G16 H2 H5 H6 H8 H11 H13 H17 J3 J5 J7 J8 J11 J12 J14 J16 K2 K6 K7 K8 K9 K10 K11 K12 Table 19 PES12NT3 Ground Pins Vss K13 K14 K17 L3 L5 L14 L16 M2 M3 M5 M7 M8 M11 M12 M14 M16 M17 N5 N6 N7 N8 N9 N10 N11 Vss N12 N13 N14 P2 P4 P15 P17 R3 R5 R14 R16 T2 T3 T14 T16 T17 U3 U16 V2 V17 21 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 PEATN00 PEATN01 PEATN02 I/O Type I I I/O I/O I/O I/O I/O I/O I/O I/O I I O I I I I I I I/O I/O I I I I I I I I I I O O O Location T9 U9 U12 V13 U13 T12 R12 V14 U14 T13 T4 U4 T5 U5 V5 T6 U6 V6 U7 T7 R7 U15 R9 C15 B11 A9 B3 C14 A11 B9 A3 A16 B13 B7 System PCI Express SMBus JTAG General Purpose Input/Output Signal Category System Table 20 PES12NT3 Alphabetical Signal List (Part 1 of 3) 22 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signal Name PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PEBLREV PEBRN00 PEBRN01 PEBRN02 PEBRN03 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 PECTN03 PECTP00 I/O Type O O O O O I I I I I I I I I O O O O O O O O I I I I I I I I I O O O O O Location A5 B16 A13 A7 B5 V10 C2 J2 L1 U2 C1 J1 L2 U1 E1 G2 N2 R1 E2 G1 N1 R2 U11 U17 L18 J18 C17 U18 L17 J17 C18 R18 N17 G17 E18 R17 Signal Category PCI Express Table 20 PES12NT3 Alphabetical Signal List (Part 2 of 3) 23 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Signal Name PECTP01 PECTP02 PECTP03 PENTBRSTN PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE VSS I/O Type O O O I I I I I I I I I I I I I/O I/O I I I I Location N18 G18 E17 V12 V4 V16 V3 V15 T11 T15 R11 V7 T8 U8 R8 V8 V9 U10 T10 R10 V11 System System SMBus System PCI Express System SMBus System PCI Express Signal Category PCI Express See Table 18 for a listing of power pins. See Table 19 for a listing of ground pins. Table 20 PES12NT3 Alphabetical Signal List (Part 3 of 3) 24 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet PES12NT3 Pinout — Top View 1 A B C D E F G H J K L M N P R T U V 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VDDCore (Power) VDDI/O (Power) VTTPE (Power) VDDPE (Power) VDDAPE (Power) Vss (Ground) Signals 25 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — 324-Pin BC324/BCG324 26 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet PES12NT3 Package Drawing — Page Two 27 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Revision History March 15, 2007: Initial publication of Preliminary data sheet. April 11, 2007: In Table 2, revised description of MSMBCLK. 28 of 29 April 11, 2007 IDT 89HPES12NT3 Data Sheet Ordering Information NN Product Family A Operating Voltage AAA Device Family NNAAN Product Detail AA Revision ID AA Package A Temp Range Legend A = Alpha Character N = Numeric Character Blank Commercial Temperature (0°C to +70°C Ambient) BC324 324-ball BGA BCG324 324-ball BGA, Green BC BCG ZA Silicon revision 12NT3 12-lane, 3-port PES PCI Express Switch H 89 1.0V +/- 0.1V Core Voltage Serial Switching Product Valid Combinations 89HPES12NT3ZABC 89HPES12NT3ZABCG 324-pin BC324 package, Commercial Temperature 324-pin Green BC324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 29 of 29 April 11, 2007