89HPES12T3G2

12-Lane 3-Port Gen2 PCI Express® Switch ® 89HPES12T3G2 Data Sheet Advance Information* Device Overview The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and two downstream ports and supports switching between downstream ports. High Performance PCI Express Switch – Twelve 5 Gbps Gen2 PCI Express lanes – Three switch ports • One x4 upstream port • Two x4 downstream ports – Low latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 2.0 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device configuration from serial EEPROM ◆ Features Block Diagram 3-Port Switch Core / 12 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Multiplexer / Demultiplexer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer Multiplexer / Demultiplexer Phy Logical Layer SerDes SerDes SerDes (Port 0) (Port 2) Figure 1 Internal Block Diagram (Port 4) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 31 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice September 4, 2007 DSC 6930 Advance Information Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed) • Receive equalization (RxEQ) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap ◆ Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Express Power Management Interface specification (PCI-PM 2.0) ◆ IDT 89HPES12T3G2 Data Sheet – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state ◆ Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Nine General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in a 19mm x 19mm, 324-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES12T3G2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 12 GBps (96 Gbps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES12T3G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES12T3G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. SMBus Interface The PES12T3G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES12T3G2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES12T3G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Bit 1 2 3 4 5 6 7 Slave SMBus Address SSMBADDR[1] SSMBADDR[2] SSMBADDR[3] 0 SSMBADDR[5] 1 1 Master SMBus Address MSMBADDR[1] MSMBADDR[2] MSMBADDR[3] MSMBADDR[4] 1 0 1 Table 1 Master and Slave SMBus Address Assignment Processor Processor North Bridge Memory Memory Memory Memory x4 PES12T3G2 x4 PCI Express Slot x4 I/O 10GbE x4 I/O 10GbE I/O SATA As shown in Figure 2, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 2(a), the master and slave SMBuses are tied together and the PES12T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES12T3G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES12T3G2 may be configured to operate in a split configuration as shown in Figure 2(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES12T3G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. Figure 2 I/O Expansion Application 2 of 31 *Notice: The information in this document is subject to change without notice September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet PES12T3G2 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES12T3G2 Processor SMBus Master ... Other SMBus Devices SSMBCLK SSMBDAT MSMBCLK MSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBDAT Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses Figure 2 SMBus Interface Configuration Examples Hot-Plug Interface The PES12T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES12T3G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES12T3G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES12T3G2. In response to an I/O expander interrupt, the PES12T3G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES12T3G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. 3 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES12T3G2, the two downstream ports are labeled port 2 and port 4. Signal PE0RP[3:0] PE0RN[3:0] PE0TP[3:0] PE0TN[3:0] PE2RP[3:0] PE2RN[3:0] PE2TP[3:0] PE2TN[3:0] PE4RP[3:0] PE4RN[3:0] PE4TP[3:0] PE4TN[3:0] PEREFCLKP[0] PEREFCLKN[0] Type I O I O I O I Name/Description PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins REFCLKM I Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type I I/O I/O I I/O I/O Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins 4 of 31 September 4, 2007 Advance Information PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. IDT 89HPES12T3G2 Data Sheet Signal GPIO[0] Type I/O Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O expander interrupt 0 input. GPIO[1] I/O GPIO[2] I/O GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins GPIO[5] GPIO[6] GPIO[7] I/O I/O I/O GPIO[11] I/O 5 of 31 September 4, 2007 Advance Information GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. IDT 89HPES12T3G2 Data Sheet Signal CCLKDS Type I Name/Description Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port’s PCIELSTS register. Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Fundamental Reset. Assertion of this signal resets all logic inside PES12T3G2 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES12T3G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES12T3G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 5 System Pins CCLKUS I MSMBSMODE I PERSTN RSTHALT I I SWMODE[2:0] I Signal JTAG_TCK Type I Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 6 Test Pins (Part 1 of 2) JTAG_TDI I 6 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Signal JTAG_TDO Type O Name/Description JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins (Part 2 of 2) JTAG_TMS JTAG_TRST_N I I Signal REFRES0 Type I/O Name/Description Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Analog Power. Serdes analog power supply (1.0V). PCI Express Analog High Power. Serdes analog power supply (2.5V). PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). Ground. REFRES2 I/O REFRES4 I/O VDDCORE VDDI/O VDDPEA VDDPEHA VDDPETA VSS I I I I I I Table 7 Power, Ground, and SerDes Resistor Pins 7 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Pin Characteristics Note: Some input pads of the PES12T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface Pin Name PE0RN[3:0] PE0RP[3:0] PE0TN[3:0] PE0TP[3:0] PE2RN[3:0] PE2RP[3:0] PE2TN[3:0] PE2TP[3:0] PE4RN[3:0] PE4RP[3:0] PE4TN[3:0] PE4TP[3:0] PEREFCLKN[0] PEREFCLKP[0] REFCLKM Type I I O O I I O O I I O O I I I I I/O I/O I I/O I/O I/O I I I I I I I I O I I Buffer CML I/O Type Serial Link Internal Resistor1 Notes Diff. Clock Input LVTTL LVTTL Input Input STI2 STI Input STI STI LVTTL LVTTL STI, High Drive Input Input Input STI Input Input LVTTL STI STI STI STI pull-down pull-down pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-down pull-up pull-down pull-up Refer to Table 9 SMBus MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT pull-up on board pull-up on board pull-up on board pull-up on board General Purpose I/O System Pins GPIO[15:0] CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[2:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Table 8 Pin Characteristics (Part 1 of 2) 8 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Function SerDes Reference Resistors Pin Name REFRES0 REFRES2 REFRES4 1. Internal 2. Type I/O I/O I/O Buffer Analog I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2) resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. Schmitt Trigger Input (STI). 9 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Logic Diagram — PES12T3G2 Reference Clocks Reference Clock Frequency Selection PCI Express Switch SerDes Input Port 0 PEREFCLKP[0] PEREFCLKN[0] REFCLKM PE0TP[0] PE0TN[0] ... PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PE4RP[0] PE4RN[0] PE4RP[3] PE4RN[3] PE0TP[3] PE0TN[3] PE2TP[0] PE2TN[0] PE2TP[3] PE2TN[3] PE4TP[0] PE4TN[0] PCI Express Switch SerDes Output Port 0 ... PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Output Port 2 ... ... PES12T3G2 4 9 PE4TP[3] PE4TN[3] Master SMBus Interface MSMBADDR[4:1] MSMBCLK MSMBDAT GPIO[11,7:0] General Purpose I/O Slave SMBus Interface SSMBADDR[5,3:1] SSMBCLK SSMBDAT 4 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N REFRES0 REFRES2 REFRES4 JTAG Pins System Pins MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0] SerDes Reference Resistors 3 VDDCORE VDDI/O VDDPEA VDDPEHA VDDPETA VSS Power/Ground Figure 3 PES12T3G2 Logic Diagram 10 of 31 September 4, 2007 Advance Information PCI Express Switch SerDes Input Port 4 PCI Express Switch SerDes Output Port 4 ... ... IDT 89HPES12T3G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. Parameter RefclkFREQ TC-RISE TC-FALL VIH VIL VCROSS VCROSS-DELTA VRB TSTABLE TPERIOD-AVG TPERIOD-ABS TCC-JITTER VMAX VMIN Duty Cycle Rise/Fall Matching ZC-DC 1. Description Input reference clock frequency range Rising edge rate Falling edge rate Differential input high voltage Differential input low voltage Absolute single-ended crossing point voltage Variation of VCROSS over all rising clock edges Ring back voltage margin Time before VRB is allowed Average clock period accuracy Absolute period, including spread-spectrum and jitter Cycle to cycle jitter Absolute maximum input voltage Absolute minimum input voltage Duty cycle Single ended rising Refclk edge rate versus falling Refclk edge rate Clock source output DC impedance Condition Min 100 Typical Max 1251 4 4 Unit MHz V/ns V/ns mV Differential Differential Differential Differential Single-ended Single-ended Differential Differential 0.6 0.6 +150 -150 +250 +550 +140 -100 500 -300 9.847 2800 10.203 150 +1.15 -0.3 40 20 40 60 60 +100 mV mV mV mV ps ppm ns ps V V % % Ω Table 9 Input Clock Requirements The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. AC Timing Characteristics Gen 1 Min1 Typ1 Max1 Min1 Gen 2 Typ1 Max1 Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER Description Units Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median TX Rise/Fall Time: 20% - 80% Minimum time in idle 399.88 0.75 400 400.12 199.94 0.75 200 200.06 ps UI UI 0.125 0.125 20 0.15 20 TTX-RISE, TTX-FALL TTX- IDLE-MIN UI UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2) 11 of 31 September 4, 2007 Advance Information IDT 89HPES12T3G2 Data Sheet Gen 1 Min1 Typ1 Max1 8 8 1.3 NA HPF: 1.5MHz NA NA 0.9 HPF: 1.0MHz 0.15 0.1 Min1 Gen 2 Typ1 Max1 8 8 1.3 Parameter TTX-IDLE-SET-TOIDLE Description Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Transmitter data skew between any 2 lanes Minimum Instantaneous Lone Pulse Width Transmit Jitter Measurement Filter Transmitter Deterministic Jitter > 1.5MHz Bandwidth Rise/Fall Time Differential Mismatch Units ns ns ns UI MHz UI UI TTX-IDLE-TO-DIFFDATA TTX-SKEW TMIN-PULSED TMEAS-HPF TTX-HF-DJ-DD TRF-MISMATCH PCIe Receive UI TRX-EYE (with jitter) TRX-EYE-MEDIUM TO MAX JITTER Unit Interval Minimum Receiver Eye Width (jitter tolerance) Max time between jitter median & max deviation Lane to lane input skew 1.5 — 100 MHz RMS jitter Maximum tolerable DJ by the receiver 10 KHz to 1.5 MHz RMS jitter Minimum receiver instantaneous eye width 399.88 0.4 400 400.12 199.94 0.4 200.06 ps 0.3 20 NA NA NA NA 0.6 8 4.2 8.8 4.2 UI ns ps ps ps UI TRX-SKEW TRX-HF-RMS TRX-HF-DJ-DD TRX-LF-RMS TRX-MIN-PULSE 1. Table 10 PCIe AC Timing Characteristics (Part 2 of 2) Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal GPIO GPIO[15:0]1 1. 2. Symbol Reference Min Max Unit Edge Timing Diagram Reference Tpw2 None 50 — ns Table 11 GPIO AC Timing Characteristics GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. The values for this symbol were determined by calculation, not by testing. 12 of 31 September 4, 2007 Advance Information UI IDT 89HPES12T3G2 Data Sheet Signal JTAG JTAG_TCK Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a Thigh_16a, Tlow_16a none 50.0 10.0 — 25.0 — — 20 20 — ns ns ns ns ns ns ns See Figure 4. JTAG_TMS1, JTAG_TDI JTAG_TDO Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2 JTAG_TCK rising 2.4 1.0 JTAG_TCK falling — — JTAG_TRST_N 1. none 25.0 Table 12 JTAG AC Timing Characteristics 2. The values for this symbol were determined by calculation, not by testing. Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 4 JTAG AC Timing Waveform Tdz_16c Tper_16a 13 of 31 September 4, 2007 Advance Information The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. IDT 89HPES12T3G2 Data Sheet Recommended Operating Supply Voltages Symbol VDDCORE VDDI/O VDDPEA 1 2 Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Analog Power PCI Express Analog High Power PCI Express Transmitter Analog Voltage Common ground Minimum 0.9 3.135 0.95 2.25 0.95 0 Typical 1.0 3.3 1.0 2.5 1.0 0 Maximum 1.1 3.465 1.1 2.75 1.1 0 Unit V V V V V V VDDPEHA VDDPETA VSS 1. 2. Table 13 PES12T3G2 Operating Voltages VDDPEA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value. During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Grade Commercial Temperature 0°C to +70°C Ambient Table 14 PES12T3G2 Operating Temperatures 14 of 31 September 4, 2007 Advance Information Power-Up/Power-Down Sequence IDT 89HPES12T3G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Number of active Lanes per Port Core Supply Typ 1.0V Max 1.1V PCIe Analog Supply Typ 1.0V Max 1.1V PCIe Analog High Supply Typ 2.5V Max 2.75V PCIe Termination Supply Typ 1.0V Max 1.1V I/O Supply Typ 3.3V Max 3.465V Total Typ Power Max Power 4/4/4 mA Watts 750 0.75 TBD TBD 1000 1.1 TBD TBD 386 0.38 TBD TBD 516 0.56 TBD TBD 202 0.5 TBD TBD 270 0.74 TBD TBD 271 0.27 TBD TBD 362 0.39 TBD TBD 10 .03 TBD TBD 10 .034 TBD TBD 1.95W 2.81W 4/2/2 mA Watts Thermal Considerations This section describes thermal considerations for the PES12T3G2 (19mm2 CABGA324 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES12T3G2 switch. Symbol TJ(max) TA(max) θJC P Parameter Junction Temperature Ambient Temperature Thermal Resistance, Junction-to-Case Power Dissipation of the Device Value 125 70 7.6 2.81 Units oC oC oC/W Conditions Maximum Maximum Maximum Watts Table 16 Thermal Specifications for PES12T3G2, 19x19 mm CABGA324 Package Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value specified in Table 16. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 16), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. 15 of 31 September 4, 2007 Advance Information Table 15 PES12T3G2 Power Consumption IDT 89HPES12T3G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. Gen 1 Min1 Serial Link PCIe Transmit VTX-DIFFp-p VTX-DIFFp-p-LOW VTX-DE-RATIO3.5dB I/O Type Parameter Description Gen 2 Max1 Min1 Typ1 Max1 Unit Conditions Typ1 Differential peak-to-peak output voltage Low-Drive Differential Peak to Peak Output Voltage De-emphasized differential output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss 800 400 -3 NA 0 1200 1200 -4 800 400 -3.0 -5.5 -3.5 -6.0 1200 1200 -4.0 -6.5 3.6 mV mV dB dB V mV 6.0dB VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta 3.6 20 100 25 20 600 0 100 25 20 600 10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz 6 mV mV mV mV dB VTX-CM-DC-linedelta VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF 10 RLTX-CM ZTX-DIFF-DC VTX-CM-ACpp VTX-DC-CM Transmitter Common Mode Return loss DC Differential TX impedance Peak-Peak AC Common Transmit Driver DC Common Mode Voltage 6 80 100 NA 0 3.6 600 0 120 dB Ω mV V mV 120 100 3.6 600 VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detection ITX-SHORT Transmitter Short Circuit Current Limit 0 90 90 mA Table 17 DC Electrical Characteristics (Part 1 of 3) 16 of 31 September 4, 2007 Advance Information VTX-DE-RATIO- IDT 89HPES12T3G2 Data Sheet Gen 1 Min1 Serial Link (cont.) PCIe Receive VRX-DIFFp-p RLRX-DIFF Differential input voltage (peakto-peak) Receiver Differential Return Loss 175 10 1200 120 1200 10dB: 0.05 1.25GHz 8dB: 1.25 2.5GHz 6 100 50 350k 50k 120 60 Refer to return loss spec 40 60 50k 50k mV dB Typ1 Max1 Min1 Gen 2 Typ1 Max1 Unit Conditions I/O Type Parameter Description RLRX-CM ZRX-DIFF-DC ZRX--DC ZRX-COMM-DC ZRX-HIGH-IMPDC-POS Receiver Common Mode Return Loss Differential input impedance (DC) DC common mode impedance Powered down input common mode impedance (DC) DC input CM input impedance for V>0 during reset or power down DC input CM input impedance for V