89TSF552BL

Traffic Manager Co-processor Data Sheet 89TTM553 Preliminary Information* Description The 89TTM553 is a flow-based traffic management co-processor that can be used in conjunction with the 89TTM552. It has two major functional parts: the queue manager (QM) and the FLQ scheduler. The QM is responsible for all the non-bandwidth functions, which include managing up to 1 Million queuing structures, handling cell and packet arrivals and departures from these queues, and maintaining a database of congestion management and statistics parameters for each flow queue (FLQ). The FLQ scheduler is responsible for managing the FLQ bandwidth functions. The 89TTM553 FLQ scheduler supports traffic scheduling on up to 1M discrete flows. In addition to the scheduling levels provided by the 89TTM552, the 89TTM553 provides one or two levels of additional scheduling hierarchy. It also provides guaranteed minimum rate, maximum rate capping, excess rate distribution using weighted fair queuing (WFQ), byte rate shaping, and dynamic configuration adjustments. The 89TTM553 stores all the flow-based parameters (and state information) that are made available to the 89TTM552 for flow-based processing. When the 89TTM553 is used with the 89TTM552, congestion and bandwidth management features are enabled at the flow level as well as at the aggregate-flow level. 89TTM55x Features 89TTM55x Features Deterministic performance at 10 Gbps wire-speed (35 Mcps) regardless of the number of flows, traffic size, and patterns. x Up to 256 megabytes of external memory buffer space (equivalent to a 210 ms buffer at 10 Gbps). x Support (Rx and Tx) for industry-standard SPI-4 phase 2, NPF Streaming Interface, and CSIX over LVDS. x Hierarchical queuing and precise scheduling: – Traffic management flexibility. – Support for up to 4K aggregate flow queues (AFQs), 1K port queues (PQs), 2K arrival reassembly queues (ARQs), and 1K output queues/channels (OQs) with no external memory required. Configurable AFQ-to-port assignments. – Support for up to 1M discrete flows (FLQs), with queuing for each flow, using external memory. Configurable mapping of FLQs into aggregate flow queues. – Two-level FLQ scheduling mode that supports up to 128K or 256K virtual pipe or subscriber queues with up to 8 or 4 CoS priority queues each. – Accurate byte-rate shaping at the FLQ, AFQ and port levels. x Multiple levels of buffer congestion management. – Hierarchical queue structure and thresholding. – Congestion indication. – Dynamic adjustment of thresholds during periods of congestion. – Packet discard (PD). – Weighted random early discard (WRED). – Local congestion indication (CI). x IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 30  2005 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice March 3, 2005 DSC 6797 IDT 89TTM553 Configurable forwarding based on classification index. Two ports for obtaining event-based statistics. x Configurable on-chip diagnostic statistics. x Bandwidth management rate guarantee and shaping mechanisms for each flow, each aggregate flow and each port queue. – Priority and weighted bandwidth distribution mechanisms across groups of flows and aggregate flows. – Schedules rates as low as 2 kbps for each flow. – One- and two-level byte-rate FLQ scheduling: maximum and minimum rates, and strict priority and weighted fair queuing (WFQ) for each FLQ. Per-flow byte-rate shaping. – AFQ scheduling with byte-rate shaping: minimum and maximum rates with VBR MBS and PCR enforcement. Excess distribution using weighted fair queuing (WFQ) and PRR. – Port queues: maximum rates with byte-rate scheduling. x Wire-speed logical multicasting. – Four classes of service. – Programmable service rate (minimum and excess bandwidth distribution). – Programmable thresholds. – Branch connections can be added and deleted during live traffic. – Traffic management features on all multicast roots and branches. x Multicast label generation for spatial multicast support. x Integrated wire-speed AAL-5 segmentation and reassembly (AAL-5 CPCS SAR) in the datapath. x 32-bit processor interface running at up to 66 MHz with integrated AAL-5 SAR and DMA engine for data insertion and extraction. – Four classes of service. – Integrated AAL-5-compliant and packet-based SAR. – Programmable service rate. – Programmable queue thresholds. – Use of descriptors and DMA support for maximum performance. – 16-bit data bus transfer at up to 66 MHz. x Algorithms implemented in hardware; software intervention required for initialization and configuration only. x Error protection on all external RAM and BIST on all internal RAM. x Inter-operable with the IDT ZTM200 traffic manager. x x 2 of 30 March 3, 2005 IDT 89TTM553 89TTM55x Functional Block Diagram Data Buffer Memory (DDR SDRAM) 89TTM552 Multicast Engine (DFC) SPI-4.2 or Streaming Interface or SIX-over-LVDS Control Path SAR (SAR) CPU and Peripheral Interface (CPIF, DMA) ZBus Rx DSR, BRX Memory Controller (PBC) OQ Manager (VOQM, BPQ) Datapath AAL-5 SAR (ILS) Tx DST, BTX SPI-4.2 or Streaming Interface or CSIX-over-LVD Forwarding and Thresholding Engine (AC) Queue Manager (QM) Packet Scheduler (SS) Statistics Processor (SP) External Statistics Port Extended Scheduler Interface 89TTM553 89TTM552-to-89TTM553 Interface Statistics Processor (SP) Packet Scheduler (ARS, GS, WFQ) Forwarding and Thresholding Engine (AC) Queue Manager (QM) CPU and Peripheral Interface (CPIF, DMA) ZBus 3 of 30 March 3, 2005 IDT 89TTM553 89TTM553 Pin Description Note: Information in this section is subject to change. Contact your IDT FAE before making design decisions. In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bi-directional, and P for power. Signal Name BLL_CLK_CP, BLL_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks BLL QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. BLL QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. BLL QDR SRAM address outputs. BLL QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. BLL QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations BLL QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. BLL QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V BLL_CLK_KP, BLL_CLK_KN BLL_ADDR[21:0] BLL_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz BLL_DIN[17:0] 1.5V HSTL Class 1 I 175 MHz BLL_WR_N 1.5V HSTL Class 1 O 175 MHz BLL_DOUT[17:0] BLL_VREF 1.5V HSTL Class 1 0.75V O — 175 MHz — Table 1 Buffer Linked List QDR SRAM Signal Name BXT_CLK_CP, BXT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks BXT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. BXT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. BXT QDR SRAM address outputs. BXT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. BXT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations BXT_CLK_KP, BXT_CLK_KN BXT_ADDR[21:0] BXT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz BXT_DIN[3:0] 1.5V HSTL Class 1 I 175 MHz Table 2 Buffer Linked List Extension QDR SRAM (Part 1 of 2) 4 of 30 March 3, 2005 IDT 89TTM553 Signal Name BXT_WR_N I/O Type 1.5V HSTL Class 1 Dir. O Freq. 175 MHz Remarks BXT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. BXT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V BXT_DOUT[3:0] BXT_LLT_VREF 1.5V HSTL Class 1 0.75V O — 175 MHz — Table 2 Buffer Linked List Extension QDR SRAM (Part 2 of 2) Signal Name FCT_CLK_CP, FCT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks FCT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. FCT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. FCT QDR SRAM address outputs. FCT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. FCT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations FCT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. FCT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V FCT_CLK_KP, FCT_CLK_KN FCT_ADDR[19:0] FCT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz FCT_DIN[27:0] 1.5V HSTL Class 1 I 175 MHz FCT_WR_N 1.5V HSTL Class 1 O 175 MHz FCT_DOUT[27:0] FCT_VREF[1:0] 1.5V HSTL Class 1 0.75 O — 175 MHz — Table 3 Flow Control Table QDR SRAM Signal Name FPT_CLK_CP, FPT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks FPT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. FPT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. FPT QDR SRAM address outputs. FPT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. FPT_CLK_KP, FPT_CLK_KN FPT_ADDR[20:0] FPT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz Table 4 Flow Parameters Table QDR SRAM (Part 1 of 2) 5 of 30 March 3, 2005 IDT 89TTM553 Signal Name FPT_DIN[35:0] I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks FPT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations FPT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. FPT QDR SRAM synchronous write byte enables (active low) FPT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V FPT_WR_N 1.5V HSTL Class 1 O 175 MHz FPT_BW_N[3:0] FPT_DOUT[35:0] FPT_VREF[1:0] 1.5V HSTL Class 1 1.5V HSTL Class 1 0.75V O O — 175 MHz 175 MHz — Table 4 Flow Parameters Table QDR SRAM (Part 2 of 2) Signal Name GPT_CLK_CP, GPT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks GPT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. GPT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. GPT QDR SRAM address outputs. GPT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. GPT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations. GPT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. GPT QDR SRAM synchronous byte enables (active low). GPT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations. HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V GPT_CLK_KP, GPT_CLK_KN GPT_ADDR[20:0] GPT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz GPT_DIN[17:0] 1.5V HSTL Class 1 I 175 MHz GPT_WR_N 1.5V HSTL Class 1 O 175 MHz GPT_BW_N[1:0] GPT_DOUT[17:0] GPT_VREF 1.5V HSTL Class 1 1.5V HSTL Class 1 0.75V O O — 175 MHz 175 MHz — Table 5 Group Parameters Table QDR SRAM 6 of 30 March 3, 2005 IDT 89TTM553 Signal Name HT_CLK_CP, HT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks HT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. HT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. HT QDR SRAM address outputs. HT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. HT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations. HT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. HT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations. HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V HT_CLK_KP, HT_CLK_KN HT_ADDR[19:0] HT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz HT_DIN[35:0] 1.5V HSTL Class 1 I 175 MHz HT_WR_N 1.5V HSTL Class 1 O 175 MHz HT_DOUT[35:0] HT_VREF[1:0] 1.5V HSTL Class 1 0.75V O — 175 MHz — Table 6 Head Tail QDR SRAM Signal Name LLT_CLK_CP, LLT_CLK_CN I/O Type 1.5V HSTL Class 1 Dir. I Freq. 175 MHz Remarks LLT QDR SRAM input clock: This clock pair registers data inputs on the rising edge of C and C#. All synchronous inputs must meet setup and hold times around the clock rising edges. LLT QDR SRAM output clock: This clock pair times the control outputs to the rising edge of K, and times the address and data outputs to the rising edge of K and K#. LLT QDR SRAM address outputs. LLT QDR SRAM synchronous read output (active low): When asserted, a read cycle is initiated to the external QDR SRAM devices. LLT QDR SRAM data inputs: Input data must meet setup and hold times around the rising edges of C and C# during read operations. LLT QDR SRAM synchronous write output (active low): When asserted, a write cycle is initiated to the external QDR SRAM devices. LLT QDR SRAM write data outputs: Output data is synchronized to the K and K# during write operations. LLT_CLK_KP, LLT_CLK_KN LLT_ADDR[19:0] LLT_RD_N 1.5V HSTL Class 1 O 175 MHz 1.5V HSTL Class 1 1.5V HSTL Class 1 O O 175 MHz 175 MHz LLT_DIN[10:0] 1.5V HSTL Class 1 I 175 MHz LLT_WR_N 1.5V HSTL Class 1 O 175 MHz LLT_DOUT[10:0] 1.5V HSTL Class 1 O 175 MHz Table 7 Linked List Table QDR SRAM 7 of 30 March 3, 2005 IDT 89TTM553 Signal Name FLQS_DIN[14:0] FLQS_DIN_PRTY FLQS_DOUT[19:0] FLQS_DOUT_PRTY FLQS_CLKIN FLQS_CLKOUT FLQS_TIC_IN FLQS_TIC_OUT FLQS_VREF I/O Type 1.5V HSTL Class 1 1.5V HSTL Class 1 1.5V HSTL Class 1 1.5V HSTL Class 1 1.5V HSTL Class 1 1.5V HSTL Class 1 0.75V Dir. I O I O I O — Freq. 175 MHz 175 MHz 175 MHz 175 MHz 175 MHz 175 MHz — Remarks Control serial interface to 89TTM552 (15 signal lines + 1 parity line) Control serial interface to 89TTM552 (20 signal lines + 1 parity line) Clock input from 89TTM552 Clock output to 89TTM552 Cell time tic input from 89TTM552 Cell time tic out to 89TTM552 HSTL reference. Nominally VDDQ / 2, so connect to 0.75 V Table 8 89TTM552/89TTM553 Interface Signal Name ZBUS_AVALID_N I/O Type 3.3V LVTTL, 12mA drive, internal pullup 3.3V, no internal pullup 3.3V LVTTL, 12mA drive, internal pullup 3.3V, internal pullup 3.3V LVTTL, 12mA drive, internal pullup 3.3V, internal pullup 3.3V LVTTL, 12mA drive 3.3V LVTTL, 12mA drive, internal pullup 3.3V LVTTL, 12mA drive 3.3V LVTTL, 12mA drive Dir. B Freq. 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz 33 or 66 MHz Remarks ZBus address valid flag (active low) ZBUS_CLK ZBUS_AD[15:0] I B ZBus clock input (up to 66 MHz) ZBus 16-bit multiplexed address/data bus ZBUS_DEVID[4:0] ZBUS_DVALID_N I B Used for ZBus device identification ZBus data valid flag (active low) ZBUS_GNT_N ZBUS_INT_N[2:0] ZBUS_PRTY I O B ZBus grant (active low) ZBus device interrupt (active low) ZBus parity over address/data; one parity bit for 16 bits ZBUS_DIR ZBUS_REQ_N O O ZBus write/read flag ZBus master cycle request (active low) Table 9 Processor Interface (ZBus) 8 of 30 March 3, 2005 IDT 89TTM553 Signal Name IDDQ RESERVE_1 SCAN_EN RESERVE_0 I/O Type 3.3V, internal pulldown 3.3V LVTTL, 4 mA drive 3.3V 3.3V, internal pullup 3.3V 3.3V, internal pullup 3.3V LVTTL, 12 mA drive 3.3V, internal pullup 3.3V, internal pullup Dir. I O I I Freq. N/A N/A N/A N/A Remarks IDDQ input (active high). For IDT use only. Do not connect. For IDT use only. Do not connect. Scan enable (active high) For IDT use only. Attach to a 4.7K resistor to 0V Tristate enable (active low) For IDT use only. Attach to a 4.7K resistor to 3.3V JTAG (IEEE 1149.1) clock input. JTAG (IEEE 1149.1) test data input. JTAG (IEEE 1149.1) test data output. JTAG (IEEE 1149.1) test mode select JTAG (IEEE 1149.1) test reset input. TCK TDI TDO TMS TRST_N I I O I I — — — — — Table 10 Test I/O Signal Name PLL_2X_BPCLK PLL_BP_MODE PLL_MON PLL_CFG_OVR PLL_RST PLL_VDDA PLL_VSSA PLL_SYS_REFCLK RESET_N VDD18 VDD15 I/O Type 3.3V, internal pulldown 3.3V, internal pulldown 3.3V LVTTL, 12mA drive 3.3V, internal pulldown 3.3V 1.8V — 3.3V 3.3V, internal pullup — — Dir. I I O I I — — I I — — Freq. N/A N/A N/A N/A Async — — 100 MHz Async — — Remarks Bypass Clock Input For IDT use only. Do not connect. Bypass Clock Input For IDT use only. Do not connect. PLL Monitor For IDT use only. Do not connect. PLL Configuration Override PLL reset. A special initialization sequence is required. PLL Analog VDD PLL Analog VSS Chip core PLL reference clock. Chip reset input (active low). 1.8V core power 1.5V I/O power for HSTL-2 I/Os: Isolated output buffer supply set nominally to 1.5V Table 11 PLL I/O (Part 1 of 2) 9 of 30 March 3, 2005 IDT 89TTM553 Signal Name VDD33 N/C GND — — — I/O Type Dir. — — I Freq. — N/A N/A Remarks 3.3V I/O power for LVTTL I/Os Do not connect. Ground Table 11 PLL I/O (Part 2 of 2) 89TTM553 Electrical Specifications Some data are TBD and will be published as they become available. The specifications are subject to change without notice. Absolute Maximum Ratings The absolute maximum ratings are the maximum conditions that the device can withstand without sustaining permanent damage. Exceeding any of these conditions could result in permanent damage to the device. Normal operation should not be expected at these conditions. In addition, exposure to absolute maximum rated conditions (or near absolute maximum rated conditions) for extended periods may affect device reliability. Operation of the device is not guaranteed at the absolute maximum ratings, but rather at the operating conditions outlined in “DC Characteristics” on page 11 and “AC Characteristics” on page 12. Symbol TJMAX TSTORAGE TSOLDER TREWORK Parameter Junction temperature under bias Storage temperature Storage temperature range Soldering temperature Rework temperature Min — — –40 — — Table 12 Absolute Maximum Ratings Max 105 150 85 215 204 Units °C °C °C °C °C Long term storage Conditions Operating Ranges Symbol TJ IV15 IV18 IV33 VDD15 VDD18 Parameter Operating junction temperature range Input current for 1.5V power supply Input current for 1.8V power supply Input current for 3.3V power supply 1.5V HSTL supply 1.8V Core supply Min 0 — — — 1.425 1.71 Typical — 800 1.16 60 1.5 1.8 Max 85 — — — 1.575 1.89 Units °C mA A mA V V ±5% ±5% Conditions Table 13 Operating Ranges (Part 1 of 2) 10 of 30 March 3, 2005 IDT 89TTM553 Symbol VDD33 VRFHSTL 1 Parameter 3.3V LVTTL supply 0.75V HSTL reference voltage Min 3.135 0.7125 — Typical 3.3 0.75 3.49 Max 3.465 0.7875 3.66 Units V V W Conditions ±5% ±5% Max. values use the maximum voltages and current listed in this table and typical values use the typical voltages and current. Power Dissipation Table 13 Operating Ranges (Part 2 of 2) 1. This operating range applies to the following pins: BLL_VREF, BXT_LLT_VREF, FCT_VREF[1:0], FPT_VREF[1:0], GPT_VREF, HT_VREF[1:0], and FLQS_VREF. DC Characteristics Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 13. Symbol VILHSTL (1.5v HSTL) VIHHSTL (1.5v HSTL) VIL33 (3.3v LVTTL) VIH33 (3.3v LVTTL) VOLHSTL VOHHSTL VOL33 VOH33 IILHSTL (1.5v HSTL) IIHHSTL (1.5v HSTL) IIL33 (3.3v pads w/o Pull Up/Down) IIH33 (3.3v pads w/o Pull Up/Down) IIL33PU (3.3v pads w/ Pull Up) Parameter Input low voltage for 1.5V HSTL inputs (VREF = 0.75V) Input high voltage for 1.5V HSTL inputs (VREF = 0.75V, VDDQ = 1.5V) Input low voltage for 3.3V LVTTL inputs Input high voltage for 3.3V LVTTL inputs Output low voltage for 1.5V HSTL outputs Output high voltage for 1.5V HSTL outputs (VDDQ = 1.5V) Output low voltage for 3.3V CMOS outputs (12mA pads) Output high voltage for 3.3V CMOS outputs (12mA pads) Input Leakage low current for 1.5V HSTL Inputs Input Leakage high current for 1.5V HSTL Inputs Input Leakage low current for 3.3V Inputs Input Leakage high current for 3.3V Inputs Input Leakage low current for 3.3V with PullUp Inputs Min — VREF+ 0.1 — 2.0 — VDDQ-0.4 — 2.4 -10 -10 -10 -10 -200 Typical VREF – 0.1 VDDQ+0.3 0.8 — 0.4 0.5 — 10 10 10 10 -10 Max V V V V V V V V uA uA uA uA uA Units 1.5v HSTL classI w/8mA Drive) 1.5v HSTL classI w/ 8mA Drive) 3.3v LVTTL w/ 12mA Drive 3.3v LVTTL w/ 12mA Drive Table 14 DC Parameters (Part 1 of 2) 11 of 30 March 3, 2005 IDT 89TTM553 Symbol IIH33PU (3.3v pads w/ Pull Up) IIL33PD (3.3v pads w/ Pull Down) IIH33PD (3.3v pads w/ Pull Down) Parameter Input Leakage high current for 3.3V with PullUp Inputs Input Leakage low current for 3.3V with PullDown Inputs Input Leakage high current for 3.3V with PullDown Inputs Min -10 -10 10 Typical +10 +10 200 Max uA uA uA Units Table 14 DC Parameters (Part 2 of 2) AC Characteristics Unless otherwise stated, the following parameters are provided given the conditions outlined in Table 13. Symbol fSYS TJSYS DSYS fZB DZB Parameter Frequency for system (core) clock reference Jitter requirements for system clock Percentage duty for system clock Frequency for ZBus clock Percentage duty for ZBus clock Table 15 System Clock Timing Min — — 45 33 45 Typical 100 — 50 33 50 Max — 80 55 66 55 Units MHz ps % MHz % Symbol TKQOV TKQOX TCQIS TCQIH Parameter K/K rising edge to address/data output valid K/K rising edge to address/data output invalid C/C rising edge to data input setup C/C rising edge to data input hold Table 16 QDR SSRAM Interface Timing 89TTM55x core clock frequency of 175 MHz. Min — 0.81 –0.2 — Typical — — — — Max 1.61 — — 1.6 Units ns ns ns ns 1. The parameter is specified at Symbol TKQV TKQX TKQLZ TKQHZ TS TH Parameter Zbus clock high to output valid Zbus clock high to output invalid Zbus clock high to output low-Z Zbus clock high to output high-Z Input setup time from system clock Input hold time from system clock Table 17 Zbus Interface Timing Min — 2.5 1.0 1.0 3.0 0 Typical — — — — — — Max 8.3 — 6.0 6.0 — — Units ns ns ns ns ns ns 12 of 30 March 3, 2005 IDT 89TTM553 AC Test Conditions Input Rise/Fall Time Output timing measurement reference level (VREF) for 3.3V interfaces Output load Table 18 AC Test Conditions 1 V / ns (20% / 80%) (VDDQ/2) V As shown in Figure 1 VDD Z0 = 50Ω For enable/disable spec 75Ω 50Ω 20 pF VREF 5 pF 75Ω For output timing Figure 1 AC Test Load Considerations 89TTM553 Thermal Considerations This section describes the temperature and heat sink calculations for flip-chip BGA devices. Symbol ØJA ØJB ØJC Parameter Thermal resistance, junction to ambient (no heat sink) Value 9.8 7.8 Units °C / W °C / W °C / W °C / W Conditions Max: still air. Typical: 200 FPM. Estimated thermal resistance, junction to board Thermal resistance, junction to case 3.1 0.7 Table 19 89TTM553 Thermal Characteristics The thermal circuit is as shown below. ØJB TA W2 (dissipated through board) TJ TA W1 ØJC ØCA Figure 2 89TTM553 Thermal Circuit Device Total Power =W 13 of 30 March 3, 2005 IDT 89TTM553 For flip-chip BGA devices, there are two paths for heat dissipation: one through the package balls to the board and other through the package case to air. The device specifications provide ØJB and ØJC numbers. The ØCA number comes from the heat sink manufacturer and depends on type of heat sink (area, height, fin type, etc.) and the airflow across the heat sink. The device specifications also provide the maximum operating junction temperature (TJ) that will not degrade the device reliability. The system designer should ensure that the device maximum junction temperature is not exceeded under any operating condition. One method of accomplishing this is to calculate the maximum ambient temperature (TA) that can be tolerated based on the above device parameters. The formula is shown below. ØJB x (ØJC + ØCA) TA = TJ - W x ----------------------ØJB + ØJC + ØCA The following graph depicts the ambient temperature (TA) versus ØCA. Ambient Temp. vs ØCA 90.0 80.0 70.0 o 81.0 79.7 78.8 78.2 77.7 77.2 76.9 76.6 C 60.0 TA 50.0 40.0 30.0 1.0 2.0 3.0 4.0 ØCA o 5.0 C/W 6.0 7.0 8.0 Figure 3 89TTM553 Ambient Temperature Curve For system designers, specification of the maximum device junction temperature (operating) is critical, since it allows them to select a heat sink that meets the maximum ambient temperature requirements of their system. The other parameter that is device package-specific is ØJA, without a heat sink, and is specified for various air-flow conditions. This is the intrinsic thermal resistance of the package (junction to case + case to ambient) and is mainly specified as a reference parameter. (This is when a heat sink is not present and the top surface of the package is essentially acting as the heat sink). However, in devices that have high power dissipation, heat sink usage is highly desirable. Consequently, system designers may have limited use for this parameter. 14 of 30 March 3, 2005 IDT 89TTM553 89TTM553 Reset Sequence A PLL reset sequence must be followed when resetting the 89TTM553 to ensure that clocks are stable when the chip comes out of reset. This section describes the reset sequence for the 89TTM553 device. The 89TTM553 uses data presented on the ZBus data and parity pins to determine the clock frequencies when the chip is in reset. The PLL_CFG_OVR pin controls this feature. When left high, the PLL will determine its clock frequency by sampling these values on the ZBus pins. The feature is not necessary if the default clock frequencies are desired. (The default frequency for the core clock is 133 MHz when a 100 MHz clock reference is used.) When default frequencies are desired, the PLL_CFG_OVR should be held low and it is not necessary to drive the ZBus data and parity lines during the reset. PLL Core PLL Frequency Setting Following is the summary of the reset sequence: 1. Assert chip reset. 2. Drive LOR (latch on reset) values on ZBus (described below) and enable configuration override on all PLLs. (Configuration override remains ON forever). 3. Reset PLLs. 4. Release reset on PLLs. 5. Release chip reset. 6. Release LOR value on ZBus. The following values must be driven on ZBUS_AD[ ] and ZBUS_PRTY before the reset sequences in order to set the chip operation frequency properly. Note that the setting is based on a 100MHz reference input clock (PLL_SYS_REFCLK pin). ZB_PRTY[1:0] = 0x3, must be driven “LOW” for the entire reset sequence cycles ZB_AD[31:16], and ZB_AD[15:0] = bits are set as: Core/system clock frequency 0x154F = 0x1527 = 0x153a = 0x1526 = 0x1538 = 0x1525 = 187.50MHz 175.00MHz 166.67MHz 150.00MHz 133.33MHz 125.00MHz 15 of 30 March 3, 2005 IDT 89TTM553 Reset Sequence Timing Diagram T0 T1 T2 T3 T4 T5 Power 10ms 10ms 10ms 10ms 10ms RESET_N ZBUS_AD[ ], ZBUS_PRTY[ ] PLL_CFG_OVR PLL_RST NOTE: - ZBUS_AD[ ] and ZBUS_PRTY[ ] are used to configure the chip operating frequency, and is listed on next page Figure 4 89TTM553 Reset Sequence Timing Diagram Pin List I/O Description The 89TTM553 Pin List on page 17 uses the following I/O notations: I O B P Input Output Bidirectional Power 16 of 30 March 3, 2005 IDT 89TTM553 89TTM553 Pin List Pin A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Pin Type P P I I I I P P I I O O P P O O O O P P O O O O P P O O O O P P P P P I I I I P P I B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Signal HT_DIN_32 HT_DOUT_13 HT_DOUT_12 VDD15 GND HT_DOUT_17 HT_CLK_KP HT_DOUT_34 HT_ADDR_15 GND VDD15 HT_ADDR_18 HT_ADDR_19 FCT_ADDR_17 FCT_ADDR_16 GND VDD15 FCT_DOUT_09 FCT_DOUT_08 FCT_DOUT_10 FCT_DOUT_11 VDD15 GND GND VDD15 VDD15 HT_DIN_03 HT_DIN_08 HT_DIN_09 HT_DIN_12 HT_DIN_11 VDD15 GND HT_DIN_28 HT_DIN_29 HT_DOUT_08 HT_DOUT_09 VDD15 GND HT_DOUT_21 HT_CLK_KN HT_ADDR_00 HT_ADDR_11 Type I O O P P O O O O P P O O O O P P O O O O P P P P P I I I I I P P I I O O P P O O O O Signal GND VDD15 HT_CLK_CN HT_CLK_CP HT_DIN_19 HT_DIN_20 VDD15 GND HT_DIN_34 HT_DIN_35 HT_DOUT_14 HT_DOUT_15 VDD15 GND HT_DOUT_16 HT_DOUT_31 HT_DOUT_35 HT_ADDR_14 GND VDD15 HT_ADDR_16 HT_ADDR_17 FCT_ADDR_12 FCT_ADDR_13 GND VDD15 FCT_DOUT_02 FCT_DOUT_03 FCT_DOUT_04 FCT_DOUT_05 VDD15 GND GND GND VDD15 HT_DIN_13 HT_DIN_14 HT_DIN_15 HT_DIN_16 VDD15 GND HT_DIN_33 17 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Signal GND VDD15 FCT_ADDR_01 FCT_ADDR_00 FCT_ADDR_18 FCT_ADDR_19 GND VDD15 FCT_DOUT_12 FCT_DOUT_13 FCT_DOUT_17 FCT_DOUT_16 FCT_DOUT_22 VDD15 VDD15 BLL_DIN_03 BLL_CLK_CP BLL_DIN_11 HT_DIN_02 HT_DIN_04 HT_DIN_06 HT_DIN_07 VDD15 GND HT_DIN_26 HT_DIN_27 HT_DOUT_06 HT_DOUT_07 VDD15 GND HT_DOUT_20 HT_DOUT_30 HT_ADDR_01 HT_ADDR_10 GND VDD15 FCT_ADDR_02 FCT_ADDR_03 FCT_CLK_KN FCT_CLK_KP GND VDD15 FCT_DOUT_18 Type P P O O O O P P O O O O O P P I I I I I I I P P I I O O P P O O O O P P O O O O P P O Pin D29 D30 D31 D32 D33 D34 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 F1 F2 F3 Signal FCT_DOUT_19 FCT_DOUT_20 FCT_DOUT_23 FCT_DIN_05 FCT_DIN_10 FCT_CLK_CP BLL_DIN_04 BLL_CLK_CN BLL_DIN_10 BLL_DIN_15 BLL_DIN_14 HT_DIN_05 HT_DIN_10 VDD15 GND HT_VREF_01 HT_DIN_25 HT_DOUT_05 HT_DOUT_04 VDD15 GND HT_DOUT_22 HT_DOUT_28 HT_ADDR_02 HT_ADDR_09 GND VDD15 FCT_ADDR_04 FCT_ADDR_05 FCT_DOUT_01 FCT_DOUT_00 GND VDD15 FCT_DIN_08 FCT_DOUT_21 FCT_DIN_01 FCT_DIN_00 FCT_DIN_04 FCT_DIN_09 FCT_CLK_CN BLL_DIN_00 BLL_DIN_06 BLL_DIN_08 Type O O O I I I I I I I I I I P P P I O O P P O O O O P P O O O O P P I O I I I I I I I I 18 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 Signal BLL_DIN_12 BLL_DIN_16 HT_DIN_00 HT_VREF_00 VDD15 GND HT_DIN_21 HT_DIN_22 HT_DOUT_00 HT_DOUT_01 VDD15 GND HT_DOUT_23 HT_DOUT_29 HT_ADDR_03 HT_ADDR_08 GND VDD15 FCT_ADDR_09 FCT_ADDR_08 FCT_ADDR_15 FCT_ADDR_14 GND VDD15 FCT_VREF_00 FCT_DOUT_25 FCT_DOUT_27 FCT_DIN_02 FCT_DIN_06 FCT_DIN_11 FCT_DIN_16 BLL_DOUT_17 BLL_DIN_05 BLL_DIN_09 BLL_DIN_13 BLL_DIN_17 HT_DIN_01 VDD15 VDD15 GND HT_DIN_31 HT_DIN_30 HT_DOUT_19 Type I I I P P P I I O O P P O O O O P P O O O O P P P O O I I I I O I I I I I P P P I I O Pin G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 Signal HT_DOUT_18 VDD15 GND HT_DOUT_24 HT_DOUT_25 HT_ADDR_07 HT_ADDR_06 GND VDD15 FCT_ADDR_10 FCT_ADDR_11 FCT_WR_N FCT_RD_N GND VDD15 VDD15 FCT_DOUT_24 FCT_DOUT_26 FCT_DIN_03 FCT_DIN_07 FCT_DIN_12 FCT_DIN_15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 GND BLL_DIN_07 HT_DIN_24 HT_DIN_23 HT_DOUT_11 HT_DOUT_10 VDD15 GND HT_DOUT_33 HT_DOUT_32 HT_ADDR_04 HT_ADDR_13 GND VDD15 Type O P P O O O O P P O O O O P P P O O I I I I P P P P P P P P I I I O O P P O O O O P P 19 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 Signal HT_WR_N HT_RD_N FCT_DOUT_07 FCT_DOUT_06 GND GND VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 GND GND GND GND GND GND GND GND BLL_VREF HT_DIN_18 HT_DIN_17 HT_DOUT_03 HT_DOUT_02 VDD15 GND HT_DOUT_27 HT_DOUT_26 HT_ADDR_05 HT_ADDR_12 GND VDD15 FCT_ADDR_07 FCT_ADDR_06 FCT_DOUT_15 FCT_DOUT_14 FCT_DIN_14 FCT_DIN_13 GND GND GND Type O O O O P P P P P P P P P P P P P P P P P P I I O O P P O O O O P P O O O O I I P P P Pin J31 J32 J33 J34 K1 K2 K3 K4 K5 K6 K7 K8 K9 K26 K27 K28 K29 K30 K31 K32 K33 K34 L1 L2 L3 L4 L5 L6 L7 L8 L9 L26 L27 L28 L29 L30 L31 L32 L33 L34 M1 M2 M3 Signal GND GND GND GND BLL_DOUT_02 BLL_DOUT_05 BLL_DOUT_08 BLL_DOUT_10 BLL_DOUT_13 BLL_DOUT_16 BLL_DOUT_03 BLL_DOUT_11 BLL_DIN_01 FCT_DIN_21 FLQS_DOUT_PRTY FCT_DIN_17 FCT_DIN_19 FCT_VREF_01 FCT_DIN_24 FCT_DIN_26 FLQS_DOUT_01 FLQS_DOUT_02 BLL_DOUT_01 BLL_DOUT_06 BLL_DOUT_07 BLL_DOUT_09 BLL_DOUT_14 BLL_DOUT_15 BLL_DOUT_04 BLL_DOUT_12 BLL_DIN_02 FCT_DIN_22 FLQS_TIC_OUT FCT_DIN_18 FCT_DIN_20 FCT_DIN_23 FCT_DIN_25 FCT_DIN_27 FLQS_DOUT_00 FLQS_DOUT_03 BLL_ADDR_13 BLL_ADDR_15 BLL_ADDR_18 Type P P P P O O O O O O O O I I O I I P I I O O O O O O O O O O I I O I I I I I O O O O O 20 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin M4 M5 M6 M7 M8 M9 M26 M27 M28 M29 M30 M31 M32 M33 M34 N1 N2 N3 N4 N5 N6 N7 N8 N9 N26 N27 N28 N29 N30 N31 N32 N33 N34 P1 P2 P3 P4 P5 P6 P7 P8 P9 P14 Signal BLL_CLK_KP BLL_ADDR_21 BLL_ADDR_02 BLL_DOUT_00 BLL_ADDR_01 BLL_ADDR_00 FLQS_DOUT_06 FLQS_DOUT_13 FLQS_TIC_IN FLQS_DOUT_04 FLQS_DOUT_09 FLQS_CLKOUT FLQS_DOUT_11 FLQS_DOUT_16 FLQS_DOUT_17 BLL_ADDR_12 BLL_ADDR_14 BLL_ADDR_19 BLL_CLK_KN BLL_ADDR_20 BLL_RD_N BLL_WR_N BLL_ADDR_17 BLL_ADDR_16 FLQS_DOUT_07 FLQS_DOUT_14 FLQS_DIN_14 FLQS_DOUT_05 FLQS_DOUT_08 FLQS_DOUT_10 FLQS_DOUT_12 FLQS_DOUT_15 FLQS_DOUT_18 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 GND Type O O O O O O O O I O O O O O O O O O O O O O O O O O I O O O O O O P P P P P P P P P P Pin P15 P16 P17 P18 P19 P20 P21 P26 P27 P28 P29 P30 P31 P32 P33 P34 R1 R2 R3 R4 R5 R6 R7 R8 R9 R14 R15 R16 R17 R18 R19 R20 R21 R26 R27 R28 R29 R30 R31 R32 R33 R34 T1 Signal VDD18 GND VDD18 GND VDD18 GND VDD18 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 GND GND GND GND GND GND GND GND GND VDD18 GND VDD18 GND VDD18 GND VDD18 GND GND GND GND GND GND GND GND GND GND BLL_ADDR_10 Type P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P O 21 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin T2 T3 T4 T5 T6 T7 T8 T9 T14 T15 T16 T17 T18 T19 T20 T21 T26 T27 T28 T29 T30 T31 T32 T33 T34 U1 U2 U3 U4 U5 U6 U7 U8 U9 U14 U15 U16 U17 U18 U19 U20 U21 U26 Signal BLL_ADDR_11 BLL_ADDR_07 BLL_ADDR_06 BLL_ADDR_05 BLL_ADDR_04 BXT_WR_N BLL_ADDR_09 BLL_ADDR_08 GND VDD18 GND VDD18 GND VDD18 GND VDD18 FLQS_VREF FLQS_DIN_01 FLQS_DIN_09 FLQS_DIN_10 FLQS_DIN_11 FLQS_DIN_13 FLQS_DIN_12 FLQS_DIN_PRTY FLQS_DOUT_19 BXT_ADDR_19 BXT_ADDR_18 BXT_ADDR_20 BXT_ADDR_21 BXT_ADDR_00 BXT_ADDR_01 BLL_ADDR_03 BXT_RD_N BXT_ADDR_02 VDD18 GND VDD18 GND VDD18 GND VDD18 GND FLQS_DIN_07 Type O O O O O O O O P P P P P P P P P I I I I I I I O O O O O O O O O O P P P P P P P P I Pin U27 U28 U29 U30 U31 U32 U33 U34 V1 V2 V3 V4 V5 V6 V7 V8 V9 V14 V15 V16 V17 V18 V19 V20 V21 V26 V27 V28 V29 V30 V31 V32 V33 V34 W1 W2 W3 W4 W5 W6 W7 W8 W9 Signal FLQS_DIN_00 FLQS_DIN_08 FLQS_DIN_06 FLQS_CLKIN FLQS_DIN_05 FLQS_DIN_04 FLQS_DIN_03 FLQS_DIN_02 BXT_ADDR_15 BXT_CLK_KP BXT_CLK_KN BXT_ADDR_14 BXT_ADDR_12 BXT_ADDR_13 BXT_ADDR_09 BXT_ADDR_17 BXT_ADDR_11 GND VDD18 GND VDD18 GND VDD18 GND VDD18 TDO TMS PLL_2X_BPCLK TDI TCK RESERVE_0 SCAN_EN IDDQ RESERVE_1 BXT_DOUT_01 BXT_DOUT_02 BXT_ADDR_05 BXT_ADDR_04 BXT_ADDR_06 BXT_ADDR_07 BXT_ADDR_08 BXT_ADDR_16 BXT_ADDR_10 Type I I I I I I I I O O O O O O O O O P P P P P P P P O I I I I I I I I O O O O O O O O O 22 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin W14 W15 W16 W17 W18 W19 W20 W21 W26 W27 W28 W29 W30 W31 W32 W33 W34 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Signal VDD18 GND VDD18 GND VDD18 GND VDD18 GND RESET_N PLL_SYS_REFCLK TRST_N PLL_BP_MODE PLL_MON PLL_CFG_OVR PLL_RST NC PLL_VSSA GND GND GND GND GND GND GND GND GND GND VDD18 GND VDD18 GND VDD18 GND VDD18 GND GND GND GND GND GND GND GND GND Type P P P P P P P P I I I I O I I I P P P P P P P P P P P P P P P P P P P P P P P P P P Pin AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 Signal VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD18 GND VDD18 GND VDD18 GND VDD18 GND VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 BXT_DOUT_00 BXT_CLK_CP BXT_DIN_00 LLT_DIN_09 LLT_DIN_06 LLT_DIN_04 BXT_ADDR_03 BXT_DIN_02 BXT_LLT_VREF ZBUS_AD_00 ZBUS_AD_01 ZBUS_AD_12 ZBUS_AD_11 ZBUS_AD_06 ZBUS_AD_04 ZBUS_AD_03 ZBUS_AVALID_N Type P P P P P P P P P P P P P P P P P P P P P P P P P P O I I I I I O I P B B B B B B B B 23 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin AB34 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AE1 AE2 AE3 AE4 AE5 AE6 Signal PLL_VDDA BXT_DIN_03 BXT_CLK_CN LLT_DIN_10 LLT_DIN_08 LLT_DIN_07 LLT_DIN_03 BXT_DOUT_03 BXT_DIN_01 LLT_DIN_05 ZBUS_AD_08 ZBUS_AD_09 ZBUS_AD_13 ZBUS_AD_10 ZBUS_AD_07 ZBUS_AD_05 ZBUS_AD_02 ZBUS_CLK NC LLT_CLK_CP LLT_DIN_01 LLT_DOUT_09 LLT_DOUT_07 LLT_DOUT_04 LLT_DOUT_01 LLT_WR_N LLT_DIN_00 LLT_DOUT_03 GPT_DIN_02 ZBUS_INT_N_01 ZBUS_DEVID_01 ZBUS_PRTY VDD33 ZBUS_DVALID_N VDD33 ZBUS_DEVID_03 ZBUS_AD_14 LLT_CLK_CN LLT_DIN_02 LLT_DOUT_08 LLT_DOUT_06 LLT_DOUT_05 LLT_DOUT_00 Type I I I I I I I O I I B B B B B B B I I I O O O O O I O I O I B P B P I B I I O O O O Pin AE7 AE8 AE9 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 Signal LLT_RD_N LLT_DOUT_10 LLT_DOUT_02 GPT_DIN_01 ZBUS_INT_N_00 ZBUS_DEVID_00 ZBUS_DIR ZBUS_INT_N_02 ZBUS_GNT_N ZBUS_DEVID_04 ZBUS_DEVID_02 ZBUS_AD_15 GND GND GND GND GND GND GND LLT_ADDR_16 LLT_ADDR_17 FPT_DIN_25 FPT_DIN_26 FPT_BW_N_01 FPT_BW_N_02 VDD15 GND FPT_ADDR_07 FPT_ADDR_00 FPT_DOUT_21 FPT_DOUT_22 GND VDD15 GPT_BW_N_00 GPT_BW_N_01 GPT_ADDR_00 GPT_ADDR_01 GPT_VREF GND GND GND GND GND Type O O O I O I O O I I I B P P P P P P P O O I I O O P P O O O O P P O O O O P P P P P P 24 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin AF32 AF33 AF34 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 AH1 AH2 AH3 AH4 AH5 AH6 Signal GND GND GND VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 GND GND FPT_DIN_17 FPT_DIN_18 FPT_ADDR_15 FPT_ADDR_16 VDD15 GND FPT_ADDR_08 FPT_DOUT_35 FPT_DOUT_29 FPT_DOUT_30 GND VDD15 FPT_DOUT_05 FPT_DOUT_06 GPT_ADDR_08 GPT_ADDR_09 GPT_DIN_07 GND VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 LLT_ADDR_18 LLT_ADDR_13 LLT_ADDR_07 LLT_CLK_KP LLT_ADDR_00 FPT_DIN_34 Type P P P P P P P P P P P P I I O O P P O O O O P P O O O O I P P P P P P P P O O O O O I Pin AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 Signal VDD15 VDD15 GND FPT_DIN_11 FPT_DIN_12 FPT_DIN_01 FPT_DIN_00 VDD15 GND FPT_ADDR_01 FPT_ADDR_02 FPT_DOUT_20 FPT_DOUT_19 GND VDD15 FPT_DOUT_13 FPT_DOUT_14 GPT_ADDR_14 GPT_ADDR_15 GND VDD15 VDD15 GPT_DOUT_01 GPT_DIN_17 GPT_DIN_13 GPT_DIN_09 GPT_DIN_05 ZBUS_REQ_N LLT_ADDR_19 LLT_ADDR_12 LLT_ADDR_06 LLT_CLK_KN LLT_ADDR_01 FPT_DIN_35 LLT_ADDR_09 VDD15 GND FPT_DIN_04 FPT_DIN_05 FPT_BW_N_03 FPT_WR_N VDD15 GND Type P P P I I I I P P O O O O P P O O O O P P P O I I I I O O O O O O I O P P I I O O P P 25 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 Signal FPT_ADDR_03 FPT_DOUT_34 FPT_DOUT_24 FPT_DOUT_18 GND VDD15 GPT_RD_N GPT_ADDR_20 GPT_ADDR_07 GPT_ADDR_06 GND VDD15 GPT_DOUT_10 GPT_DOUT_00 GPT_DIN_16 GPT_DIN_12 GPT_DIN_08 GPT_DIN_06 GPT_DIN_00 LLT_ADDR_15 LLT_ADDR_10 LLT_ADDR_04 LLT_ADDR_02 LLT_ADDR_03 FPT_DIN_31 LLT_ADDR_08 VDD15 GND FPT_DIN_13 FPT_DIN_14 FPT_BW_N_00 FPT_RD_N VDD15 GND FPT_ADDR_04 FPT_DOUT_33 FPT_DOUT_23 FPT_DOUT_17 GND VDD15 GPT_WR_N FPT_DOUT_00 GPT_ADDR_10 Type O O O O P P O O O O P P O O I I I I I O O O O O I O P P I I O O P P O O O O P P O O O Pin AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 Signal GPT_ADDR_11 GND VDD15 GPT_DOUT_11 GPT_DOUT_05 GPT_DIN_14 GPT_DIN_15 GPT_DIN_10 GPT_CLK_CN GPT_DIN_04 LLT_ADDR_14 LLT_ADDR_11 LLT_ADDR_05 FPT_DIN_33 FPT_DIN_30 FPT_DIN_29 FPT_VREF_01 VDD15 GND FPT_VREF_00 FPT_DIN_10 FPT_ADDR_20 FPT_ADDR_19 VDD15 GND FPT_ADDR_05 FPT_DOUT_32 FPT_DOUT_25 FPT_DOUT_15 GND VDD15 FPT_DOUT_02 FPT_DOUT_01 GPT_CLK_KP GPT_CLK_KN GND VDD15 GPT_DOUT_07 GPT_DOUT_06 GPT_DOUT_04 GPT_DOUT_02 GPT_DIN_11 GPT_CLK_CP Type O P P O O I I I I I O O O I I I P P P P I O O P P O O O O P P O O O O P P O O O O I I 26 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin AL34 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 Signal GPT_DIN_03 VDD15 VDD15 FPT_DIN_32 FPT_DIN_27 FPT_DIN_28 FPT_DIN_24 FPT_DIN_23 VDD15 GND FPT_DIN_09 FPT_DIN_08 FPT_ADDR_17 FPT_ADDR_18 VDD15 GND FPT_ADDR_06 FPT_DOUT_31 FPT_DOUT_26 FPT_DOUT_16 GND VDD15 FPT_DOUT_04 FPT_DOUT_03 GPT_ADDR_13 GPT_ADDR_12 GND VDD15 GPT_DOUT_12 GPT_DOUT_13 GPT_DOUT_09 GPT_DOUT_08 GPT_DOUT_03 VDD15 VDD15 GND GND VDD15 FPT_DIN_22 FPT_DIN_21 FPT_DIN_19 FPT_DIN_20 VDD15 Type I P P I I I I I P P I I O O P P O O O O P P O O O O P P O O O O O P P P P P I I I I P Pin AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 Signal GND FPT_DIN_06 FPT_DIN_07 FPT_ADDR_14 FPT_ADDR_13 VDD15 GND FPT_ADDR_10 FPT_CLK_KP FPT_DOUT_27 FPT_DOUT_12 GND VDD15 FPT_DOUT_07 FPT_DOUT_08 GPT_ADDR_16 GPT_ADDR_17 GND VDD15 GPT_DOUT_17 GPT_DOUT_16 GPT_DOUT_15 GPT_DOUT_14 VDD15 GND GND GND VDD15 FPT_CLK_CN FPT_CLK_CP FPT_DIN_16 FPT_DIN_15 VDD15 GND FPT_DIN_03 FPT_DIN_02 FPT_ADDR_12 FPT_ADDR_11 VDD15 GND FPT_ADDR_09 FPT_CLK_KN FPT_DOUT_28 Type P I I O O P P O O O O P P O O O O P P O O O O P P P P P I I I I P P I I O O P P O O O 27 of 30 *Notice: The information in this document is subject to change without notice March 3, 2005 IDT 89TTM553 Pin AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 Signal FPT_DOUT_11 GND VDD15 FPT_DOUT_10 FPT_DOUT_09 GPT_ADDR_19 GPT_ADDR_18 GND VDD15 GPT_ADDR_05 GPT_ADDR_04 GPT_ADDR_02 GPT_ADDR_03 VDD15 GND Type O P P O O O O P P O O O O P P 28 of 30 March 3, 2005 IDT 89TTM553 89TTM553 Package The package is an LSI Logic FPBGA-HP, having 960 pins, with 1 mm pitch; a 34 ×34 pin array; and a 35 × 35 mm enclosure. Figure 5 shows the package geometry. Figure 5 89TTM553 Package Diagram 29 of 30 March 3, 2005 IDT 89TTM553 Information Ordering Information NN Product Family A Operating Voltage AA Device Family 55x Product Detail A Package A Temp range Legend A = Alpha Character N = Numeric Character Blank Commercial Temperature (See Thermal Considerations section) BL 552 553 960-pin FCBGA Aggregate flow device Per flow device TM SF T 89 Valid Combinations 89TTM553BL 960-pin FCBGA package, Commercial Temperature Traffic Manager Switch Fabric 1.8V ±5% Core Voltage Serial Switching Product Revision History November 23, 2004: Initial publication by IDT. January 12, 2005: On page 14, deleted reference to LVDS in the Core PLL Frequency Setting heading. March 3, 2005: In Table 11, changed frequency for PLL_SYS_REFCLK from 125 to 100 MHz. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208 30 of 30 March 3, 2005