8S89834AKILF

Low Skew, 2-to-4 LVCMOS/LVTTL-toLVPECL/ECL Clock Multiplexer ICS8S89834I DATA SHEET General Description The ICS8S89834I is a high speed 2-to-4 LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer. HiPerClockS™ The ICS8S89834I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS8S89834I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. Features • • • • • • • • • • Four differential LVPECL/ECL output pairs Two LVCMOS/LVTTL clock inputs Maximum output frequency: 1GHz Output skew: 30ps (maximum) Part-to-part skew: 100ps (maximum) Propagation delay: 550ps (maximum) Additive phase jitter, RMS: 0.12ps (typical) Full 3.3V and 2.5V operating supply modes -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package ICS Block Diagram SEL Pullup Q0 nQ0 IN1 Pullup 1 IN2 Pullup 0 Q2 nQ2 EN Pullup D CK Q Q3 nQ3 Q1 nQ1 Pin Assignment nQ0 VCC Q1 1 nQ1 2 16 15 14 13 12 IN1 11 SEL 10 nc 9 IN2 5 Q3 Q2 3 nQ2 4 6 nQ3 7 VCC ICS8S89834I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View ICS8S89834AKI REVISION A FEBRUARY 4, 2010 1 ©2010 Integrated Device Technology, Inc. EN VEE Q0 8 ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Table 1. Pin Descriptions Number 1, 2 3, 4 5, 6 7, 14 Name Q1, nQ1 Q2, nQ2 Q3, nQ3 Vcc Output Output Output Power Type Description Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a 37kΩ pullup resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN1, IN2. LVTTL/LVCMOS interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. No connect. Pullup Pullup Select clock input. When LOW, selects IN2 and when HIGH selects IN1. LVCMOS/LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. Negative supply pin. Differential output pair. LVPECL/ECL interface levels. 8 EN Input Pullup 9 10 11 12 13 15, 16 IN2 nc SEL IN1 VEE Q0, nQ0 Input Unused Input Input Power Output Pullup NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units kΩ ICS8S89834AKI REVISION A FEBRUARY 4, 2010 2 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Function Tables Table 3A. Control Input Function Table Inputs EN 0 1 Selected Source IN1, IN2 IN1, IN2 Q[0:3] Disabled; LOW Enabled Outputs nQ[0:3] Disabled; HIGH Enabled NOTE: EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. Disabled Enabled IN1, IN2 EN nQx Qx Figure 1. EN Timing Diagram Table 3B. Truth Table Inputs IN1, IN2 0 1 X X X IN1, IN2 X X 0 1 X EN 1 1 1 1 0 0 Outputs Q[0:3] 0 1 0 1 (NOTE 1) nQ[0:3] 1 0 1 0 1 (NOTE 1) NOTE 1: On next negative transition of the input signal (IN). Table 3C. SEL Control Function Table SEL 0 1 . Input Selected IN2 IN1 ICS8S89834AKI REVISION A FEBRUARY 4, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuos Current Surge Current Operating Temperature Range, TA Package Thermal Impedance, θJA, (Junction-to-Ambient) Storage Temperature, TSTG Rating 4.6V (LVPECL mode, VEE = 0V) -4.6V (ECL mode, VCC = 0V) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA -40°C to +85°C 74.7°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = -40°C to 85°C Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.97 Typical 3.3 Maximum 3.63 52 Units V mA Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 52 Units V mA Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 2.5V ± 5% or 3.3V ± 10%, VEE = 0V, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions VCC = 3.3V VCC = 2.5V Input Low Voltage Input High Current Input Low Current VCC = 3.3V VCC = 2.5V VCC = VIN = 3.63V or 2.625V VCC = 3.63V or 2.625V, VIN = 0V -150 Minimum 2.2 1.7 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 10 Units V V V V µA µA VIL IIH IIL ICS8S89834AKI REVISION A FEBRUARY 4, 2010 4 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Test Conditions Minimum VCC – 1.145 VCC – 1.945 0.6 1.2 Typical Maximum VCC – 0.80 VCC – 1.60 1.0 2.0 Units V V V V NOTE 1: Outputs terminated with 50Ω to VCC - 2V. AC Electrical Characteristics Table 5. AC Characteristics, VCC = 2.5V ± 5% or or 3.3V ± 10%, TA = -40°C to 85°C Symbol fMAX tPLH tPHL tSW tsk(o) tsk(pp) tjit tS tH tR / tF odc Parameter Maximum Frequency Propagation Delay; Low-to-High; NOTE 1 Propagation Delay; High-to-Low; NOTE 1 Switchover Time Output Skew; NOTE 2, 3 Part-to-Part Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Clock Enable Setup Time Clock Enable Hold Time Output Rise/Fall Time Output Duty Cycle EN to IN1, IN2 EN to IN1, IN2 20% to 80% fMAX < 622MHz fMAX ≥ 622MHz 200MHz Integration Range: (12kHz - 20MHz) 300 500 50 48 45 250 52 55 0.12 SEL to Q 250 300 300 Test Conditions Minimum Typical Maximum 1 550 550 550 30 100 Units GHz ps ps ps ps ps ps ps ps ps % % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters are measured at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. ICS8S89834AKI REVISION A FEBRUARY 4, 2010 5 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 200MHz 12kHz to 20MHz = 0.12ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". ICS8S89834AKI REVISION A FEBRUARY 4, 2010 6 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx SCOPE LVPECL nQx VEE LVPECL nQx VEE -1.3V±0.33V -0.5V ± 0.125V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit Par t 1 nQx nQx Qx Qx nQy Qy Par t 2 nQy Qy t sk(o) t sk(pp) Part-to-Part Skew Output Skew V DD IN1, IN2 2 IN1, IN2 EN t SET-UP t HOLD nQ0:nQ3 Q0:Q3 tpLH tpHL Setup & Hold Time Propagation Delay ICS8S89834AKI REVISION A FEBRUARY 4, 2010 7 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Parameter Measurement Information, continued IN1 nQ0:nQ3 80% 80% VOUT IN2 Q0:Q3 20% tR tF 20% SEL nQ0:nQ3 Q0:Q3 t sw Output Rise/Fall Time Switch Over nQ0:nQ3 Q0:Q3 VIN, VOUT 800mV (typical) VDIFF_IN, VDIFF_OUT 1600mV (typical) t PW t PERIOD odc = t PW t PERIOD x 100% Differential Output Voltage Swing Output Duty Cycle/Pulse Width/Period Application Information Recommendations for Unused Input and Output Pins Inputs: IN Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the IN input to ground. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS8S89834AKI REVISION A FEBRUARY 4, 2010 8 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 2. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. PIN SOLDER EXPOSED HEAT SLUG SOLDER PIN PIN PAD GROUND PLANE THERMAL VIA LAND PATTERN (GROUND PAD) PIN PAD Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8S89834AKI REVISION A FEBRUARY 4, 2010 9 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V 3.3V Zo = 50Ω + 3.3V R3 125Ω Zo = 50Ω 3.3V R4 125Ω 3.3V + _ LVPECL Zo = 50Ω R1 50Ω RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 R2 50Ω VCC - 2V RTT Input LVPECL Zo = 50Ω R1 84Ω R2 84Ω _ Input Figure 3A. 3.3V LVPECL Output Termination Figure 3B. 3.3V LVPECL Output Termination ICS8S89834AKI REVISION A FEBRUARY 4, 2010 10 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Termination for 2.5V LVPECL Outputs Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50Ω + 50Ω – 50Ω – R3 250 50Ω + VCC = 2.5V 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example ICS8S89834AKI REVISION A FEBRUARY 4, 2010 11 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8S89834I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8S89834I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 52mA = 188.76mW Power (outputs)MAX = 32mW w/Loaded Output pair If all outputs are loaded, the total power is 4 * 32mW = 128mW Total Power_MAX = (3.63V, with all outputs switching) = 188.76mW + 128mW = 316.76mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.317W * 74.7°C/W = 108.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 74.7°C/W 1 65.3°C/W 2.5 58.5°C/W ICS8S89834AKI REVISION A FEBRUARY 4, 2010 12 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.80V (VCC_MAX – VOH_MAX) = 0.80V For logic low, VOUT = VOL_MAX = VCC_MAX – 1.60V (VCC_MAX – VOL_MAX) = 1.60V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.80V)/50Ω] * 0.80V = 19.20mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCO_MAX – VOL_MAX) = [(2V – 1.60V)/50Ω] * 1.60V = 12.80mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW ICS8S89834AKI REVISION A FEBRUARY 4, 2010 13 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Reliability Information Table 6. θJA vs. Air Flow Table for a 16 Lead VFQFN θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 74.7°C/W 1 65.3°C/W 2.5 58.5°C/W Transistor Count The transistor count for ICS8S89834I is: 351 This device is pin and function compatible and a suggested replacement for ICS889834. ICS8S89834AKI REVISION A FEBRUARY 4, 2010 14 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN Seating Plane Index Area N A1 A3 L N 1 2 E2 (NE -1)x e E2 2 (Re f.) (Ref.) (ND-1)x e (R ef.) ND & NE Even e (Typ.) 2 If ND & NE Top View Anvil Singulation or Sawn Singulation are Even b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C (Ref.) e D2 2 D2 ND & NE Odd Thermal Base Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID 4 BB 2 1 CHAMFER 2 1 N N-1 AA 4 4 2 1 RADIUS There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) Table 7. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8S89834AKI REVISION A FEBRUARY 4, 2010 CC 4 N N-1 4 DD 4 N N-1 15 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER Ordering Information Table 8. Ordering Information Part/Order Number 8S89834AKILF 8S89834AKILFT Marking 834A 834A Package “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8S89834AKI REVISION A FEBRUARY 4, 2010 16 ©2010 Integrated Device Technology, Inc. ICS8S89834I Data Sheet LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.