8S89874BKILFT

1:2 Differential-to-LVPECL Buffer/Divider ICS8S89874I DATA SHEET General Description The ICS8S89874I is a high speed 1:2 Differential-to- LVPECL Buffer/ Divider. The ICS8S89874I has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider, which allows the device to be used as either a 1:2 fanout buffer or frequency divider. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. Features • • • • • • • • • • • Two LVPECL/ECL output pairs Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8, ÷16 IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML Output frequency: 2GHz (maximum) Output skew: 15ps (maximum) Part-to-part skew: 250ps (maximum) Additive phase jitter, RMS: 0.20ps (typical) LVPECL supply voltage range: 2.375V to 3.63V ECL supply voltage range: -3.63V to -2.375V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram S2 Pullup Pin Assignment VCC Q0 1 nRESET Pullup nQ0 Enable FF Enable MUX Q0 0 nQ0 2 16 15 14 13 12 IN 11 VT 10 VREF_AC 9 nIN 5 S2 Q1 3 nQ1 4 6 nc 7 VCC 1 IN VT 50Ω 50Ω Q1 nQ1 nIN 00 01 10 11 ÷2 ÷4 ÷8 ÷16 ICS8S89874I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View S0 Pullup S1 Pullup VREF_AC Decoder ICS8S89874BKI REVISION A OCTOBER 22, 2010 1 ©2010 Integrated Device Technology, Inc. nRESET VEE S0 S1 8 ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Table 1. Pin Descriptions Number 1, 2 3, 4 5, 15, 16 6 7, 14 8 9 10 11 12 13 Name Q0, nQ0 Q1, nQ1 S2, S1, S0 nc Vcc nRESET nIN VREF_AC VT IN VEE Type Output Output Input Unused Power Input Input Output Input Input Power Pullup Pullup Description Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Select pins. LVCMOS/LVTTL interface levels. No connect. Positive supply pins. When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold is VCC/2. Includes a 37kΩ pullup resistor. LVTTL/LVCMOS interface levels. Inverting differential LVPECL clock input. RT = 50Ω termination to VT. Reference voltage for AC-coupled applications. Termination input. Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT. Negative supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units kΩ ICS8S89874BKI REVISION A OCTOBER 22, 2010 2 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Function Tables Table 3A. Control Input Function Table Inputs nRESET 0 1 Selected Source IN/nIN IN/nIN Q0, Q1 Disabled; LOW Enabled Outputs nQ0, nQ1 Disabled; HIGH Enabled VCC/2 nRESET IN nIN tRR VIN VIN Swing tPD VOUT Swing nQx Qx Figure 1. nRESET Timing Diagram Table 3B. Truth Table Inputs nRESET 1 1 1 1 1 0 0 S2 0 1 1 1 1 1 0 S1 X 0 0 1 1 X X S0 X 0 1 0 1 X X Outputs Reference Clock ÷1 (pass through) Reference Clock ÷2 Reference Clock ÷4 Reference Clock ÷8 Reference Clock ÷16 Q = LOW, nQ = HIGH; Clock Disabled Q = LOW, nQ = HIGH; Clock Disabled ICS8S89874BKI REVISION A OCTOBER 22, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT VREF_AC Input Sink/Source, IREF_AC Operating Temperature Range, TA Package Thermal Impedance, θJA, (Junction-to-Ambient) Storage Temperature, TSTG Rating -0.5V to + 4.6V -0.5V to VCC + 0.5V 50mA 100mA ±50mA ±100mA ±2mA -40°C to +85°C 74.7°C/W (0 mps) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.63 45 Units V mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VCC = VIN = 3.63V or 2.625V VCC = 3.63V or 2.625V, VIN = 0V -150 Test Conditions Minimum 2.2 0 Typical Maximum VCC + 0.3 0.8 10 Units V V µA µA ICS8S89874BKI REVISION A OCTOBER 22, 2010 4 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Table 4C. Differential DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol RIN VIH VIL VIN VDIFF_IN IIN VREF_AC Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing Differential Input Voltage Swing Input Current; NOTE 1 Bias Voltage (IN, nIN) VCC – 1.45 VCC – 1.37 (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions Minimum 40 1.2 0 0.15 0.3 35 VCC – 1.32 Typical 50 Maximum 60 VCC VIH – 0.15 1.2 Units Ω V V V V mA V NOTE 1: Guaranteed by design. Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Test Conditions Minimum VCC – 1.175 VCC – 2.0 0.6 1.2 Typical Maximum VCC – 0.82 VCC – 1.575 1.0 2.0 Units V V V V NOTE: Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. ICS8S89874BKI REVISION A OCTOBER 22, 2010 5 ©2010 Integrated Device Technology, Inc. ICS8S89874I Data Sheet 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol fOUT fIN tPD tsk(o) tsk(pp) tjit tRR tR / tF Parameter Output Frequency Input Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Part-to-Part Skew; NOTE 3, 4 Buffer Additive Jitter; RMS; refer to Additive Phase Jitter Section; NOTE 5 Reset Recovery time Output Rise/Fall Time 20% to 80% 155.52MHz, Integration Range: 12kHz – 20MHz 600 70 250 0.20 Test Conditions Output Swing ≥ 450mV ÷2, ÷4, ÷8, ÷16 Input Swing: