90E36

Poly-Phase High-Performance Wide-Span Energy Metering IC 90E36 Version 1.2 December 9, 2011 6024 Silver Creek Valley Road, San Jose, CA 95138 © 2011 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents FEATURES .............................................................................................................................................................................. 7 APPLICATION ......................................................................................................................................................................... 7 GENERAL DESCRIPTION ...................................................................................................................................................... 7 BLOCK DIAGRAM .................................................................................................................................................................. 8 1 PIN ASSIGNMENT ............................................................................................................................................................. 9 2 PIN DESCRIPTION .......................................................................................................................................................... 10 3 FUNCTION DESCRIPTION .............................................................................................................................................. 12 3.1 3.2 3.3 POWER SUPPLY .......................................................................................................................................................................................... 12 CLOCK .......................................................................................................................................................................................................... 12 RESET ........................................................................................................................................................................................................... 12 3.3.1 RESET Pin ....................................................................................................................................................................................... 12 3.3.2 Power On Reset (POR) .................................................................................................................................................................. 12 3.3.3 Software Reset ............................................................................................................................................................................... 12 METERING FUNCTION ................................................................................................................................................................................ 13 3.4.1 Theory of Energy Registers .......................................................................................................................................................... 13 3.4.2 Energy Registers ............................................................................................................................................................................ 15 3.4.3 Energy Pulse Output ...................................................................................................................................................................... 15 3.4.4 Startup and No-load Power ........................................................................................................................................................... 15 MEASUREMENT FUNCTION ....................................................................................................................................................................... 17 3.5.1 Active/ Reactive/ Apparent Power ................................................................................................................................................ 17 3.5.2 Fundamental / Harmonic Active Power ........................................................................................................................................ 17 3.5.3 Mean Power Factor (PF) ................................................................................................................................................................ 17 3.5.4 Voltage / Current RMS ................................................................................................................................................................... 17 3.5.5 Phase Angle .................................................................................................................................................................................... 18 3.5.6 Frequency ....................................................................................................................................................................................... 18 3.5.7 Temperature ................................................................................................................................................................................... 18 3.5.8 THD+N for Voltage and Current .................................................................................................................................................... 18 FOURIER ANALYSIS FUNCTION ................................................................................................................................................................ 19 POWER MODE .............................................................................................................................................................................................. 20 3.7.1 Normal Mode (N Mode) .................................................................................................................................................................. 20 3.7.2 Idle Mode (I Mode) .......................................................................................................................................................................... 21 3.7.3 Detection Mode (D Mode) .............................................................................................................................................................. 23 3.7.4 Partial Measurement mode (M Mode) ........................................................................................................................................... 24 3.7.5 Transition of Power Modes ........................................................................................................................................................... 25 EVENT DETECTION ..................................................................................................................................................................................... 26 3.8.1 Zero-Crossing Detection ............................................................................................................................................................... 26 3.8.2 Sag Detection ................................................................................................................................................................................. 26 3.8.3 Phase Loss Detection .................................................................................................................................................................... 26 3.8.4 Neutral Line Overcurrent Detection .............................................................................................................................................. 26 3.8.5 Phase Sequence Error Detection ................................................................................................................................................. 26 DC AND CURRENT RMS ESTIMATION ...................................................................................................................................................... 26 INTERFACE DESCRIPTION ......................................................................................................................................................................... 27 SLAVE MODE: SPI INTERFACE .................................................................................................................................................................. 28 4.2.1 SPI Slave Interface Format ............................................................................................................................................................ 28 4.2.2 Reliability Enhancement Feature .................................................................................................................................................. 28 MASTER MODE: DMA .................................................................................................................................................................................. 29 3 December 9, 2011 3.4 3.5 3.6 3.7 3.8 3.9 4.1 4.2 4.3 4 SPI / DMA INTERFACE .................................................................................................................................................... 27 Table of Contents 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5 CALIBRATION METHOD ................................................................................................................................................. 32 6 REGISTER ........................................................................................................................................................................ 33 6.1 6.2 REGISTER LIST ............................................................................................................................................................................................ 33 SPECIAL REGISTERS .................................................................................................................................................................................. 40 6.2.1 Soft Reset Register ........................................................................................................................................................................ 40 6.2.2 IRQ and WarnOut Signal Generation ............................................................................................................................................ 41 6.2.3 Special Configuration Registers ................................................................................................................................................... 46 6.2.4 Last SPI Data Register ................................................................................................................................................................... 48 LOW-POWER MODES REGISTERS ............................................................................................................................................................ 49 6.3.1 Detection Mode Registers ............................................................................................................................................................. 49 6.3.2 Partial Measurement mode Registers .......................................................................................................................................... 51 CONFIGURATION AND CALIBRATION REGISTERS ................................................................................................................................ 54 6.4.1 Start Registers and Associated Checksum Operation Scheme ................................................................................................ 54 6.4.2 Configuration Registers ................................................................................................................................................................ 54 6.4.3 Energy Calibration Registers ........................................................................................................................................................ 58 6.4.4 Fundamental/Harmonic Energy Calibration registers ................................................................................................................ 60 6.4.5 Measurement Calibration .............................................................................................................................................................. 60 ENERGY REGISTER .................................................................................................................................................................................... 61 6.5.1 Regular Energy Registers ............................................................................................................................................................. 61 6.5.2 Fundamental / Harmonic Energy Register ................................................................................................................................... 63 MEASUREMENT REGISTERS ..................................................................................................................................................................... 63 6.6.1 Power and Power Factor Registers .............................................................................................................................................. 63 6.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers ...................................................................................... 64 6.6.3 THD+N, Frequency, Angle and Temperature Registers ............................................................................................................. 65 HARMONIC FOURIER ANALYSIS REGISTERS ......................................................................................................................................... 66 ELECTRICAL SPECIFICATION ................................................................................................................................................................... 68 METERING/ MEASUREMENT ACCURACY ................................................................................................................................................ 70 7.2.1 Metering Accuracy ......................................................................................................................................................................... 70 7.2.2 Measurement Accuracy ................................................................................................................................................................. 71 INTERFACE TIMING ..................................................................................................................................................................................... 72 7.3.1 SPI Interface Timing (Slave Mode) ................................................................................................................................................ 72 7.3.2 DMA Timing (Master Mode) ........................................................................................................................................................... 73 POWER ON RESET TIMING ........................................................................................................................................................................ 74 ZERO-CROSSING TIMING ........................................................................................................................................................................... 75 VOLTAGE SAG AND PHASE LOSS TIMING .............................................................................................................................................. 76 ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 77 5.1 5.2 NORMAL MODE OPERATION CALIBRATION ........................................................................................................................................... 32 PARTIAL MEASUREMENT MODE CALIBRATION ..................................................................................................................................... 32 4.3.1 4.3.2 DMA Burst Transfer for ADC Sampling ........................................................................................................................................ 29 Control Sequence for External Device ......................................................................................................................................... 31 6.3 6.4 6.5 6.6 6.7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7 ELECTRICAL SPECIFICATION ....................................................................................................................................... 68 PACKAGE DIMENSIONS...................................................................................................................................................... 78 ORDERING INFORMATION.................................................................................................................................................. 79 DATASHEET DOCUMENT HISTORY................................................................................................................................... 79 4 December 9, 2011 List of Tables Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Table-16 Table-17 Table-18 Table-19 Table-20 Pin Description ............................................................................................................................................................................................. Power Mode Mapping .................................................................................................................................................................................. Digital I/O and Power Pin States in Idle Mode ............................................................................................................................................. Register List ................................................................................................................................................................................................. Configuration Registers ............................................................................................................................................................................... Calibration Registers .................................................................................................................................................................................... Fundamental/Harmonic Energy Calibration Registers ................................................................................................................................. Measurement Calibration Registers ............................................................................................................................................................. Regular Energy Registers ............................................................................................................................................................................ Fundamental / Harmonic Energy Register ................................................................................................................................................... Power and Power Factor Register ............................................................................................................................................................... Fundamental/ Harmonic Power and Voltage/ Current RMS Registers ........................................................................................................ THD+N, Frequency, Angle and Temperature Registers .............................................................................................................................. Harmonic Fourier Analysis Results Registers .............................................................................................................................................. Metering Accuracy for Different Energy within the Dynamic Range ............................................................................................................ Measurement Parameter Range and Format .............................................................................................................................................. SPI Timing Specification .............................................................................................................................................................................. DMA Timing Specification ............................................................................................................................................................................ Power On Reset Specification ..................................................................................................................................................................... Zero-Crossing Specification ......................................................................................................................................................................... 10 20 21 33 54 58 60 60 61 63 63 64 65 66 70 71 72 73 74 75 List of Tables 5 December 9, 2011 List of Figures Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 Figure-16 Figure-17 Figure-18 Figure-19 Figure-20 Figure-21 Figure-22 Figure-23 Figure-24 Figure-25 Figure-26 Figure-27 Figure-28 90E36 Block Diagram .................................................................................................................................................................................... 8 Pin Assignment (Top View) ............................................................................................................................................................................ 9 Energy Register Operation Diagram ............................................................................................................................................................ 14 CFx Pulse Output Regulation ...................................................................................................................................................................... 15 Metering Startup Handling ........................................................................................................................................................................... 16 Analysis Function ......................................................................................................................................................................................... 19 Block Diagram in Normal Mode ................................................................................................................................................................... 20 Block Diagram in Idle Mode ......................................................................................................................................................................... 21 Block Diagram in Detection Mode ................................................................................................................................................................ 23 Block Diagram in Partial Measurement mode ............................................................................................................................................. 24 Power Mode Transition ............................................................................................................................................................................... 25 Slave Mode ................................................................................................................................................................................................. 27 Master Mode (PIN_DIR_SEL=0) ................................................................................................................................................................. 27 Read Sequence ........................................................................................................................................................................................... 28 Write Sequence ........................................................................................................................................................................................... 28 Clock Mode0 (CLK_DRV=0, CLK_IDLE=0) and Mode1 (CLK_DRV=0, CLK_IDLE=1) .............................................................................. 29 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1) .............................................................................. 30 Sample Sequence Example ........................................................................................................................................................................ 30 Sample Bit Sequence Example ................................................................................................................................................................... 31 IRQ and WarnOut Generation ..................................................................................................................................................................... 41 Current Detection Register Latching Scheme ............................................................................................................................................. 49 Start and Checksum Register Operation Scheme ...................................................................................................................................... 54 SPI Timing Diagram .................................................................................................................................................................................... 72 DMA Timing Diagram .................................................................................................................................................................................. 73 Power On Reset Timing (90E36 and MCU are Powered on Simultaneously) ............................................................................................ 74 Power On Reset Timing in Normal & Partial Measurement Mode .............................................................................................................. 74 Zero-Crossing Timing Diagram (per phase) ................................................................................................................................................ 75 Voltage Sag and Phase Loss Timing Diagram ............................................................................................................................................ 76 List of Figures 6 December 9, 2011 Poly-Phase High-Performance Wide-Span Energy Metering IC FEATURES Metering Features • Metering features fully in compliance with the requirements of IEC62052-11, IEC62053-22 and IEC62053-23, ANSI C12.1 and ANSI C12.20; applicable in class 0.5S or class 1 poly-phase watt-hour meter or class 2 poly-phase var-hour meter. • Accuracy of ±0.1% for active energy and ±0.2% for reactive energy over the dynamic range of 6000:1. • Temperature coefficient is 6 ppm/ ℃ (typical) for on-chip reference voltage. • Single-point calibration on each phase over the whole dynamic range for active energy; no calibration needed for reactive/ apparent energy. • ±1 ℃ (typical) temperature sensor accuracy. • Electrical parameters measurement: less than ±0.5% fiducial error for Vrms, Irms, mean active/ reactive/ apparent power, frequency, power factor and phase angle. • Active (forward/reverse), reactive (forward/reverse), apparent energy with independent energy registers. Active/ reactive/ apparent energy can be output by pulse or read through energy registers to adapt to different applications. • Programmable startup and no-load power threshold, special designed of startup and no-load circuits to eliminate crosstalk among phases achieving better accuracy especially at low power conditions. • Dedicated ADC and different gains for phase A/B/C and Neutral line current sampling circuits. Current sampled over current transformer (CT) or Rogowski coil (di/dt coil); phase A/B/C voltage sampled over resistor divider network or potential transformer (PT). • Programmable power modes: Normal mode (N mode), Idle mode (I mode), Detection mode (D mode) and Partial Measurement mode (M mode). 90E36 Preliminary Information* • Fundamental (CF3, 0.2%) and harmonic (CF4, 1%) active energy with dedicated energy and power registers. • Total Harmonic Distortion (THD) and Discrete Fourier Transform (DFT) functions for 2 ~ 32 order harmonic component. THD and DFT results available in SPI accessible registers. Both voltage and current of all phases processed within the same time period. • Event detection: sag, phase loss, reverse voltage/ current phase sequence, reverse flow, calculated neutral line current INC overcurrent sampled neutral line current INS overcurrent and THD+N over-threshold. Other Features • 3.3V single power supply. Operating voltage range: 2.8V~3.6V. Metering accuracy guaranteed within 3.0V~3.6V. • Four-wire SPI interface with Direct Memory Access (DMA) mode to stream out 7-channel ADC raw data. • Parameter diagnosis function and programmable interrupt output of the IRQ interrupt signals and the WarnOut signal. • Programmable voltage sag detection and zero-crossing output. • CF1/CF2/CF3/CF4 output active/ reactive/ apparent energy pulses and fundamental/ harmonic energy pulses respectively. • Crystal oscillator frequency: 16.384 MHz. On-chip two capacitors and no need of external capacitors. • TQFP48 package. • Operating temperature: -40 ℃ ~ +85 ℃ . APPLICATION • Poly-phase energy meters of class 0.5S and class 1 which are used in three-phase four-wire (3P4W, Y0) or three-phase threewire (3P3W, Y or ∆) systems. • Data Acquisition Terminal. • Power monitoring instruments which need to measure voltage, current, THD, DFT, mean power, etc. GENERAL DESCRIPTION The 90E36 is a poly-phase high performance wide-dynamic range metering IC. The 90E36 incorporates 7 independent 2nd order sigmadelta ADCs, which could be employed in three voltage channels (phase A, B and C) and four current channels (phase A, B, C and neutral line) in a typical three-phase four-wire system. The 90E36 has an embedded DSP which executes calculation of active energy, reactive energy, apparent energy, fundamental and harmonic active energy over ADC signal and on-chip reference voltage. The DSP also calculates measurement parameters such as voltage and current RMS value as well as mean active/reactive/apparent power. A four-wire SPI interface is provided between the 90E36 and the external microcontroller. In addition, DMA mode can be used for 7-channel ADC raw data access, offering more flexibility in system application. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The 90E36 is suitable for poly-phase multi-function meters which could measure active/reactive/apparent energy and fundamental/harmonic energy either through four independent energy pulse outputs CF1/CF2/CF3/CF4 or through the corresponding registers. With the on-chip THD and DFT engine, all phases' THD and DFT results can be directly accessed through related registers, thus simplifying hardware design in Data Acquisition Terminals. IDT's proprietary ADC and auto-temperature compensation technology for reference voltage ensure the 90E36's long-term stability over variations in grid and ambient environment conditions. 7  2011 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC BLOCK DIAGRAM OSCI OSCO RESET PM1 PM0 Power On Reset Power Mode Configuration Current Detector VDD18 Regulator Crystal Oscillator I1P / I1N I2P / I2N I3P / I3N I4P / I4N V1P / V1N V2P / V2N V3P / V3N ADC-I1 ADC-I2 ADC-I3 ADC-IN ADC-V1 ADC-V2 ADC-V3 Temperature Sensor Energy Metering (Forward/Reverse Active/Reactive/CF Generator) CF Out CF1 CF2 CF3 CF4 ZX0 ZX1 ZX2 WarnOut IRQ0 IRQ1 CS DSP Measure and Monitoring (V/I/rms / SAG / Phase / Frequency) Signal Analyzer ADC Sample Capture / THD Zero Crossing Warn Out IRQ SPI Interface Control Logic DMA SCLK SDO SDI DMA_CTRL Vref Reference Voltage Figure-1 90E36 Block Diagram Block Diagram 8 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 1 PIN ASSIGNMENT RESET VDD18 VDD18 DGND DGND DVDD SCLK 38 SDO SDI NC NC 48 47 46 45 44 43 42 41 40 39 AVDD AGND I1P I1N I2P I2N I3P I3N I4P I4N Vref AGND 1 2 3 4 5 6 7 8 9 37 CS 36 35 34 33 32 31 30 29 28 27 26 25 14 15 16 17 18 19 20 21 22 23 24 DM A_CTRL NC PM 1 PM 0 TEST IRQ1 IRQ0 WarnOut CF4 CF3 CF2 CF1 10 11 12 13 OSCI ZX1 DGND V1N V2N V3N Figure-2 Pin Assignment (Top View) Pin Assignment 9 OSCO V1P V2P V3P ZX0 ZX2 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 2 PIN DESCRIPTION Name Reset Pin No. 41 I/O I Type LVTTL Description Reset: Reset Pin (active low) This pin should connect to ground through a 0.1 µF filter capacitor and a 10kΩ resistor to VDD. In application it can also directly connect to one output pin from microcontroller (MCU). AVDD: Analog Power Supply This pin provides power supply to the analog part. This pin should connect to DVDD and be decoupled with a 0.1µF capacitor. DVDD: Digital Power Supply This pin provides power supply to the digital part. It should be decoupled with a 10µF capacitor and a 0.1µF capacitor. VDD18: Digital Power Supply (1.8 V) These two pins should be connected together and connected to ground through a 10µF capacitor. DGND: Digital Ground AGND: Analog Ground I1P: Positive Input for Phase A Current I1N: Negative Input for Phase A Current These pins are differential inputs for phase A current. Note: I1 to phase A and I3 to phase C mapping can be swapped by configuring the I1I3Swap bit (b13, MMode0). I2P: Positive Input for Phase B Current I2N: Negative Input for Phase B Current These pins are differential inputs for phase B current. I3P: Positive Input for Phase C Current I3N: Negative Input for Phase C Current These pins are differential inputs for phase C current. Note: I1 to phase A and I3 to phase C mapping can be swapped by configuring the I1I3Swap bit (b13, MMode0). I4P: Positive Input for N Line Current I4N: Negative Input for N Line Current These pins are differential inputs for N line current. Vref: Output Pin for Reference Voltage This pin should be decoupled with a 10µF capacitor, possibly a 0.1µF ceramic capacitor and a 1nF ceramic capacitor. V1P: Positive Input for Phase A Voltage V1N: Negative Input for Phase A Voltage These pins are differential inputs for phase A voltage. V2P: Positive Input for Phase B Voltage V2N: Negative Input for Phase B Voltage These pins are differential inputs for phase B voltage. V3P: Positive Input for Phase C Voltage V3N: Negative Input for Phase C Voltage These pins are differential inputs for phase C voltage. OSCI: External Crystal Input OSCO: External Crystal Output A 16.384 MHz crystal is connected between OSCI and OSCO. There are two on-chip capacitor, therefore no need of external capacitors. ZX2/ZX1/ZX0:Zero-Crossing Output These pins are asserted when voltage or current crosses zero. Zero-crossing mode can be configured by the ZXConfig register (07H). CF1: (all-phase-sum total) Active Energy Pulse Output Table-1 Pin Description AVDD 1 I Power DVDD 48 I Power VDD18 DGND AGND I1P I1N 42, 43 19, 44, 47 2, 12 3 4 P I I Power Power Power I Analog I2P I2N 5 6 I Analog I3P I3N 7 8 I Analog I4P I4N Vref V1P V1N V2P V2N V3P V3N OSCI OSCO ZX0 ZX1 ZX2 CF1 9 10 11 13 14 15 16 17 18 20 21 22 23 24 25 I Analog O Analog I Analog I Analog I I O Analog OSC OSC O O LVTTL LVTTL Pin Description 10 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-1 Pin Description (Continued) Name CF2 CF3 CF4 WarnOut Pin No. 26 27 28 29 I/O O O O O Type LVTTL LVTTL LVTTL LVTTL Description CF2: (all-phase-sum total) Reactive/ Apparent Energy Pulse Output The output of this pin is determined by the CF2varh bit (b7, MMode0) and the CF2ESV bit (b8, MMode0). CF3: (all-phase-sum total) Active Fundamental Energy Pulse Output CF4: (all-phase-sum total) Active Harmonic Energy Pulse Output WarnOut: Fatal Error Warning This pin is asserted high when there is metering related parameter checksum error. Otherwise this pin stays low. Refer to 6.2.2 IRQ and WarnOut Signal Generation. IRQ0: Interrupt Output 0 This pin is asserted when one or more events in the SysStatus0 register (01H) occur. It is deasserted when there is no bit set in the SysStatus0 register (01H). In Detection mode, the IRQ0 is used to indicate the output of current detector. The IRQ0 state is cleared when entering or exiting Detection mode. IRQ1: Interrupt Output 1 This pin is asserted when one or more events in the SysStatus1 register (02H) occur. It is deasserted when there is no bit set in the SysStatus1 register (02H). In Detection mode, the IRQ1 is used to indicate the output of current detector. The IRQ1 state is cleared when entering or exiting Detection mode. PM1/0: Power Mode Configuration These two pins define the power mode of 90E36. Refer to Table-2. DMA_CTRL: DMA Enable DMA is started when this pin is asserted. DMA is stopped when this pin is deasserted. Refer to 4 SPI / DMA Interface. CS: Chip Select (Active Low) In SPI mode, this pin must be driven from high to low for each read/ write operation, and maintain low for the entire operation. In DMA mode, this pin is asserted during data transmission. Refer to 4 SPI / DMA Interface. SCLK: Serial Clock This pin is used as the clock for the SPI/DMA interface. Refer to 4 SPI / DMA Interface. SDO: Serial Data Output This pin is used as the data output for the SPI mode and input for the DMA mode. Refer to 4 SPI / DMA Interface. SDI: Serial Data Input This pin is used as the data input for the SPI mode and output for the DMA mode. Refer to 4 SPI / DMA Interface. This pin should be always connected to DGND in system application. NC: These pins should be left open. IRQ0 30 O LVTTL IRQ1 31 O LVTTL PM0 PM1 DMA_CTRL 33 34 36 I I LVTTL LVTTL CS 37 B LVTTL SCLK SDO 38 39 B B LVTTL LVTTL SDI TEST NC 40 32 35, 45, 46 B I LVTTL LVTTL Pin Description 11 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3 3.1 FUNCTION DESCRIPTION POWER SUPPLY - RESET pin On-chip Power On Reset circuit Software Reset generated by the Software Reset register RESET PIN The 90E36 works with single power rail 3.3V. An on-chip voltage regulator regulates the 1.8V voltage for the digital logic. The regulated 1.8V power is connected to the VDD18 pin. It needs to be bypassed by an external capacitor. The 90E36 has multiple power modes, in Idle and Detection modes the 1.8V power regulator is not turned on and the digital logic is not powered. When the logic is not powered, all the configured register values are not kept (all context lost) except for Detection mode related registers (10H~13H) for Detection mode configuration. User has to re-configure the registers in Partial Measurement mode or Normal mode when transiting from Idle or Detection mode. Refer to 3.7 Power Mode for power mode details. 3.3.1 The RESET pin can be asserted to reset the 90E36. The RESET pin has RC filter with typical time constant of 2µs in the I/O, as well as a 2µs (typical) de-glitch filter. Any reset pulse that is shorter than 2µs can not reset the 90E36. 3.3.2 POWER ON RESET (POR) The POR circuit resets the 90E36 at power up. POR circuit triggers reset when: - DVDD power up, crossing the power-up threshold. Refer to Figure-26. - VDD18 regulator changing from disable to enable, i.e. from Idle or Detection mode to Partial Measurement mode or Normal mode. Refer to Figure-25. 3.3.3 SOFTWARE RESET Chip reset can be triggered by writing to the SoftReset register in Normal mode. The software reset is the same as the reset scope generated from the RESET pin or POR. These three reset sources have the same reset scope. All digital logics and registers, except for the Harmonic Ratio registers will be subject to reset. The Harmonic Ratio registers can not be reset. • Interface logic: clock dividers • Digital core/ logic: All registers except for the Harmonic Ratio registers and some other special registers, refer to 6.3.1 Detection Mode Registers. 3.2 CLOCK The 90E36 has an on-chip oscillator and can directly connect to an external crystal. The OSCI pin can also be driven with a clock source. The oscillator will be powered down in Idle and Detection power modes, as described in 3.7 Power Mode. 3.3 RESET There are three reset sources for the 90E36: Function Description 12 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.4 METERING FUNCTION The accumulated energy is converted to pulse frequency on the CF pins and stored in the corresponding energy registers. The 90E36 provides energy accumulation registers with 0.1 or 0.01 CF resolution. 0.01CF / 0.1CF setting is defined by the 001LSB bit (b9, MMode0). 3.4.1 THEORY OF ENERGY REGISTERS The energy accumulation runs at 1 MHz clock rate, by accumulating the power value calculated by the DSP processor. The power accumulation process is equivalent to digitally integrating the instantaneous power with a delta-time of about 1us. The accumulated energy is used to calculate the CF pulses and the corresponding internal energy registers. The accumulated energy is converted to frequency of the CF pulses. One CF usually corresponds to 1KWh / MC (MC is Meter Constant, e.g. 3200 imp/kWh), and is usually referenced as an energy unit in this data- sheet. The internal energy resolution for accumulation and conversion is 0.01 CF. The 0.01 CF pulse energy constant is referenced as 'PL_constant'. Within 0.01 CF, forward and reverse energy are counteracted. When energy exceeds 0.01 pulse, the respective forward/ reverse energy is increased. Take the example of active energy, suppose: T0: Forward energy register is 12.34 pulses and reverse energy register is 1.23 pulses. From t0 to t1: 0.005 forward pulses appeared. From t1 to t2: 0.004 reverse pulses appeared. From t2 to t3: 0.005 reverse pulses appeared. From t3 to t4: 0.007 reverse pulses appeared. The following table illustrates the process of energy accumulation process: t2 -0.005 -0.004 0 0 12.34 1.23 t3 -0.007 -0.001 0 1 12.34 1.23 12.34 1.24 t4   Input energy Bidirectional energy accumulator Forward 0.01 CF Reverse 0.01CF Forward energy register Reverse energy register t0 + 0.005 0.005 0 0 12.34 1.23 t1 -0.004 0.001 0 0 12.34 1.23 When forward/reverse energy reaches 0.1/0.01 pulse, the respective register is updated. When forward or reverse energy reaches 1 pulse, CFx pins output pulse and the REVP/REVQ bits (b7~0, SysStatus1) are updated. Refer to Figure-3. Function Description 13 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC A/B/C Power Phase-A Phase-B Phase-C Bi-directional Energy accumulator, roll over Bi-directional Energy positive/nega accumulator, roll over tive @ positive/negative @ 0.01CF 0.01CF (+)0.01 Forward CF energy (+)0.01 Forward accumulator CF energy (+)0.01 Forward energy (-)0.01 accumulator CF Backward register CF energy (-)0.01 accumulator Backward accumulator CF energy (-)0.01 Reverse energy accumulator CF register accumulator ENA ENB ENC Energy accumulator @ Energy 1Mhz accumulator @ 1Mhz Energy accumulator @ 1Mhz Rev[P/Q]chg[A/BC} ABS or Arithmetic + All-phase sum Bi-directional Energy accumulator, roll over positive/negative @ 0.01CF (+)0.01 CF (-)0.01 CF Positive CF Accumulator Rev[P/Q]chgT Forward energy register accumulator reverse energy register accumulator Negative 0-CF Accumulator CF Gen Logic CF pulse Energy accumulator @ 1Mhz CF[P/Q]RevFlag Figure-3 Energy Register Operation Diagram For all-phase-sum total of active, reactive and (arithmetic sum) apparent energy, the associated power is obtained by summing the power of the three phases. The accumulation method of all-phase-sum energy is determined by the EnPC/EnPB/EnPA/ABSEnP/ABSEnQ bits (b0~b4, MMode0). Note that the direction of all-phase-sum power and single-phase power might be different. Function Description 14 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.4.2 ENERGY REGISTERS The 90E36 meters non-decomposed total active, reactive and apparent energy, as well as decomposed active fundamental and harmonic energy. The registers are listed as below. 3.4.2.1 Total Energy Registers Each phase and all-phase-sum has the following registers: - Active forward/ reverse - Reactive forward/ reverse - Apparent energy In addition, there is an apparent energy all-phase vector sum register. Altogether there are 21 energy registers. Those registers are defined in 6.5.1 Regular Energy Registers. 3.4.2.2 Fundamental and Harmonic Energy Registers The 90E36 counts decomposed active fundamental and harmonic energy. Reactive energy is not decomposed to fundamental and harmonic. The fundamental/harmonic energy is accumulated in the same way as active energy accumulation method described above. Registers: - Fundamental / harmonic - all-phase-sum / phase A / phase B / phase C - Forward / reverse Altogether there are 16 energy registers. Refer to 3.4.2.2 Fundamental and Harmonic Energy Registers. 3.4.3 ENERGY PULSE OUTPUT CF1 is fixed to be total active energy output (all-phase-sum). Both forward and reverse energy registers can generate the CF pulse (change of forward/ reverse direction can generate an interrupt if enabled). CF2 is reactive energy output (all-phase-sum) by default. It can also be configured to be arithmetic sum apparent energy output (all-phasesum) or vector sum apparent energy output (all-phase-sum). CF3 is fixed to be active fundamental energy output (all-phase-sum). CF4 is fixed to be active harmonic energy output (all-phase-sum). Tp=80ms Tp=0.5T CFx T≥160ms For more details pls refer to AN-645. Tp=5ms 10ms≤T QPhaseTh? A/B/C Phase ReActive Power from DSP 0 1 Total ReActive Power 0 ABS > QStartTh? 0 1 Total ReActive Energy Metering 3 phases + 1 0 0 Power Threshold |P|+|Q|> SPhaseTh? 3 phases 0 0 ABS > SStartTh? Phase ReActive Energy Metering Total Apparent Power 0 1 Total (arithmetic sum) Apparent Energy Metering + A/B/C Phase Apparent Power from DSP 0 1 1 0 0 0 Phase Apparent Energy Metering Figure-5 Metering Startup Handling Function Description 16 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.5 MEASUREMENT FUNCTION - Measured parameters can be divided to 7 types as follows: - Active/ Reactive/ Apparent Power - Fundamental/ Harmonic Power - RMS for Voltage and Current - Power Factor - Phase Angle - Frequency - Temperature Measured parameters are average values that are averaged among 16 phase-voltage cycles (about 320ms at 50Hz) except for the temperature. The measured parameter update frequency is approximately 3Hz. Refer to Table-16. 3.5.1 ACTIVE/ REACTIVE/ APPARENT POWER Active/ Reactive/ Apparent Power measurement registers can be divided as below: - active, reactive, apparent power - all-phase-sum / phase A / phase B / phase C - apparent power all-phase vector sum Altogether there are 13 power registers. Refer to 6.6.1 Power and Power Factor Registers and the SVmeanT register (98H). Per-phase apparent power is defined as the product of measured Vrms and Irms of that phase. All-phase-sum power is measured by arithmetically summing the per-phase measured power. The summing of phases can be configured by the MMode0 register. The ‘apparent power all-phase vector sum’ is done according to IEEE std 1459. 3.5.2 FUNDAMENTAL / HARMONIC ACTIVE POWER Fundamental / harmonic active power measurement registers can be divided as below: fundamental and harmonic power all-phase-sum / phase A / phase B / phase C Altogether there are 8 power registers. Refer to 6.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers. 3.5.3 MEAN POWER FACTOR (PF) Power Factor is defined for those cases: all-phase-sum / phase A / phase B / phase C. Altogether there are 4 power factor registers. Refer to 6.6.1 Power and Power Factor Registers. For all-phase: PF_all = All_phase_ sum active_pow er All_phase_ sum apparent_p ower The all-phase-sum apparent power selection is defined by the CF2E SV bit (b6, MMode0). For each of the phase:: PF_phase = active_pow er apparent_p ower 3.5.4 VOLTAGE / CURRENT RMS Voltage/current RMS registers can be divided as follows: Per-phase: Phase A / Phase B / Phase C Voltage / Current Altogether there are 6 RMS registers. Neutral Line Current RMS: Neutral line current can be measured by A/D, or calculated by instantaneous value iN = i A + iB + iC . Altogether there are 2 N line current RMS registers. Refer to 6.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers. Function Description 17 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.5.5 PHASE ANGLE Phase Angle measurement registers can be divided as below: - phase A / phase B / phase C - voltage / current Altogether there are 6 phase angle registers. Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers. Note: Calculation of phase angle is based on zero-crossing interval and frequency. There might be big error when voltage/current at low value. 3.5.6 FREQUENCY Frequency is measured using phase A voltage by default. When phase A has voltage sag, phase C is used, and phase B is used when both phase A and C have voltage sag. Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers. 3.5.7 TEMPERATURE Chip Junction-Temperature is measured roughly every 100 ms by onchip temperature sensor. Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers. 3.5.8 THD+N FOR VOLTAGE AND CURRENT Voltage THD+N is defined as: (V rms_total 2 - V rms_fundam ental 2 ) V rms_fundam ental Current THD+N's definition is similar to that of voltage. Registers: - voltage and current - phase A / phase B / phase C Altogether there are 6 THD+N registers. Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers. The THD+N measurement is mainly used to monitor the percentage of harmonics in the system. Accuracy is not guaranteed when THD+N is lower than 10%. Function Description 18 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.6 FOURIER ANALYSIS FUNCTION nd nd The 90E36 offers a hardware DFT Engine for 2 to 32 order harmonic component, both V and I of each phase with the same time period. The registers can be divided as follows: - voltage and current for each phase - phase A / phase B / phase C - 32 frequency components (fundamental value, and harmonic ratios) - Total Harmonic Distortion (THD) The harmonic analysis is implemented with a DFT engine. The DFT period is 0.5 second, which gives a resolution frequency bin of 2Hz. The input samples are multiplied with a Hanning window before feeding to the DFT processor. The DFT processor computes the fundamental and harmonic components based on the measured line frequency and sampling rate, which is 8KHz. Line Frequency Sample Frequency Harmonic Analyzer Hanning Window Input sample from DSP processor Scaler X X DFT Computation Engine Frequency Components for Fundamental and Harmonic PostProcessing Ratios for Fundamental and Harmonic Sample Capture To DMA Module Figure-6 Analysis Function Function Description 19 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.7 POWER MODE 3.7.1 NORMAL MODE (N MODE) The 90E36 has four power modes. The power mode is solely defined by the PM1 and PM0 pins. Table-2 Power Mode Mapping PM1:PM0 Value 11 10 01 00 Power Mode Normal (N mode) Partial Measurement (M mode) Detection (D mode) Idle (I mode) In Normal mode, all function blocks are active except for current detector block. Refer to Figure-7. OSCI OSCO Power On Reset Power Mode Configuration Current Detector ADC-I1 ADC-I2 ADC-I3 ADC-IN ADC-V1 ADC-V2 ADC-V3 Temperature Sensor Reference Voltage VDD18 Regulator Crystal Oscillator Energy Metering (Forward/Reverse Active/Reactive/CF Generator) CF Out DSP Measure and Monitoring (V/I/rms, SAG, Phase, Freq) Zero Crossing Warn Out IRQ Signal Analyzer ADC sample capture, THD SPI Interface Control Logic DMA Disabled Figure-7 Block Diagram in Normal Mode Function Description 20 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.7.2 IDLE MODE (I MODE) The digital I/Os' supply is powered. In I/O and analog interface, the input signals from digital core (which is not powered) will be set to known state as described in Table-3. The PM1 and PM0 pins which are controlled by external MCU are active and can configure the 90E36 to other modes. In Idle mode, all functions are shut off. The analog blocks' power supply is powered but circuits are set into power-down mode, i.e, power supply applied but all current paths are shut off. There is very low current since only very low device leakage could exist in this mode. OSCI OSCO Power On Reset Power Mode Configuration Current Detector ADC-I1 ADC-I2 ADC-I3 ADC-IN ADC-V1 ADC-V2 ADC-V3 Temperature Sensor Reference Voltage Disabled VDD18 Regulator Crystal Oscillator Energy Metering (Forward/Reverse Active/Reactive/CF Generator) CF Out DSP Measure and Monitoring (V/I/rms,SAG, Phase, Freq) Zero Crossing Warn Out Signal Analyzer ADC Sample Capture, THD IRQ SPI Interface Control Logic DMA Figure-8 Block Diagram in Idle Mode Please note that since the digital I/O is not shut off, the I/O circuit is active in the Idle mode. The application shall make sure that valid logic levels are applied to the I/O. Table-3 Digital I/O and Power Pin States in Idle Mode Name Reset CS SCLK SDO SDI PM1 PM0 OSCI OSCO I/O type I B B B B I I O Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL OSC Input level shall be VDD33. I/O set in input mode. Input level shall be VDD33 or VSS. I/O set in input mode. Input level shall be VDD33 or VSS. I/O set in input mode. Input level shall be VDD33 or VSS. I/O set in input mode. Input level shall be VDD33 or VSS. As defined in Table-2 Oscillator powered down. OSCO stays at fixed (low) level. Pin State in Idle Mode Table-3 lists digital I/O and power pins’ states in Idle mode. It lists the requirements for inputs and the output level for output. For bi-directional pins, the direction is defined. Function Description 21 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-3 Digital I/O and Power Pin States in Idle Mode Name ZX0 ZX1 ZX2 CF1 CF2 CF3 CF4 WarnOut IRQ0 IRQ1 DMA_CTRL VDD18 DVDD AVDD Test I/O type O Type LVTTL 0 Pin State in Idle Mode O O O I I I I I LVTTL LVTTL LVTTL LVTTL Power Power Power Input 0 0 0 I/O set in input mode. Input level shall be VDD33 or VSS. Regulated 1.8V: high impedance Digital Power Supply: powered by system Analog Power Supply: powered by system Always tie to ground in system application Function Description 22 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.7.3 DETECTION MODE (D MODE) In Detection mode, the current detector is active. The current detector compares whether any phase current exceeds the configured threshold using low-power comparators. When the current of one phase or multiple phases exceeds the configured threshold, the 90E36 asserts the IRQ0 pin to high and hold it until power mode change. The IRQ0 state is cleared when entering or exiting Detection mode. When the current of all three current channels exceed the configured threshold, the 90E36 asserts the IRQ1 pin to high and hold it until power mode change. The IRQ1 state is cleared when entering or exiting Detection mode. The threshold registers need to be programmed in Normal mode before entering Detection mode. The digital I/O state is the same as that in Idle state (except for IRQ0/ IRQ1 and PM1/PM0). The 90E36 has two comparators for detecting each phase’s positive and negative current. Each comparator’s threshold can be set individually. The two comparators are both active by default, which called ‘double-side detection’. User also can enable one comparator only to save power consumption, which called ‘single-side detection’. Double-side detection has faster response and can detect ‘half-wave’ current. But it consumes nearly twice as much power as single-side detection. Comparators can be power-down by configuring the DetectCtrl register. OSCI OSCO Power On Reset Power Mode Configuration Current Detector ADC-I1 ADC-I2 ADC-I3 ADC-IN ADC-V1 ADC-V2 ADC-V3 Temperature Sensor Reference Voltage VDD18 Regulator Crystal Oscillator Energy Metering (Forward/Reverse Active/Reactive/CF generator) CF Out DSP Measure and Monitoring (V/I/rms, SAG, Phase, Freq) Zero Crossing Warn Out IRQ Signal Analyzer ADC Sample Capture, THD SPI Interface Control Logic DMA Disabled Figure-9 Block Diagram in Detection Mode Function Description 23 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.7.4 PARTIAL MEASUREMENT MODE (M MODE) In this mode, Voltage ADCs, Neutral Line ADC and digital circuits are inactive. The 90E36 measures the current RMS of one line cycle. When the measurement is done, the 90E36 asserts the IRQ0 pin high until the Partial Measurement mode exits. In this mode, the user needs to program the related registers (including PGA gain, channel gain, offset, etc.) to make the current RMS measurement accurate. Refer to 5.2 Partial Measurement mode Calibration. Please note that not all registers in this mode is accessible. Only the Partial Measurement related registers (14H~1DH) and some special registers (00H, 01H, 03H, 07H,0EH, 0FH) can be accessed. OSCI OSCO Power On Reset Power Mode Configuration Current Detector ADC-I1 ADC-I2 ADC-I3 ADC-IN ADC-V1 ADC-V2 ADC-V3 Temperature Sensor Reference Voltage VDD18 Regulator Crystal Oscillator Energy Metering (Forward/Reverse Active/Reactive/CF generator) Measure and Monitoring (V/I/rms, SAG, Phase, Freq) CF Out DSP Zero Crossing Warn Out Signal analyzer ADC sample capture, THD IRQ SPI Interface Control Logic DMA Disabled Figure-10 Block Diagram in Partial Measurement mode Function Description 24 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.7.5 TRANSITION OF POWER MODES Normal Mode The above power modes are controlled by the PM0 and PM1 pins. In application, the PM0 and PM1 pins are connected to external MCU. The PM0 and PM1 pins have internal RC- filters. Generally, the 90E36 stays in Idle mode most of the time while outage. It enters Detection mode at a certain interval (for example 5s) as controlled by the MCU. It informs the MCU if the current exceeds the configured threshold. The MCU then commands the 90E36 to enter Partial Measurement mode at a certain interval (e.g. 60s) to read related current. After current reading, the 90E36 gets back to the Idle mode. The measured current may be used to count energy according to some metering model (like current RMS multiplying the rated voltage to compute the power). Any power mode transition goes through the Idle mode, as shown in Figure-11. Detection Mode Idle Mode Partial Measurement Mode Figure-11 Power Mode Transition Function Description 25 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.8 3.8.1 EVENT DETECTION ZERO-CROSSING DETECTION 3.8.4.2 Computed N-Line Zero-crossing detector detects the zero-crossing point of the fundamental component of voltage and current for each of the 3 phases. Zero-crossing signal can be independently configured and output. Refer to the definition of the ZXConfig register. 3.8.2 SAG DETECTION Usually in the application the Sag threshold is set to be 78% of the reference voltage. The 90E36 generates Sag event when there are less than three 8KHz samples (absolute value) greater than the sag threshold during two continuous 11ms time-window. For the computation of Sag threshold register value, refer to AN-644. The Sag event is captured by the SagWarn bit (b3, SysStatus0). If the corresponding IRQ enable bit the SagWnEn bit (b3, FuncEn0) is set, IRQ can be generated. Refer to Figure-28. 3.8.3 PHASE LOSS DETECTION The phase loss detection detects if there is one or more phases’ voltage is less than the phase-loss threshold voltage. The processing and handling is similar to sag detection, only the threshold is different. The threshold computation flow is also similar. The typical threshold setting could be 10% Un or less. If any phase line is detected as in phase-loss mode, that phase’s zero-crossing detection function (both voltage and current) is disabled. 3.8.4 3.8.4.1 NEUTRAL LINE OVERCURRENT DETECTION Sampled N-Line The neutral line computed current (calculated) RMS is checked with the threshold defined in the INWarnTh0 register. If the N Line current is greater than the threshold, the INOv0 bit (b14, SysStatus1) bit is set. IRQ1 is generated if the corresponding Enable bit the INOv0En bit (b14, FuncEn1) is set. 3.8.5 PHASE SEQUENCE ERROR DETECTION The phase sequence is detected in two cases: 3P4W and 3P3W, which is defined by the 3P3W bit (b8, MMode0). 3P4W case: Correct sequence: Voltage/current zero-crossing sequence: phaseA, phase-B and phase-C. 3P3W case: Correct sequence: Voltage/current zero-crossing between phase-A and phase-C is greater than 180 degree. If the above mentioned criteria are violated, it is assumed as a phase sequence error. 3.9 DC AND CURRENT RMS ESTIMATION The 90E36 has a module named ‘PMS’ which can estimate current channel RMS or current channel arithmetic average (DC component). The measurement type is defined in the PMConfig register. It can be used to estimate current RMS in Partial Measurement mode. Since the PMS block only consume very small power, it can be also used to estimate current RMS in Normal mode. The PMS module is turned on in both Partial Measurement mode and Normal mode. The result is in different format and different scale for the RMS and average respectively. The RMS result is unsigned; while current average is signed. Refer to 6.3.2 Partial Measurement mode Registers for associated register definition. The neutral line measured RMS is checked with the threshold defined in the INWarnTh1 register. If the N Line current is greater than the threshold, the INOv1 bit (b15, SysStatus1) is set. IRQ1 is generated if the corresponding Enable bit (the INOv1En bit (b15, FuncEn1)) is set. Function Description 26 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4 4.1 SPI / DMA INTERFACE INTERFACE DESCRIPTION Five pins are associated with the interface as below: SDI – Data pin, bi-directional. SDO – Data pin, bi-directional. SCLK – Bi-directional pin. It is a clock output pin in master mode and clock input pin in slave mode. • CS – Bi-directional chip select pin . It is an output pin in master mode and input pin in slave mode. • DMA_CTRL – Uni-directional input pin. The external device pull this pin high to control the interface work in master mode for data dumping in DMA mode. • • • The interface can work in two modes: Slave (SPI) mode and Master mode, which is also named DMA (Direct Memory Access) mode. The interface mode is determined by the DMA_CTRL pin as below: Mode Slave (SPI) Mode Master (DMA) Mode DMA_CTRL 0 1 Description The interface works as normal fourwire SPI interface. The interface operates as a master and dumps data to the other devices. SPI Interface logic (As slave) SDI SDO SCLK CS DMA_CTRL MOSI MISO SCK CS DMA_CTRL=0 Host controller in master mode MOSI MISO SCK GPIO1 GPIO2 Figure-12 Slave Mode SPI Interface logic (As master) SDI SDO SCLK CS DMA_CTRL MOSI MISO SCK CS DMA_CTRL=1 DSP slave mode MOSI MISO SCK SPISS GPIO Figure-13 Master Mode (PIN_DIR_SEL=0) SPI / DMA Interface 27 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4.2 SLAVE MODE: SPI INTERFACE Instruction Read Write Description read from registers write to registers Instruction Format 1 0 The interface works in slave mode when the DMA_CTRL pin is low as shown in Figure-12. 4.2.1 SPI SLAVE INTERFACE FORMAT In the SPI mode, data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK. Refer to Figure-14 and Figure-15 below for the timing diagram. Access type: The first bit on SDI defines the access type as below: Read Sequence: CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Address: Fixed 15-bit, following the access type bits. The lower 10-bit is decoded as address; the higher 5 bits are ‘Don't Care’. Read/Write data: Fixed as 16 bits. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCLK Register Address SDI SDO X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Don't care 16-bit data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 High Impedance Figure-14 Read Sequence Write Sequence: CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SCLK Register Address 16-bit data A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI SDO X X X X X A9 A8 A7 A6 A5 A4 High Impedance Figure-15 Write Sequence 4.2.2 RELIABILITY ENHANCEMENT FEATURE The SPI read/write transaction is CS-low defined. Each transaction can only access one register. Within each CS-low defined transaction: Write: access occurs only when CS goes from low to high and there are exactly 32 SCLK cycles received during CS low period. Read: if SCLK>=16 (full address received), data is read out from internal registers and gets to the SDO pin; and the LastSPIData register is updated. The R/C registers can only be cleared after the LastSPIData register is updated. SPI / DMA Interface 28 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4.3 MASTER MODE: DMA Clock Dividing Ratio The SCLK frequency of SPI interface is defined by the CLK_DIV[3:0] bits (b3~0, DMACtrl) as the following equation: f SCLK = f sys_clk CLK_DIV *2+ 2 The interface is defined to connect with various DSP processors for ADC samples dumping. For DMA configure please refer to DMACtrl register definition in 6.2 Special Registers. The interface works in Master mode when the DMA_CTRL pin is pulled high by the external device. In Master mode, registers in 90E36 cannot be accessed. The dump transaction can be stopped by the external device via pulling the DMA_CTRL pin to low at any time. Figure-13 shows a connection between 90E36 and a DSP processor where 90E36 acts as the master. 4.3.1 DMA BURST TRANSFER FOR ADC SAMPLING When the DMA_CTRL pin changes from low to high, the voltage and current channel ADC samples (after decimation and frequency compensation) are dumped out serially through the interface with SCLK frequency defined by the CLK_DIV[3:0] bits (b3~0, DMACtrl). When the 90E36 detects that the DMA_CTRL pin is de-asserted, it stops the DMA transaction after the current sample has been sent. Here fsys_clk means system’s oscillator frequency. Interface Direction In DMA mode, the interface direction of SDI/SDO pins are normally defined as Figure-13. But the direction also can be swapped by configuring the PIN_DIR_SEL bit (b8, DMACtrl). ADC Channel Selection Internally, the 90E36 has 7 ADC channels. The user can select which channel’s samples to be dumped out via configuring the ADC_CH_SE L[15:9] bits (b15~9, DMACtrl). Each bit of the 7-bit field ADC_CH_SEL enables the data dumping for one ADC channel. Set ‘1’ to a bit enables the dump of the corresponding ADC channel samples. Clock Modes Four clock modes are defined in master mode according to the CLK_DRV bit (b4, DMACtrl) and CLK_IDLE bit (b5, DMACtrl) configuration as the following diagram shows. CLOCK Cycle # SCLK (CLK_IDLE=0) SCLK (CLK_IDLE=1) SDI/SDO CS 1 2 3 4 N-2 N-1 N Figure-16 Clock Mode0 (CLK_DRV=0, CLK_IDLE=0) and Mode1 (CLK_DRV=0, CLK_IDLE=1) SPI / DMA Interface 29 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CLOCK Cycle # SCLK (CLK_IDLE=0) SCLK (CLK_IDLE=1) SDI/SDO CS 1 2 3 4 N-2 N-1 N Figure-17 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1) For mode0 and mode1 (CLK_DRV = 0), the first edge of SCLK is used by the slave to sample the data. For mode2 and mode3 (CLK_DRV=1), the first edge of SCLK is used by the master to drive out the data. ADC Channel Selection. During CS de-asserted state, the SCLK stays in idle state as configured by the CLK_IDLE bit (b5, DMACtrl). Data Frame Format and Sample Sequence in DMA Mode The 90E36 sends the ADC samples (In 8K sample rate) continuously in DMA mode. The samples of all enabled ADC channels are sent out in interleaved manner, with the sequence of I4, I1, V1, I2, V2, and I3, V3 (If any channel is disabled, remove it from the list while maintaining the sequence of the other channels). Figure-18 shows an example of the sample sequence when the ADC_CH_SEL[15:9] bits (b15~9, DMACtrl) are configured to be ‘0101001’. CS Deactivation for Rate Adaptation Since the bit rate may be higher than the equivalent bit rate of the samples (For example, for 24-bit non-frame mode, the equivalent bitrate is sample_rate*6*24bps). To compensate for that, the CS signal is de-asserted to wait for the new samples and be asserted again once the new sample arrives. There are at least 2 SCLK clock periods for CS resume from deasserted state to assert state depending on the Clock Dividing Ratio and I1 Samples on MOSI CS I2 V3 I1 I2 V3 I1 I2 V3 Samples 1 T=125µs Samples 2 Samples N Figure-18 Sample Sequence Example Bit Sequence The samples sent over the interfaces are the processed data according to the CH_BITWIDTH[7:6] bits (b7~6, DMACtrl). All the samples sent are MSB first. Figure-19 shows an example of sample bit sequence for 32-bit sample bit width. SPI / DMA Interface 30 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Samples Samples on MOSI CS I1 I2 V3 b23 b16 b15 b8 b7 b0 0 0 0 0 0 0 0 0 8 pads I1 sample N Figure-19 Sample Bit Sequence Example 4.3.2 CONTROL SEQUENCE FOR EXTERNAL DEVICE To start and stop the DMA dump sequence, the external device follows the rules described below: • Start of the dump process: a) The external device configures the DMACtrl register. b) The external device switches to SPI slave mode. Note that the parameters of clock idle state / driving edge, sample bit width and pin direction of SPI_D0/SPI_D1 configured to 90E36 should match with external device's settings. c) The external device asserts the DMA_CTRL signal. The 90E36 swaps I/O direction if necessary after it has detected that master has asserted the DMA. The samples are dumped out with a delay of at most 1 sample period (125us). • Stop of the dump process: a) The external device de-asserts the DMA_CTRL signal. The 90E36 stops the transaction after current (all selected) samples have been successfully sent out. b) The external device waits one sample period of 125us or detects that the CS signal is pulled high, then switches the interface back to master mode. SPI / DMA Interface 31 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5 5.1 CALIBRATION METHOD NORMAL MODE OPERATION CALIBRATION Calibration is done per phase and there is no need to calibrate for the all-phase-sum (total) parameters. The calibration method is as follows: Step-1: Register configuration for calibration - Start to configure the System configuration Registers by writing 5678H to the ConfigStart register. - The 90E36 automatically reset the configuration registers to their default value. - Program all the system configuration registers. - Calculate and write the checksum to the CS0 register. - Write 8765H to the ConfigStart register (enable checksum checking). - System may check the WarnOut pin to see if there is a checksum error. The start register and checksum handling scheme is the same throughout the calibration process, so the following section does not describe the start and checksum operation. Step-2: Measurement calibration (per-phase) - First calibrate offset at I = 0, U = 0 for current or/and voltage; • Configure calculated channel Gain (The user needs to program the PGA gain and DPGA gain properly in order to get the calculated gain within 0 to 2 in step-1). • Read Irms/ Urms value. • Calculate the compensation value. • Write the calculated value to the offset register. - Then calibrate gain at I = In (Ib), U = Un for current and voltage; • Read Irms/ Urms value. • Calculate the compensation value. • Write the calculated value to the Gain register. Step-3: Metering calibration (per phase) - First calibrate the Power/ Energy offset. • U = Un, I = 0. • Read full 32 bits (or lower 16 bits) Active and Reactive Power • Calculate the compensation values • Write the calculated values to the offset registers respectively. - Then calibrate Energy gain at unity power factor: • PF=1.0, U = Un, I = In (Ib). • Connect CF1 to the calibration bench; • User/ PC calculate the energy gain according to the data got from calibration bench • Write the calculated value to the Energy Gain register. - Then calibrate the phase angle compensation at 0.5 inductive power factor. • PF=0.5L, U = Un, I = In (Ib), Rated frequency = 50Hz, or 60Hz according to the application; • CF1 connected to the calibration bench; • User/ PC calculate the phase angle according to the data got from calibration bench; • Write the calculated value to the Phase angle register. 5.2 PARTIAL MEASUREMENT MODE CALIBRATION The calibration method is as follows: Step-1: Set the input current to zero and measure the current mean value (set MeasureType = 1, write 1 to the ReMeasure bit (b14, PMConfig) to trigger the measurement. Refer to the PMIrmsA register). Negate the result register (the PMIrmsA/PMIrmsB/PMIrmsC registers) reading (16-bit) and then write the result to the offset register. Step-2: The output of Partial Measurement result = ADC_input_voltage *PGA_gain*DPGA_gain*65536 / 1.2. For instance, a 150 mVrms signal (from CT) with PGA = 1 gets 8192 in the RMS result register. Step-3: The user needs to do its own conversion to get meaningful result. The scaling factor in user's software could be calibrated device per device. Calibration Method 32 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6 6.1 REGISTER REGISTER LIST Table-4 Register List Register Address 00H 01H 02H 03H 04H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Register Name SoftReset SysStatus0 SysStatus1 FuncEn0 FuncEn1 ZXConfig SagTh PhaseLossTh INWarnTh0 INWarnTh1 THDNUTh THDNITh DMACtrl LastSPIData Read/Write Type W R/C R/C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Functional Description Status and Special Register Software Reset System Status 0 System Status 1 Function Enable 0 Function Enable 1 Zero-Crossing Configuration Voltage Sag Threshold Voltage Phase Losing Threshold Similar to Voltage Sag Threshold register Threshold for calculated (Ia + Ib +Ic) N line rms Check SysStatus0/1 register. current Threshold for sampled (from ADC) N line rms Check SysStatus0/1 register. current Voltage THD Warning Threshold Current THD Warning Threshold DMA Mode Interface Control Last Read/ Write SPI Value Low Power Mode Register 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH DetectCtrl DetectThA DetectThB DetectThC PMOffsetA PMOffsetB PMOffsetC PMPGA PMIrmsA PMIrmsB PMIrmsC PMConfig PMAvgSamples PMIrmsLSB R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R Current Detect Control Phase A current threshold in Detection mode Phase B current threshold in Detection mode Phase C current threshold in Detection mode Ioffset for phase A in Partial Measurement mode Ioffset for phase B in Partial Measurement mode Ioffset for phase C in Partial Measurement mode PGAgain Configuration in Partial Measurement mode Irms for phase A in Partial Measurement mode Irms for phase B in Partial Measurement mode Irms for phase C in Partial Measurement mode Measure configuration in Partial Measurement mode Number of 8K samples to be averaged in RMS/ mean computation LSB bits of PMRrms[A/B/C] It returns MSB of the mean measurement data in Mean value test P 49 P 50 P 50 P 51 P 51 P 51 P 51 P 52 P 52 P 52 P 52 P 53 P 53 P 53 Check SysStatus0/1 register. Check SysStatus0/1 register. DMA mode interface control Refer to 4.2.2 Reliability Enhancement Feature Configuration of ZX0/1/2 pins’ source P 40 P 42 P 42 P 44 P 44 P 46 P 46 P 46 P 47 P 47 P 47 P 47 P 48 P 48 Comment Page Register 33 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 50H 51H 52H 53H 54H 55H 56H 57H Register Name ConfigStart PLconstH PLconstL MMode0 MMode1 PStartTh QStartTh SStartTh PPhaseTh QPhaseTh SPhaseTh CS0 CalStart PoffsetA QoffsetA POffsetB QOffsetB POffsetC QOffsetC GainA PhiA GainB PhiB GainC PhiC CS1 HarmStart POffsetAF POffsetBF POffsetCF PGainAF PGainBF PGainCF CS2 Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Functional Description Configuration Registers Calibration Start Command High Word of PL_Constant Low Word of PL_Constant Metering method configuration PGA gain configuration Active Startup Power Threshold. Reactive Startup Power Threshold. Apparent Startup Power Threshold. Startup Power Threshold (Active Energy Accumulation) Startup Power Threshold (ReActive Energy Accumulation) Startup Power Threshold (Apparent Energy Accumulation) Checksum 0 Calibration Registers Calibration Start Command Phase A Active Power Offset Phase A Reactive Power Offset Phase B Active Power Offset Phase B Reactive Power Offset Phase C Active Power Offset Phase C Reactive Power Offset Phase A calibration gain Phase A calibration phase angle Phase B calibration gain Phase B calibration phase angle Phase C calibration gain Phase C calibration phase angle Checksum 1 Fundamental/ Harmonic Energy Calibration registers Harmonic Calibration Startup Command Phase A Fundamental Active Power Offset Phase B Fundamental Active Power Offset Phase C Fundamental Active Power Offset Phase A Fundamental Active Power Gain Phase B Fundamental Active Power Gain Phase C Fundamental Active Power Gain Checksum 2 Refer to Table-7. Refer to Table-6. P 59 P 59 P 59 P 59 P 58 Refer to Table-5. P 55 P 55 P 55 P 56 P 57 Comment Page Register 34 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 98H 99H Register Name AdjStart UgainA IgainA UoffsetA IoffsetA UgainB IgainB UoffsetB IoffsetB UgainC IgainC UoffsetC IoffsetC IgainN IoffsetN CS3 APenergyT APenergyA APenergyB APenergyC ANenergyT ANenergyA ANenergyB ANenergyC RPenergyT RPenergyA RPenergyB RPenergyC RNenergyT RNenergyA RNenergyB RNenergyC SAenergyT SenergyA SenergyB SenergyC SVenergyT EnStatus0 EnStatus1 SVmeanT SVmeanTLSB Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R R R R Functional Description Measurement Calibration Measurement Calibration Startup Command Phase A Voltage RMS Gain Phase A Current RMS Gain Phase A Voltage RMS Offset Phase A Current RMS Offset Phase B Voltage RMS Gain Phase B Current RMS Gain Phase B Voltage RMS Offset Phase B Current RMS Offset Phase C Voltage RMS Gain Phase C Current RMS Gain Phase C Voltage RMS Offset Phase C Current RMS Offset Sampled N line Current RMS Gain Sampled N line Current RMS Offset Checksum 3 Energy Register Total Forward Active Energy Phase A Forward Active Energy Phase B Forward Active Energy Phase C Forward Active Energy Total Reverse Active Energy Phase A Reverse Active Energy Phase B Reverse Active Energy Phase C Reverse Active Energy Total Forward Reactive Energy Phase A Forward Reactive Energy Phase B Forward Reactive Energy Phase C Forward Reactive Energy Total Reverse Reactive Energy Phase A Reverse Reactive Energy Phase B Reverse Reactive Energy Phase C Reverse Reactive Energy Total (Arithmetic Sum) Apparent Energy Phase A Apparent Energy Phase B Apparent Energy Phase C Apparent Energy (Vector Sum) Total Apparent Energy Metering Status 0 Metering Status 1 (Vector Sum) Total Apparent Power LSB of (Vector Sum) Total Apparent Power P 62 P 62 Refer to Table-9. Refer to Table-8. Comment Page Register 35 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH Register Name APenergyTF APenergyAF APenergyBF APenergyCF ANenergyTF ANenergyAF ANenergyBF ANenergyCF APenergyTH APenergyAH APenergyBH APenergyCH ANenergyTH ANenergyAH ANenergyBH ANenergyCH Read/Write Type R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Functional Description Fundamental / Harmonic Energy Register Total Forward Active Fundamental Energy Phase A Forward Active Fundamental Energy Phase B Forward Active Fundamental Energy Phase C Forward Active Fundamental Energy Total Reverse Active Fundamental Energy Phase A Reverse Active Fundamental Energy Phase B Reverse Active Fundamental Energy Phase C Reverse Active Fundamental Energy Total Forward Active Harmonic Energy Phase A Forward Active Harmonic Energy Phase B Forward Active Harmonic Energy Phase C Forward Active Harmonic Energy Total Reverse Active Harmonic Energy Phase A Reverse Active Harmonic Energy Phase B Reverse Active Harmonic Energy Phase C Reverse Active Harmonic Energy Refer to Table-10. P 63 Comment Page Register 36 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH Register Name PmeanT PmeanA PmeanB PmeanC QmeanT QmeanA QmeanB QmeanC SAmeanT SmeanA SmeanB SmeanC PFmeanT PFmeanA PFmeanB PFmeanC PmeanTLSB PmeanALSB PmeanBLSB PmeanCLSB QmeanTLSB QmeanALSB QmeanBLSB QmeanCLSB SAmeanTLSB SmeanALSB SmeanBLSB SmeanCLSB Read/Write Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R Functional Description Power and Power Factor Registers Total (all-phase-sum) Active Power Phase A Active Power Phase B Active Power Phase C Active Power Total (all-phase-sum) Reactive Power Phase A Reactive Power Phase B Reactive Power Phase C Reactive Power Total (Arithmetic Sum) apparent power phase A apparent power phase B apparent power phase C apparent power Total power factor phase A power factor phase B power factor phase C power factor Lower word of Total (all-phase-sum) Active Power Lower word of Phase A Active Power Lower word of Phase B Active Power Lower word of Phase C Active Power Lower word of Total (all-phase-sum) Reactive Power Lower word of Phase A Reactive Power Lower word of Phase B Reactive Power Lower word of Phase C Reactive Power Lower word of Total (Arithmetic Sum) apparent power Lower word of phase A apparent power Lower word of phase B apparent power Lower word of phase C apparent power Refer to Table-11. P 63 Comment Page Register 37 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E9H EAH EBH EDH EEH EFH Register Name PmeanTF PmeanAF PmeanBF PmeanCF PmeanTH PmeanAH PmeanBH PmeanCH IrmsN1 UrmsA UrmsB UrmsC IrmsN0 IrmsA IrmsB IrmsC PmeanTFLSB PmeanAFLSB PmeanBFLSB PmeanCFLSB PmeanTHLSB PmeanAHLSB PmeanBHLSB PmeanCHLSB UrmsALSB UrmsBLSB UrmsCLSB IrmsALSB IrmsBLSB IrmsCLSB Read/Write Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Functional Description Total active fundamental power phase A active fundamental power phase B active fundamental power phase C active fundamental power Total active harmonic power phase A active harmonic power phase B active harmonic power phase C active harmonic power N Line Sampled current RMS phase A voltage RMS phase B voltage RMS phase C voltage RMS N Line calculated current RMS phase A current RMS phase B current RMS Lower word of Total active fundamental Power Refer to Table-12. Lower word of phase A active fundamental Power Lower word of phase B active fundamental Power Lower word of phase C active fundamental Power Lower word of Total active harmonic Power Lower word of phase A active harmonic Power Lower word of phase B active harmonic Power Lower word of phase C active harmonic Power Lower word of phase A voltage RMS Lower word of phase B voltage RMS Lower word of phase C voltage RMS Lower word of phase A current RMS Lower word of phase B current RMS Lower word of phase C current RMS phase C current RMS Comment Page P 64 Fundamental / Harmonic Power and Voltage / Current RMS Registers Register 38 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address F1H F2H F3H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH 100H ~ 1BFH 1D0H ~ 1D1H Register Name THDNUA THDNUB THDNUC THDNIA THDNIB THDNIC Freq PAngleA PAngleB PAngleC Temp UangleA UangleB UangleC Read/Write Type R R R R R R R R R R R R R R Functional Description phase A voltage THD+N phase B voltage THD+N phase C voltage THD+N phase A current THD+N phase B current THD+N phase C current THD+N Frequency phase A mean phase angle phase B mean phase angle phase C mean phase angle Measured temperature phase A voltage phase angle phase B voltage phase angle phase C voltage phase angle Harmonic Fourier Analysis Registers R Refer to Table-14. R/W P 66 Refer to Table-13. Comment Page P 65 THD+N, Frequency, Angle and Temperature Registers Register 39 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.2 6.2.1 SPECIAL REGISTERS SOFT RESET REGISTER SoftReset Software Reset Address: 00H Type: Write Default Value: 0000H Bit 15 - 0 Name Description Software reset register. The 90E36 resets only if 789AH is written to this register. The reset domain is the same as the RESET SoftReset[15:0] pin or Power On Reset. Reading this register always return 0. Register 40 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.2.2 IRQ AND WARNOUT SIGNAL GENERATION Status bits in the SysStatus0 register generate an interrupt and get the IRQ0 pin to be asserted if the corresponding enable bits are set in the FuncEn0 register. Status bits in the SysStatus1 register generate an interrupt and get the IRQ1 pin to be asserted, if the corresponding enable bits are set in the FuncEn1 register. Some of the status signals can also assert the WarnOut pin. The following diagram illustrates how the status bits, enable bits and IRQ/ WarnOut pins work together. event capture Status 1 WarnOut Status without enable Read clear Status with enable Status 2 EN Read clear event capture Status n Enable n Enable 2 IRQ0/1 Read clear Register bits in SysStatus0/1 Register bits in FuncEn0/1 Figure-20 IRQ and WarnOut Generation Register 41 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SysStatus0 System Status 0 Address: 01H Type: Read/Clear Default Value: 0000H Bit 15 14 13 12 11 10 9 8 Name CS0Err CS1Err CS2Err CS3Err Reserved. * Description This bit indicates CS0 (3BH) checksum status. 0: CS0 checksum correct (default) 1: CS0 checksum error. The WarnOut pin is asserted at the same time. Reserved. This bit indicates CS1 (4DH) checksum status. 0: CS1 checksum correct (default) 1: CS1 checksum error. The WarnOut pin is asserted at the same time. Reserved. This bit indicates CS2 (57H) checksum status. 0: CS2 checksum correct (default) 1: CS2 checksum error. The WarnOut pin is asserted at the same time. Reserved. This bit indicates CS3 (6FH) checksum status. 0: CS3 checksum correct (default) 1: CS3 checksum error. The WarnOut pin is asserted at the same time. This bit indicates whether there is any error with the voltage phase sequence. 0: No error with the voltage phase sequence (default) 1: Error with the voltage phase sequence. This bit indicates whether there is any error with the current phase sequence. 0: No error with the current phase sequence (default) 1: Error with the current phase sequence. Reserved. This bit indicates whether there is any voltage sag (voltage lower than threshold) in one phase or more. 0: No voltage sag (default) 1: Voltage sag. 7 URevWn 6 5-4 3 IRevWn SagWarn 2 1-0 This bit indicates whether there is any voltage phase losing in one phase or more. PhaseLoseWn 0: No voltage phase losing (default) 1: Voltage phase losing. Reserved. Note: All reserved bits of any register should be ignored when reading and should be written with zero. Register 42 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SysStatus1 System Status 1 Address: 02H Type: Read/Clear Default Value: 0000H Bit 15 Name INOv1 Description This bit indicates whether the N line current sampling value is greater than the threshold set by the INWarnTh1 register. 0: Not greater than the threshold (default) 1: Greater than the threshold. This bit indicates whether the calculated N line current is greater than the threshold set by the INWarnTh0 register. 0: Not greater than the threshold (default) 1: Greater than the threshold. Reserved. This bit indicates whether one or more voltage THDUx (THDUA/ THDUB/ THDUC) is greater than the threshold set by the THDNUTh register. 0: Not greater than the threshold (default) 1: Greater than the threshold. This bit indicates whether one or more current THDIx (THDIA/ THDIB/ THDIC) is greater than the threshold set by the THDNITh register. 0: Not greater than the threshold (default) 1: Greater than the threshold. This bit indicates whether the DFT data is ready. 0: Not ready (default) 1: Ready. Reserved. When there is any direction change of active/reactive energy for all-phase-sum or individual phase (from forward to reverse, or from reverse to forward), the corresponding status bit is set. The judgment of direction change is solely based on the energy register (not related to the CF pulses), and dependent on the energy register resolution (0.01CF / 0.1CF setting set by the 001LSB bit (b9, MMode0)). 0: direction of active/reactive energy no change (default) 1: direction of active/reactive energy changed The status bits are RevQchgT/ RevPchgT are status bits for all-phase-sum and RevQchgA/ RevQchgB/ RevQchgC/ RevPchgA/ RevPchgB/ RevPchgC are for individual phase. 14 13-12 11 INOv0 THDUOv 10 THDIOv 9 8 7 6 5 4 3 2 1 0 DFTDone RevQchgT RevQchgA RevQchgB RevQchgC RevPchgT RevPchgA RevPchgB RevPchgC Register 43 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FuncEn0 Function Enable 0 Address: 03H Type: Read/Write Default Value: 0000H Bit 15-11 10 9-8 7 Name CS2ErrEn URevWnEn Description Reserved. This bit determines whether to enable the interrupt when the CS2Err bit (b10, SysStatus0) is set. 0: disable (default) 1: enable Reserved. This bit determines whether to enable the interrupt when the URevWn bit (b7, SysStatus0) is set. 0: disable (default) 1: enable This bit determines whether to enable the interrupt when the IRevWn bit (b6, SysStatus0) is set. 0: disable (default) 1: enable Reserved. This bit determines whether to enable the voltage sag interrupt when the SagWarn bit (b3, SysStatus0) is set. 0: disable (default) 1: enable 6 5-4 3 IRevWnEn SagWnEn 2 1-0 This bit determines whether to enable the interrupt when the PhaseLoseWn bit (b2, SysStatus0) is set. PhaseLoseWnEn 0: disable (default) 1: enable Reserved. Register 44 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FuncEn1 Function Enable 1 Address: 04H Type: Read/Write Default Value: 0000H Bit 15 Name INOv1En Description This bit determines whether to enable the interrupt when the INOv1 bit (b15, SysStatus1) is set. 0: disable (default) 1: enable This bit determines whether to enable the interrupt when the INOv0 bit (b14, SysStatus1) is set. 0: disable (default) 1: enable Reserved. This bit determines whether to enable the interrupt when the THDUOv bit (b11, SysStatus1) is set. 0: disable (default) 1: enable This bit determines whether to enable the interrupt when the THDIOv bit (b10, SysStatus1) is set. 0: disable (default) 1: enable This bit determines whether to enable the interrupt when the DFTDone bit (b9, SysStatus1) is set. 0: disable (default) 1: enable Reserved. 14 13-12 11 INOv0En THDUOvEn 10 THDIOvEn 9 8 7 6 5 4 3 2 1 0 DFTDone RevQchgTEn RevQchgAEn RevQchgBEn RevQchgCEn RevPchgTEn RevPchgAEn RevPchgBEn RevPchgCEn These bits determine whether to enable the corresponding interrupt when any of the direction change bits (b7~b0, SysStatus1) is set. 0: disable (default) 1: enable Register 45 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.2.3 SPECIAL CONFIGURATION REGISTERS ZXConfig Zero-Crossing Configuration Address: 07H Type: Read/Write Default Value: 0001H Bit 15:13 12:10 Name ZX2Src[2:0] ZX1Src[2:0] Code 011 000 001 010 111 100 101 110 Source Fixed-0 Ua Ub Uc Fixed-0 Ia Ib Ic Description These bits select the signal source for the ZX2, ZX1 or ZX0 pins. 9:7 ZX0Src[2:0] 6:5 4:3 ZX2Con[1:0] ZX1Con[1:0] These bits configure zero-crossing mode for the ZX2, ZX1 and ZX0 pins. Code 00 01 10 11 Zero-Crossing Configuration positive zero-crossing negative zero-crossing all zero-crossing no zero-crossing output 2:1 ZX0Con[1:0] 0 ZXdis This bit determines whether to disable the ZX signals: 0: enable 1: disable all the ZX signals to ‘0’ (default). SagTh Voltage Sag Threshold Address: 08H Type: Read/Write Default Value: 0000H Bit 15:0 Name SagTh Description Unsigned 16-bit integer with unit related to PGA and voltage sense circuits. Refer to 3.8.2 Sag Detection. PhaseLossTh Voltage Phase Losing Threshold Address: 09H Type: Read/Write Default Value: 0000H Bit 15:0 Name PhaseLossTh Description Unsigned 16-bit integer with unit related to PGA and voltage sense circuits. Refer to 3.8.3 Phase Loss Detection. Register 46 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC INWarnTh0 Neutral Current (Calculated) Warning Threshold Address: 0AH Type: Read/Write Default Value: FFFFH Bit 15:0 Name INWarnTh0 Description Neutral current (calculated) warning threshold. Threshold for calculated (Ia + Ib +Ic) N line rms current. Unsigned 16 bit, unit 1mA. If N line rms current is greater than the threshold, The INOv0 bit (b14, SysStatus1) will be asserted if enabled. Refer to 3.8.4.2 Computed N-Line. INWarnTh1 Neutral Current (Sampled) Warning Threshold Address: 0BH Type: Read/Write Default Value: FFFFH Bit 15:0 Name INWarnTh1 Description Neutral Current (Sampled) Warning threshold. Threshold for sampled (from ADC) N line rms current. Unsigned 16 bit, unit 1mA. If N line rms current is greater than the threshold, The INOv1 bit (b15, SysStatus1) will be asserted if enabled. Refer to 3.8.4.1 Sampled N-Line. THDNUTh Voltage THD Warning Threshold Address: 0CH Type: Read/Write Default Value: FFFFH Bit 15:0 Name THDNUTh Description Voltage THD Warning threshold. Voltage THD+N Threshold. Unsigned 16 bit, unit 0.01%. Exceeding the threshold will assert the THDUOv bit (b11, SysStatus1) if enabled. THDNITh Current THD Warning Threshold Address: 0DH Type: Read/Write Default Value: FFFFH Bit 15:0 Name THDNITh Description Current THD Warning threshold. Current THD+N Threshold. Unsigned 16-bit, unit 0.01%. Exceeding the threshold will assert the THDIOv bit (b10, SysStatus1) if enabled. Register 47 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DMACtrl DMA Mode Interface Control Address: 0EH Type: Read/Write Default Value: 7E44H Bit Name Description These bits configure the data source of the ADC channel. Each bit enables the data dumping for one ADC channel as the following diagram shows. Set a ‘1’ to a bit enables the dumping of the corresponding ADC channel samples. b15 15:9 ADC_CH_SEL I4 b14 b13 b12 b11 b10 b9 I1 V1 I2 V2 I3 V3 Note: I1 to phase A and I3 to phase C mapping can be swapped by configuring the I1I3Swap bit (b13, MMode0). This bit configures the direction of the SDI and SDO pins. PIN_DIR_SEL 0 1 Master Mode (DMA_Ctrl=1) SDI→MOSI SDO←MISO SDI←MISO SDO→MOSI 8 PIN_DIR_SEL These bits configure the bit width for each channel. Code 00 01 10 11 Channel Bit Width 32 bits 24 bits (default) 16 bits reserved 7:6 CH_BIT_WIDTH 5 CLK_IDLE This bit configures the Idle state clock level. 0: Idle low (default) 1: Idle High This bit configures which edge to drive data out. 0: Second edge drives data out. (default) 1: First edge drives data out. Divide ratio to generate SCLK frequency from SYS_CLK. Default value is ‘100’. 4 3:0 CLK_DRV CLK_DIV 6.2.4 LAST SPI DATA REGISTER LastSPIData Last Read/Write SPI Value Address: 0FH Type: Read Default Value: 0000H Bit 15:0 Name Description LastSPIData15 - This register is a special register which logs data of the previous SPI Read or Write access especially for Read/Clear registers. LastSPIData0 This register is useful when the user wants to check the integrity of the last SPI access. Register 48 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.3 6.3.1 LOW-POWER MODES REGISTERS DETECTION MODE REGISTERS Current Detection register latching scheme is: When any of the 4 current detection registers (0x10 - 0x13) were programmed, all the 4 current detection registers (including the registers that not being programmed) will be automatically latched into the current detector's internal configuration latches at the same time. Those latched configuration values are not subject to digital reset signals and will be kept in all the 4 power modes. The power up value of those latches is not deterministic, so user needs to program the current detection registers to update. Current detector register Write update registers 0x10 0x11 0x12 0x13 Current Detector block latch latch latch latch Figure-21 Current Detection Register Latching Scheme DetectCtrl Current Detect Control Address: 10H Type: Read/Write Default Value: 0000H Bit 15:6 5:0 Name DetectCtrl Reserved. Detector power-down, active high: [5:3]: Power-down for negative detector of channel 3/2/1; [2:0]: Power-down for positive detector of channel 3/2/1. Description Register 49 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DetectThA Phase A Current Threshold in Detection Mode Address: 11H Type: Read/Write Default Value: 0000H Bit 15 Name Reserved. Channel I1 negative detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Reserved. Channel I1 positive detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Description 14:8 CalCodeN 7 - 6:0 CalCodeP DetectThB Phase B Current Threshold in Detection Mode Address: 12H Type: Read/Write Default Value: 0000H Bit 15 Name Reserved. Channel I2 negative detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Reserved. Channel I2 positive detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Description 14:8 CalCodeN 7 - 6:0 CalCodeP Register 50 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DetectThC Phase C Current Threshold in Detection Mode Address: 13H Type: Read/Write Default Value: 0000H Bit 15 Name Reserved. Channel I3 negative detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Reserved. Channel I3 positive detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4µV=95.7µVrms Description 14:8 CalCodeN 7 - 6:0 CalCodeP The calibration method is that, the user program the detection threshold and test with the standard input signal until the output trips. 6.3.2 PARTIAL MEASUREMENT MODE REGISTERS PMOffsetA Ioffset for phase A in Partial Measurement mode Address: 14H Type: Read/Write Default Value: 0000H Bit 15-14 13:0 Name PMOffsetA Reserved. Phase A current offset in Partial Measurement mode. Description PMOffsetB Ioffset for phase B in Partial Measurement mode Address: 15H Type: Read/Write Default Value: 0000H Bit 15-14 13:0 Name PMOffsetB Reserved. Phase B current offset in Partial Measurement mode. Description PMOffsetC Ioffset for phase C in Partial Measurement mode Address: 16H Type: Read/Write Default Value: 0000H Bit 15-14 13:0 Name PMOffsetC Reserved. Phase C current offset in Partial Measurement mode. Description Register 51 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PMPGA PGAgain Configuration in Partial Measurement mode Address: 17H Type: Read/Write Default Value: 0000H Bit 15-14 13:0 Name DPGA PGAGain DPGA in Partial Measurement mode. PGAGain in Partial Measurement mode Refer to the MMode1 register for encoding and mapping. Description PMIrmsA Irms for phase A in Partial Measurement mode Address: 18H Type: Read Default Value: 0000H Bit 15:0 Name PMIrmsA * Description Current RMS/mean result in Partial Measurement mode. Format: It is unsigned for RMS while signed for mean value. Note: For current measuring in Partial Measurement mode, current gain is suggested to realized by external MCU and current RMS value shall not exceed 40A. PMIrmsB Irms for phase B in Partial Measurement mode Address: 19H Type: Read Default Value: 0000H Bit 15:0 Name PMIrmsB * Description Current RMS/mean result in Partial Measurement mode. Format: It is unsigned for RMS while signed for mean value. Note: For current measuring in Partial Measurement Mode, current gain is suggested to realized by external MCU and current RMS value shall not exceed 40A. PMIrmsC Irms for phase C in Partial Measurement mode Address: 1AH Type: Read Default Value: 0000H Bit 15:0 Name PMIrmsC * Description Current RMS/mean result in Partial Measurement mode. Format: It is unsigned for RMS while signed for mean value. Note: For current measuring in Partial Measurement Mode, current gain is suggested to realized by external MCU and current RMS value shall not exceed 40A. Register 52 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PMConfig Measure Configuration in Partial Measurement mode Address: 1BH Type: Read/Write Default Value: 0000H Bit 15 14 13 Name ReMeasure Reserved. This bit is ‘1’-write-only. Write ‘1’ to this bit will trigger another measurement cycle. Description This bit configures start of measurement whether starts from zero crossing point. MeasureStartZX 0: Measurement start immediately (default) 1: Measurement start from zero-crossing point MeasureType PMBusy This bit indicates the measurement type. 0: RMS measurement (default) 1: Mean Value (DC Average) measurement Reserved. This bit indicates the measure status. This bit is read-only. 0: Measurement done (default) 1: Measurement in progress 12 11-1 0 PMAvgSamples Number of 8K Samples to be Averaged Address: 1CH Type: Read Default Value: 00A0H Bit 15:0 Name Description Number of 8K samples to be averaged in RMS/mean computation. PMIrmsLSB LSB bits of PMRrms[A/B/C] Address: 1DH Type: Read Default Value: 0000H Bit 15:12 11:8 7:4 3:0 Name IrmsCLSB IrmsBLSB IrmsALSB Reserved. These bits indicate LSB of the corresponding phase RMS measurement result if the MeasureType bit (b12, PMConfig) =0. These bits indicate MSB of the corresponding phase mean measurement result if the MeasureType bit (b12, PMConfig) =1. Description Register 53 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.4 6.4.1 CONFIGURATION AND CALIBRATION REGISTERS START REGISTERS AND ASSOCIATED CHECKSUM OPERATION SCHEME The Start Registers (ConfigStart (30H), CalStart (40H), HarmStart (50H) and AdjStart (60H)) and associated registers / checksum have a special operation scheme to protect important configuration data, illustrated below in the diagram. Start registers have multiple valid settings for different operation modes. Start Register Value 6886H 5678H 8765H Other Usage Power up state Calibration Operation Error Operation It is the value after reset. This state blocks checksum checking error generation Similar like 6886H, This state blocks checksum checking error generation. Writing with this value trigger a reset to the associated registers. Checksum checking is enabled and if error detected, IRQ/Warn is asserted and Metering stopped. Force checksum error generation and system stop. xxxStart = 5678H xxxStart register 0 1 1 0 0 1 Checksum Computation Error xxxStart = 8765H 0 1 xxxStart = 6886H Checksum Error Metering Enable Start Associated Regisers 0 IRQ/WarnOut Generation User Read User Write CheckSum (computed) CheckSum (programmed) Compare Error?  xxxStart refers to ConfigStart, CalStart, HarmStart and AdjStart. Those registers and their assoicated checksum computation has similar behavior.  xxxStart registers’ reset value is 6886H.  Writing 5678H to xxxStart register will trigger a reset to its associated register. Register can be accessed after reset.  xxxStart associated register is the register between xxxStart and associated checksum Figure-22 Start and Checksum Register Operation Scheme 6.4.2 CONFIGURATION REGISTERS Table-5 Configuration Registers Register Address 30H 31H 32H 33H 34H 35H 36H 37H Register Name ConfigStart PLconstH PLconstL MMode0 MMode1 PStartTh QStartTh SStartTh Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W Functional Description Configuration Registers Calibration Start Command High Word of PL_Constant Low Word of PL_Constant * Power-on Value and Comments 6886H 0861H C468H HPF/Integrator On/off, CF and all-phase energy 0087H computation configuration PGA gain configuration Active Startup Power Threshold. 16 bit unsigned integer, Unit: 0.00032 Watt Reactive Startup Power Threshold. 16 bit unsigned integer, Unit: 0.00032 var Apparent Startup Power Threshold. 16 bit unsigned integer, Unit: 0.00032 VA 0000H 0000H. 0000H 0000H Register 54 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-5 Configuration Registers Register Address 38H Register Name PPhaseTh Read/Write Type R/W Functional Description Power-on Value and Comments Startup power threshold (for |P|+|Q| of a phase) for 0000H any phase participating Active Energy Accumula- 16 bit unsigned integer, tion. Common for phase A/B/C. Unit: 0.00032 Watt/var Startup power threshold (for |P|+|Q| of a phase) for 0000H any phase participating ReActive Energy Accumula- 16bit unsigned integer, tion. Common for phase A/B/C. Unit: 0.00032 Watt/var Startup power threshold (for |P|+|Q| of a phase) for 0000H any phase participating Apparent Energy Accumula- 16 bit unsigned integer, tion. Common for phase A/B/C. Unit: 0.00032 Watt/var Checksum 0 Checksum register. 421CH (calculated value after reset) 39H QPhaseTh R/W 3AH 3BH SPhaseTh CS0 RW R/W Note: For details, please refer to IDT application note AN-644. ConfigStart Configure Start Command Address: 30H Type: Read/Write Default Value: 6886H Bit 15 - 0 Name CalStart[15:0] Description Refer to 6.4.1 Start Registers and Associated Checksum Operation Scheme. PLconstH High Word of PL_Constant Address: 31H Type: Read/Write Default Value: 0861H Bit Name Description The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. PL_Constant is a constant which is proportional to the sampling ratios of voltage and current, and inversely proportional to the Meter Constant. PL_Constant is a threshold for energy calculated inside the chip, i.e., energy larger than PL_Constant will be PLconstH[15:0] accumulated as 0.01CFx in the corresponding energy registers and then output on CFx if one CF reaches. It is suggested to set PL_constant as a multiple of 4 so as to double or redouble Meter Constant in low current state to save verification time. 15 - 0 PLconstL Low Word of PL_Constant Address: 32H Type: Read/Write Default Value: C468H Bit 15 - 0 Name Description The PLconstH[15:0] and PLconstL[15:0] bits are high word and low word of PL_Constant respectively. PLconstL[15:0] It is suggested to set PL_constant as a multiple of 4. Register 55 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMode0 Metering method configuration Address: 33H Type: Read/Write Default Value: 0087H Bit 15-14 13 Name I1I3Swap Reserved. This bit defines phase mapping for I1 and I3: 0: I1 maps to phase A, I3 maps to phase C (default) 1: I1 maps to phase C, I3 maps to phase A Note: I2 always maps to phase B. Current Grid operating line frequency. 0: 50Hz (default) 1: 60Hz Disable HPF in the signal processing path. Enable Integrator for didt current sensor. 0: disable (default) 1: enable Energy register LSB configuration for all energy registers: 0: 0.1CF (default) 1: 0.01CF This bit defines the voltage/current phase sequence detection mode: 0: 3P4W (default) 1: 3P3W (Ua is Uab, Uc is Ucb, Ub is not used) CF2 pin source: 0: apparent energy 1: reactive energy (default) This bit is to configure the apparent energy type in power factor calibration, and in CF2 output if apparent energy is selected by setting CF2varh=0. 0:All-phase apparent energy arithmetic sum (default) 1:All-phase apparent energy vector sum Reserved. These bits configure the calculation method of total (all-phase-sum) reactive/active energy and power: 0: Arithmetic sum: (default) ET=EA*EnPA+ EB*EnPB+ EC*EnPC PT= PA*EnPA+ PB*EnPB+ PC*EnPC 1: Absolute sum: ET=|EA|*EnPA+ |EB|*EnPB+ |EC|*EnPC PT=|PA|*EnPA+ |PB|*EnPB+ |PC|*EnPC Note: ET is the total (all-phase-sum) energy, EA/EB/EC are the signed phase A/B/C energy respectively. Reverse energy is negative. PT is the total (all-phase-sum) power, PA/PB/PC are the signed phase A/B/C power respectively. Reverse power is negative. These bits configure whether Phase A/B/C are counted into the all-phase sum energy/power (P/Q/S). 1: Corresponding Phase A/B/C to be counted into the all-phase sum energy/power (P/Q/S) (default) 0: Corresponding Phase A/B/C not counted into the all-phase sum energy/power (P/Q/S) Description 12 11 10 Freq60Hz HPFOff didtEn 9 001LSB 8 3P3W 7 CF2varh 6 5 CF2ESV - 4 ABSEnQ 3 ABSEnP 2 1 0 EnPA EnPB EnPC Register 56 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMode1 PGA Gain Configuration Address: 34H Type: Read/Write Default Value: 0000H Bit Name Description Digital PGA gain for the 4 current channels. This gain is implemented at the end of decimation filter. 00: Gain = 1 (default) 01: Gain = 2 10: Gain = 4 11: Gain = 8 PGA gain for all ADC channels. Mapping: [13:12]: V3 [11:10]: V2 [9:8]: V1 [7:6]: I4 [5:4]: I3 [3:2]: I2 [1:0]: I1 Encoding: 00: 1X (default) 01: 2X 10: 4X 11: N/A 15-14 DPGA_GAIN 13-0 PGA_GAIN Register 57 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CS0 Checksum 0 Address: 3BH Type: Read/Write Default Value: 421CH Bit Name Description This register should be written after the 31H-3AH registers are written. Suppose the high byte and the low byte of the 31H-3AH registers are shown in the below table. Register Address 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH The calculation of the CS0 register is as follows: The low byte of 3BH register is: L3B=MOD(H31+H32+...+H3A+L31+L32+...+L3A, 2^8) The high byte of 3BH register is: H3B=H31 XOR H32 XOR... XOR H3A XOR L31 XOR L32 XOR... XOR L3A The 90E36 calculates CS0 regularly. If the value of the CS0 register and the calculation by the 90E36 is different when ConfigStart=8765H, the CS0Err bit (b14, SysStatus0) is set and the WarnOut and IRQ pins are asserted. Note: The readout value of the CS0 register is the calculation by the 90E36, which is different from what is written. High Byte H31 H32 H33 H34 H35 H36 H37 H38 H39 H3A Low Byte L31 L32 L33 L34 L35 L36 L37 L38 L39 L3A 15 - 0 CS0[15:0] There are multiple Start register and Checksum (CS0/CS1/CS2/CS3) registers for different crucial register blocks. Those registers are handled in the similar way. 6.4.3 ENERGY CALIBRATION REGISTERS Table-6 Calibration Registers Register Address 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H Register Name CalStart POffsetA QOffsetA POffsetB QOffsetB POffsetC QOffsetC GainA PhiA GainB Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Functional Description Calibration Registers Calibration Start Command Phase A Active Power Offset Phase A Reactive Power Offset Phase B Active Power Offset Phase B Reactive Power Offset Phase C Active Power Offset Phase C Reactive Power Offset Phase A Active/Reactive Energy calibration gain Phase A calibration phase angle Phase B Active/Reactive Energy calibration gain 6886H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Power-on Value Register 58 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-6 Calibration Registers Register Address 4AH 4BH 4CH 4DH Register Name PhiB GainC PhiC CS1 * Read/Write Type R/W R/W R/W R/W Functional Description Phase B calibration phase angle Phase C Active/Reactive Energy calibration gain Phase C calibration phase angle Checksum 1 Power-on Value 0000H 0000H 0000H 0000H Note: The calculation of the CS1 register is similar as the CS0 register by calculating the 41H-4CH registers. For details, please refer to IDT application note AN-644. PoffsetA Phase A Active Power Offset Address: 41H Type: Read/Write Default Value: 0000H Bit 15-0 Name Offset Power offset. Signed 16-bit integer. Description QoffsetA Phase A Reactive Power Offset Address: 42H Type: Read/Write Default Value: 0000H Bit 15-0 Name Offset Power offset. Signed 16-bit integer. Description GainA Phase A Active/Reactive Energy calibration gain Address: 47H Type: Read/Write Default Value: 0000H Bit 15-0 Name Gain Energy calibration gain. Signed integer. Actual power gain = (1+ Gain) Description PhiA Phase A calibration phase angle Address: 48H Type: Read/Write Default Value: 0000H Bit 15 14:10 9:0 Name DelayV DelayCycles 0: Delay Cycles are applied to current channel. (default) 1: Delay Cycles are applied to voltage channel. Reserved. Unit is 2.048MHz cycle. It is an unsigned 10 bit integer. Description The phase B and phase C’s calibration registers are similar as phase A. Register 59 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.4.4 FUNDAMENTAL/HARMONIC ENERGY CALIBRATION REGISTERS Table-7 Fundamental/Harmonic Energy Calibration Registers Register Address 50H 51H 52H 53H 54H 55H 56H 57H Register Name HarmStart POffsetAF POffsetBF POffsetCF PGainAF PGainBF PGainCF CS2 * Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W Functional Description Harmonic Calibration Startup Command Phase A Fundamental Active Power Offset Phase B Fundamental Active Power Offset Phase C Fundamental Active Power Offset Phase A Fundamental Active Power Gain Phase B Fundamental Active Power Gain Phase C Fundamental Active Power Gain Checksum 2 Power-on Value 6886H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Note: The calculation of the CS2 register is similar as the CS0 register by calculating the 51H-56H registers. For details, please refer to IDT application note AN-644. 6.4.5 MEASUREMENT CALIBRATION Table-8 Measurement Calibration Registers Register Address 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH Register Name AdjStart UgainA IgainA UoffsetA IoffsetA UgainB IgainB UoffsetB IoffsetB UgainC IgainC UoffsetC IoffsetC IgainN IoffsetN CS3 * Read/Write Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Functional Description Measurement Calibration Startup Command Phase A Voltage RMS Gain Phase A Current RMS Gain Phase A Voltage RMS Offset Phase A Current RMS Offset Phase B Voltage RMS Gain Phase B Current RMS Gain Phase B Voltage RMS Offset Phase B Current RMS Offset Phase C Voltage RMS Gain Phase C Current RMS Gain Phase C Voltage RMS Offset Phase C Current RMS Offset Sampled N line Current RMS Gain Sampled N line Current RMS Offset Checksum 3 Power-on Value 6886H CE40H 7530H 0000H 0000H CE40H 7530H 0000H 0000H CE40H 7530H 0000H 0000H 7530H 0000H 8EBEH Note: The calculation of the CS3 register is similar as the CS0 register by calculating the 61H-6EH registers. Register 60 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.5 6.5.1 ENERGY REGISTER REGULAR ENERGY REGISTERS Table-9 Regular Energy Registers Register Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 98H 99H Register Name APenergyT APenergyA APenergyB APenergyC ANenergyT ANenergyA ANenergyB ANenergyC RPenergyT RPenergyA RPenergyB RPenergyC RNenergyT RNenergyA RNenergyB RNenergyC SAenergyT SenergyA SenergyB SenergyC SVenergyT EnStatus0 EnStatus1 SVmeanT SVmeanTLSB Read/Write Type R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R R R R Functional Description Total Forward Active Energy Phase A Forward Active Energy Phase B Forward Active Energy Phase C Forward Active Energy Total Reverse Active Energy Phase A Reverse Active Energy Phase B Reverse Active Energy Phase C Reverse Active Energy Total Forward Reactive Energy Phase A Forward Reactive Energy Phase B Forward Reactive Energy Phase C Forward Reactive Energy Total Reverse Reactive Energy Phase A Reverse Reactive Energy Phase B Reverse Reactive Energy Phase C Reverse Reactive Energy Total (Arithmetic Sum) Apparent Energy Phase A Apparent Energy Phase B Apparent Energy Phase C Apparent Energy (Vector Sum) Total Apparent Energy Metering Status 0 Metering Status 1 (Vector Sum) Total Apparent Power LSB of (Vector Sum) Total Apparent Power Complement, MSB is always ‘0’; XX.XXX kVA LSB of SVmeanT. Unit/LSB is 4/65536 VA Resolution is 0.1CF/0.01CF. 0.01CF / 0.1CF setting is defined by the 001LSB bit (b9, MMode0). Cleared after read. Comment Register 61 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC EnStatus0 Metering Status 0 Address: 95H Type: Read Default Value: F000H Bit 15 14 13 12 11-4 3 2 1 0 Name TQNoload TPNoload TASNoload TVSNoload CF4RevFlag CF3RevFlag CF2RevFlag CF1RevFlag all-phase-sum reactive power no-load condition detected. all-phase-sum active power no-load condition detected. all-phase-sum apparent power no-load condition detected. all-phase-sum vectored sum apparent active power no-load condition detected. Reserved. CF4/CF3/CF2/CF1 Forward/Reverse Flag – reflect the direction of the current CF pulse. 0: Forward (default) 1: Reverse Description EnStatus1 Metering Status 1 Address: 96H Type: Read Default Value: 0000H Bit 15-7 6 5 4 3 2 1 0 Name SagPhaseA SagPhaseB SagPhaseC PhaseLossA PhaseLossB PhaseLossC Reserved. These bits indicate whether there is voltage sag on phase A, B or C respectively. 0: no voltage sag (default) 1: voltage sag Reserved. These bits indicate whether there is a phase loss in Phase A/B/C. 0: no phase loss (default) 1: phase loss. Description Register 62 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.5.2 FUNDAMENTAL / HARMONIC ENERGY REGISTER Table-10 Fundamental / Harmonic Energy Register Register Address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH Register Name APenergyTF APenergyAF APenergyBF APenergyCF ANenergyTF ANenergyAF ANenergyBF ANenergyCF APenergyTH APenergyAH APenergyBH APenergyCH ANenergyTH ANenergyAH ANenergyBH ANenergyCH Read/Write Type R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C R/C Functional Description Total Forward Active Fundamental Energy Phase A Forward Active Fundamental Energy Phase B Forward Active Fundamental Energy Phase C Forward Active Fundamental Energy Total Reverse Active Fundamental Energy Phase A Reverse Active Fundamental Energy Phase B Reverse Active Fundamental Energy Phase C Reverse Active Fundamental Energy Total Forward Active Harmonic Energy Phase A Forward Active Harmonic Energy Phase B Forward Active Harmonic Energy Phase C Forward Active Harmonic Energy Total Reverse Active Harmonic Energy Phase A Reverse Active Harmonic Energy Phase B Reverse Active Harmonic Energy Phase C Reverse Active Harmonic Energy Resolution is 0.1CF / 0.01CF. 0.01CF / 0.1CF setting is defined by the 001LSB bit (b9, MMode0). Cleared after read. Comment 6.6 6.6.1 MEASUREMENT REGISTERS POWER AND POWER FACTOR REGISTERS Table-11 Power and Power Factor Register Register Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H Register Name PmeanT PmeanA PmeanB PmeanC QmeanT QmeanA QmeanB QmeanC SAmeanT SmeanA SmeanB SmeanC PFmeanT PFmeanA PFmeanB PFmeanC PmeanTLSB Read/Write Type R R R R R R R R R R R R R R R R R Functional Description Total (all-phase-sum) Active Power Phase A Active Power Phase B Active Power Phase C Active Power Total (all-phase-sum) Reactive Power Phase A Reactive Power Phase B Reactive Power Phase C Reactive Power Total (Arithmetic Sum) apparent power phase A apparent power phase B apparent power phase C apparent power Total power factor phase A power factor phase B power factor phase C power factor Lower word of Total (all-phase-sum) Active Power Comment Complement, MSB as the sign bit XX.XXX kW 1LSB corresponds to 1Watt for phase A/B/C, and 4Watt for Total (all-phase-sum) Complement, MSB as the sign bit XX.XXX kvar 1LSB corresponds to 1var for phase A/B/C, and 4var for Total (all-phase-sum) Complement, MSB always '0' XX.XXX kVA 1LSB corresponds to 1va for phase A/B/C, and 4va for Total (all-phase-sum) Signed, MSB as the sign bit X.XXX LSB is 0.001. Range from -1000 to +1000 Lower word of Active Powers. 1LLSB corresponds to 4/256 Watt * Register 63 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-11 Power and Power Factor Register Register Address C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH Register Name PmeanALSB PmeanBLSB PmeanCLSB QmeanTLSB QmeanALSB QmeanBLSB QmeanCLSB SAmeanTLSB SmeanALSB SmeanBLSB SmeanCLSB Read/Write Type R R R R R R R R R R R Functional Description Lower word of Phase A Active Power Lower word of Phase B Active Power Lower word of Phase C Active Power Lower word of Total (all-phase-sum) Reactive Power Lower word of Phase A Reactive Power Lower word of Phase B Reactive Power Lower word of Phase C Reactive Power Lower word of Total (Arithmetic Sum) apparent power Lower word of phase A apparent power Lower word of phase B apparent power Lower word of phase C apparent power Comment Lower word of Active Powers. 1LLSB corresponds to 1/256 Watt Lower word of ReActive Powers. 1LLSB corresponds to 4/256 var Lower word of ReActive Powers. 1LLSB corresponds to 1/256 var Lower word of Apparent Powers. 1LLSB corresponds to 4/256 VA Lower word of Apparent Powers. 1LLSB corresponds to 1/256 VA Note: All the lower 8 bits of C0H-CBH registers and E0H-EFH registers are always zero. Only the higher 8 bits of these registers are valid. In this document, LLSB means bit 8 of the lower registers as below: b15 b14 b13 b12 b11 b10 b9 b8 (LLSB) b7 b6 b5 b4 b3 b2 b1 b0 6.6.2 FUNDAMENTAL/ HARMONIC POWER AND VOLTAGE/ CURRENT RMS REGISTERS Table-12 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers Register Address D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H Register Name PmeanTF PmeanAF PmeanBF PmeanCF PmeanTH PmeanAH PmeanBH PmeanCH IrmsN1 UrmsA UrmsB UrmsC IrmsN0 IrmsA IrmsB IrmsC PmeanTFLSB Read/Write Type R R R R R R R R R R R R R R R R R Functional Description Total active fundamental power phase A active fundamental power phase B active fundamental power phase C active fundamental power Total active harmonic power phase A active harmonic power phase B active harmonic power phase C active harmonic power N Line Sampled current RMS phase A voltage RMS phase B voltage RMS phase C voltage RMS N Line calculated current RMS phase A current RMS phase B current RMS phase C current RMS Lower word of Total active fundamental Power Lower word of D0H register. 1LLSB corresponds to 4/256 Watt * Comment Complement, 16-bit integer with unit of 4Watt. 1LSB corresponds to 4Watt Complement, 16-bit integer with unit of 1Watt. 1LSB corresponds to 1Watt Complement, 16-bit integer with unit of 4Watt. 1LSB corresponds to 4Watt Complement, 16-bit integer with unit of 1Watt. 1LSB corresponds to 1Watt unsigned 16-bit integer with unit of 0.001A 1LSB corresponds to 0.001 A 1LSB corresponds to 0.01 V unsigned 16-bit integer with unit of 0.001A 1LSB corresponds to 0.001 A Register 64 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-12 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers Register Address E1H E2H E3H E4H E5H E6H E7H E9H EAH EBH EDH EEH EFH Register Name PmeanAFLSB PmeanBFLSB PmeanCFLSB PmeanTHLSB PmeanAHLSB PmeanBHLSB PmeanCHLSB UrmsALSB UrmsBLSB UrmsCLSB IrmsALSB IrmsBLSB IrmsCLSB Read/Write Type R R R R R R R R R R R R R Functional Description Lower word of phase A active fundamental Power Lower word of phase B active fundamental Power Lower word of phase C active fundamental Power Lower word of Total active harmonic Power Lower word of phase A active harmonic Power Lower word of phase B active harmonic Power Lower word of phase C active harmonic Power Lower word of phase A voltage RMS Lower word of phase B voltage RMS Lower word of phase C voltage RMS Lower word of phase A current RMS Lower word of phase B current RMS Lower word of phase C current RMS Lower word of D4H register. 1LLSB corresponds to 4/256 Watt Lower word of registers from D5H to D7H. 1LLSB corresponds to 1/256 Watt Lower word of registers from D9H to DBH. 1LLSB corresponds to 0.01/256V Lower word of registers from DDH to DFH. 1LLSB corresponds to 0.001/256A Lower word of registers from D1H to D3H. 1LLSB corresponds to 1/256 Watt Comment Note: All the lower 8 bits of C0H-CBH registers and E0H-EFH registers are always zero. Only the higher 8 bits of these registers are valid. In this document, LLSB means bit 8 of the lower registers as below: b15 b14 b13 b12 b11 b10 b9 b8 (LLSB) b7 b6 b5 b4 b3 b2 b1 b0 6.6.3 THD+N, FREQUENCY, ANGLE AND TEMPERATURE REGISTERS Table-13 THD+N, Frequency, Angle and Temperature Registers Register Address F1H F2H F3H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Register Name THDNUA THDNUB THDNUC THDNIA THDNIB THDNIC Freq PAngleA PAngleB PAngleC Temp UangleA UangleB UangleC Read/Write Type R R R R R R R R R R R R R R Functional Description phase A voltage THD+N phase B voltage THD+N phase C voltage THD+N phase A current THD+N phase B current THD+N phase C current THD+N Frequency phase A mean phase angle phase B mean phase angle phase C mean phase angle Measured temperature phase A voltage phase angle phase B voltage phase angle phase C voltage phase angle 1LSB corresponds to 0.01% Hz Signed, MSB as the sign bit 1LSB corresponds to 0.1-degree, -180.0°~+180.0° 1LSB corresponds to 1 °C Signed, MSB as the sign bit Always ‘0’ Signed, MSB as the sign bit Take phase A voltage as base voltage 1LSB corresponds to 0.1 degree, -180.0°~+180.0° 1LSB corresponds to 0.01% 1LSB corresponds to 0.01% Comment Register 65 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.7 HARMONIC FOURIER ANALYSIS REGISTERS Table-14 Harmonic Fourier Analysis Results Registers Register Address 100H 101H 102H … 11EH 11FH 120H 121H 122H … 13EH 13FH 140H 141H 142H … 15EH 15FH 160H 161H 162H … 17EH 17FH AV_HR32 AV_THD CI_HR32 CI_THD AV_HR2 AV_HR3 AV_HR4 BI_HR32 BI_THD CI_HR2 CI_HR3 CI_HR4 AI_HR32 AI_THD BI_HR2 BI_HR3 BI_HR4 Register Name AI_HR2 AI_HR3 AI_HR4 Read/Write Type R R R R R R R R R R R R R R R R R R R R R R R R phase A, Voltage, Harmonic Ratio for 32-th order component phase A, Voltage, Total Harmonic Distortion Ratio phase C, Current, Harmonic Ratio for 32-th order component phase C, Current, Total Harmonic Distortion Ratio phase A, Voltage, Harmonic Ratio for 2-th order component phase A, Voltage, Harmonic Ratio for 3-th order component phase A, Voltage, Harmonic Ratio for 4-th order component Harmonic Ratio (%) = Register Value / 163.84 phase B, Current, Harmonic Ratio for 32-th order component phase B, Current, Total Harmonic Distortion Ratio phase C, Current, Harmonic Ratio for 2-th order component phase C, Current, Harmonic Ratio for 3-th order component phase C, Current, Harmonic Ratio for 4-th order component Harmonic Ratio (%) = Register Value / 163.84 phase A, Current, Harmonic Ratio for 32-th order component phase A, Current, Total Harmonic Distortion Ratio phase B, Current, Harmonic Ratio for 2-th order component phase B, Current, Harmonic Ratio for 3-th order component phase B, Current, Harmonic Ratio for 4-th order component Harmonic Ratio (%) = Register Value / 163.84 Functional Description phase A, Current, Harmonic Ratio for 2-th order component phase A, Current, Harmonic Ratio for 3-th order component phase A, Current, Harmonic Ratio for 4-th order component Harmonic Ratio (%) = Register Value / 163.84 Comment Register 66 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-14 Harmonic Fourier Analysis Results Registers Register Address 180H 181H 182H … 19EH 19FH 1A0H 1A1H 1A2H … 1BEH 1BFH 1C0H 1C1H 1C2H 1C3H 1C4H 1C5H CV_HR32 CV_THD AI_FUND AV_FUND BI_FUND BV_FUND CI_FUND CV_FUND BV_HR32 BV_THD CV_HR2 CV_HR3 CV_HR4 Register Name BV_HR2 BV_HR3 BV_HR4 Read/Write Type R R R R R R R R R R R R R R R R R R phase C, Voltage, Harmonic Ratio for 32-th order component phase C, Voltage, Total Harmonic Distortion Ratio phase A, Current, Fundamental component value phase A, Voltage, Fundamental component value phase B, Current, Fundamental component value phase B, Voltage, Fundamental component value phase C, Current, Fundamental component value phase C, Voltage, Fundamental component value Input Gain = 2^Scale, i.e. Scale = # of bit shifts [2:0]: Scale for Channel A-I. [5:3]: Scale for Channel B-I. [8:6]: Scale for Channel C-I. [10:9]: Scale for Channel A-V. [12:11]: Scale for Channel B-V. [14:13]: Scale for Channel C-V. [15]: Window disable. ‘1’ disable the Hanning window. Bit[0]: DFT_START. 0: Reset and abort the DFT computation. 1: Start the DFT. This bit is automatically cleared after DFT finishes. Current, Fundamental component value = Register Value * 3.2656*10 / 2^scale, Register (1C0H, 1C2H, 1C4H); Voltage, Fundamental component value = Register Value * 3.2656*10 / 2^scale, Register (1C1H, 1C3H, 1C5H). The scale is defined by the DFT_SCALE (1D0H) register. -2 -3 Functional Description phase B, Voltage, Harmonic Ratio for 2-th order component phase B, Voltage, Harmonic Ratio for 3-th order component phase B, Voltage, Harmonic Ratio for 4-th order component phase B, Voltage, Harmonic Ratio for 32-th order component phase B, Voltage, Total Harmonic Distortion Ratio phase C, Voltage, Harmonic Ratio for 2-th order component phase C, Voltage, Harmonic Ratio for 3-th order component phase C, Voltage, Harmonic Ratio for 4-th order component Comment Harmonic Ratio (%) = Register Value / 163.84 Harmonic Ratio (%) = Register Value / 163.84 1D0H DFT_SCALE RW Input data is scaled before sampling or DFT. 1D1H DFT_CTRL RW Register 67 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7 7.1 ELECTRICAL SPECIFICATION ELECTRICAL SPECIFICATION Parameter Min Typ Max Accuracy ±0.1 Unit Test Condition/ Comments VDD=3.3V±0.3V, I=5A, V=220V, CT 1000:1, sampling resistor 4.8Ω VDD=3.3V superimposes 400mVrms, I=5A, V=220V, CT 1000:1, sampling resistor 4.8Ω CT 1000:1, sampling resistor 4.8Ω PGA=1 PGA=2 PGA=4 DC Power Supply Rejection Ratio (PSRR) AC Power Supply Rejection Ratio (PSRR) Active Energy Error (Dynamic Range 6000:1) % Differential Input Voltage Analog Input Pin Absolute Voltage Range Channel Input Impedance Channel Sampling Frequency Channel Sampling Bandwidth Temperature Sensor Accuracy Reference voltage Reference voltage temperature coefficient Current Detector threshold range Current Detector threshold setting step/ resolution Current Detector detection time (single-side) Current Detector detection time (double-side) Oscillator Frequency (fsys_clk) AVDD DVDD VDD18 Normal mode operating current (I-Normal) Normal mode operating current with DFT engine on (I-Normal + DFT) Idle mode operating current (I-Idle) Detection mode operating current (I-Detection) Partial Measurement mode operating current (I-Measurement) Slave mode (SPI) bit rate Master mode (DMA) bit rate Machine Model (MM) Charged Device Model (CDM) Human Body Model (HBM) Latch Up Latch Up ±0.1 % ±0.1 % ADC Channel 0.12 720 0.07 360 mVrms 0.04 180 VDDGND-300 mV 1200 120 KΩ 80 50 8 kHz 2 kHz Temperature Sensor and Reference 1 °C 1.2 ppm/ 6 15 °C Current detectors 2 3 4 mVrms 0.096 mVrms 32 ms 17 ms Crystal Oscillator 16.384 2.8 2.8 Power Supply 3.3 3.6 3.3 3.6 1.8 Operating Currents 25 25.5 2.2 180 100 6.8 SPI 100 ESD 400 1000 6000 ±100 5.4 V V V mA V 1200k 1800k note 1 PGA=1 PGA=2 PGA=4 3.3 V, 25 °C From -40 to 85 °C 3.3 V, 25 °C 3.3 V, 25 °C MHz The Accuracy of crystal or external clock is ±20 ppm, 10pF ~ 20pF crystal load capacitor integrated. V mA mA µA µA mA bps bps JESD22-A115 JESD22-C101 JESD22-A114 JESD78A JESD78A 3.3 V, 25 °C 3.3 V, 25 °C 3.3 V, 25 °C Double-side detection (at 3.3 V, 25 °C) Single-side detection (at 3.3 V, 25 °C) 3.3 V, 25°C 10 250 140 Electrical Specification 68 December 9, 2011 90E36 Parameter Min POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Typ Max DC Characteristics VDD 0.8 ±1 0.4 0.4 Unit V V µA V V V V Test Condition/ Comments VDD=3.3V VDD=3.3V VDD=3.6V, VI=VDD or GND VDD=3.3V, IOL=8mA VDD=3.3V, IOL=5mA VDD=3.3V, IOH=-8mA, by separately VDD=3.3V, IOH=-5mA, by separately Digital Input High Level (all digital pins except OSCI) 2.4 Digital Input Low Level (all digital pins except OSCI) Digital Input Leakage Current Digital Output Low Level (CF1, CF2, CF3, CF4) Digital Output Low Level (IRQ0, IRQ1, WarnOut, ZX0, ZX1, ZX2, SDO) Digital Output High Level (CF1, CF2, CF3, CF4) 2.8 Digital Output High Level (IRQ0, IRQ1, WarnOut, ZX0, ZX1, ZX2, SDO) 2.8 Note 1: The maximum SPI bit rate during current detector calibration is 900k bps. Electrical Specification 69 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.2 7.2.1 METERING/ MEASUREMENT ACCURACY METERING ACCURACY γ= Metering accuracy or energy accuracy is calculated with relative error: E mea − E real × 100% E real Where Emea is the energy measured by the meter, Ereal is the actual energy measured by a high accurate normative meter. Table-15 Metering Accuracy for Different Energy within the Dynamic Range Energy Type Active energy (Per phase and all-phase-sum) Reactive energy (Per phase and all-phase-sum) Apparent energy (Per phase and arithmetic all-phase-sum) Apparent energy (Vector sum) Fundamental active energy (Per phase and all-phase-sum) Harmonic active energy (Per phase and all-phase-sum) Energy Pulse CF1 ADC Range When Gain=1 PF=1.0 120µV-720mV PF=0.5L, 180µV-720mV PF=0.8C, 150µV-720mV sinФ=1.0 120µV-720mV sinФ=0.5L, 180µV-720mV sinФ=0.8C, 150µV-720mV 600µV-720mV note 2 Metering Accuracy 0.1% note 1 CF2 CF2 CF2 CF3 0.2% 0.2% 0.5% 0.2% CF4 Note 1: All the parameters in this table is tested on IDT’s test platform. Note 2: Apparent energy is tested using active energy with unity power factor since there’s no standard for apparent energy. Signal below 600 µV is not tested. 120µV-720mV PF=1.0 120µV-720mV PF=0.5L, 180µV-720mV PF=0.8C, 150µV-720mV PF=1.0 120µV-720mV PF=0.5L, 180µV-720mV PF=0.8C, 150µV-720mV 0.5% Electrical Specification 70 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.2.2 MEASUREMENT ACCURACY The measurements are all calculated with fiducial error except for frequency and THD. Fiducial error is calculated as follows: Where Umea means the measured data of one measurement parameter, and Ureal means the real/actual data of the parameter, UFV means the fiducial value of this measurement parameter, which can be defined as Table-16. Fiducial_Error = Umea - Ureal * 100% UFV Table-16 Measurement Parameter Range and Format 90E36 Defined Measurement Voltage Current Voltage rms Current rms note 1 note 1 Fiducial Value (FV) reference voltage Un maximum current Imax (4×In is recommended) Un Ib/In Un×4Ib Un×4Ib Reference Frequency 50 Hz 1.000 180º Relative error is adopted, no Fiducial Value Format XXX.XX XX.XXX XXX.XX XX.XXX XX.XXX XX.XXX XX.XX X.XXX XXX.X XX.XX Range 0 ~ 655.35V 0 ~ 65.535A 0 ~ 655.35V 0 ~ 65.535A -32.768 ~ +32.767 kW/kvar 0 ~ +32.767 kVA 45.00~65.00 Hz -1.000 ~ +1.000 -180º ~ +180º 0.00%-99.99% Comment Unsigned integer with unit of 0.01V Unsigned integer with unit of 0.001A Unsigned integer with unit of 0.01V Unsigned integer with unit of 0.001A Signed integer with unit/LSB of 1 Watt/var Unsigned integer with unit/LSB of 1 VA Signed integer with unit/LSB of 0.01Hz Signed integer, LSB/Unit = 0.001 Signed integer, unit/LSB = 0.1º Unit is 0.01% Active/ Reactive Power Apparent Power Frequency Power Factor Phase Angle THD+N note 2 THD 0.00%-399% Arithmetic ratio, 2 bit integer and 14 bit fractional. Harmonic Component 0.00%-399% Note 1: All registers are of 16-bit. For cases when the current or active/reactive/apparent power goes beyond the above range, it is suggested to be handled by MCU in application. For example, register value can be calibrated to 1/2 of the actual value during calibration, then multiply 2 in application. Note 2: Phase angle is obtained when voltage/current crosses zero at the sampling frequency of 256kHz. For the above mentioned parameters, the measurement accuracy requirement is 0.5% maximum. For frequency, temperature, THD+N, THD and Harmonic analysis: Parameter Accuracy Frequency: 0.01Hz Temperature: 1 °C THD/Harmonics: 5% relative error Accuracy of all orders of harmonics: 5% relative error Harmonic component% = Where u(i)h − u(i)hN × 100 u(i)hN u (i ) h means the measuring value of the hth harmonic voltage/ current; u (i ) hN current. means the given or actual value of the h harmonic voltage/ th Electrical Specification 71 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.3 7.3.1 INTERFACE TIMING SPI INTERFACE TIMING (SLAVE MODE) The SPI interface timing is as shown in Figure-23 and Table-17. t t CSH CS t CYC CSS t CLH t t CLL CSD t CLD SCLK t DIS t DIH SDI Valid Input t DW t PD Valid Output t DF High Impedance SDO High Impedance Figure-23 SPI Timing Diagram Table-17 SPI Timing Specification Symbol tCSH tCSS tCSD tCLD tCYC tCLH tCLL tDIS tDIH tDW tPD tDF Description Minimum CS High Level Time CS Setup Time CS Hold Time Clock Disable Time SCLK cycle Clock High Level Time Clock Low Level Time Data Setup Time Data Hold Time Minimum Data Width Output Delay Output Disable Time Min. +10 2T 2T+10 3T+10 1T 7T+10 5T+10 2T+10 2T+10 1T+10 3T+10 2T+20 2T+20 note 1 Typical Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. T means system clock cycle. T=1/fsys_clk Electrical Specification 72 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.3.2 DMA TIMING (MASTER MODE) The DMA timing is as shown in Figure-24 and Table-18. SCLK (CLK_IDLE=0) SCLK (CLK_IDLE=1) SDI/SDO tPD CS Figure-24 DMA Timing Diagram Table-18 DMA Timing Specification Symbol tPD Description Output Delay Min. Typical Max. 50 Unit ns Electrical Specification 73 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.4 POWER ON RESET TIMING In this operation, RESET is held to high in idle mode and de-asserted by delay T1 after idle-normal transition. Refer to Figure-25. In most case, the power of 90E36 and MCU are both derived from 220V power lines. To make sure 90E36 is reset and can work properly, MCU must force 90E36 into idle mode firstly and then into normal mode. DVDD T0 PM[1:0] MCU startup Idle Mode T1 RESET Figure-25 Power On Reset Timing (90E36 and MCU are Powered on Simultaneously) Normal Mode VH DVDD T1 RESET Figure-26 Power On Reset Timing in Normal & Partial Measurement Mode Table-19 Power On Reset Specification Symbol VH T0 T1 Description Power On Trigger Voltage Duration forced in idle mode after power on Delay time after power on or exit idle mode Min 1 5 Typ 2.5 16 Max 2.7 40 Unit V ms ms Electrical Specification 74 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.5 ZERO-CROSSING TIMING V TZX ZX (Positive zero-crossing) TD ZX (Negative zero-crossing) ZX (All zero-crossing) Figure-27 Zero-Crossing Timing Diagram (per phase) Table-20 Zero-Crossing Specification Symbol TZX TD Description High Level Width Delay Time Min Typ 5 0.2 Max 0.5 Unit ms ms Electrical Specification 75 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.6 VOLTAGE SAG AND PHASE LOSS TIMING Voltage + threshold time - threshold 11ms window Sag/Phase Loss condition found in two consecutive windows IRQ (if enabled) Assert of Voltage Sag / Phase Loss Figure-28 Voltage Sag and Phase Loss Timing Diagram Electrical Specification 76 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.7 ABSOLUTE MAXIMUM RATING Parameter Relative Voltage Between AVDD and AGND Relative Voltage Between DVDD and DGND Analog Input Voltage (I1P, I1N, I2P, I2N, I3P, I3N, I4P, I4N, V1P, V1N, V2P, V2N, V3P, V3N) Digital Input Voltage Operating Temperature Range Maximum Junction Temperature Package Type TQFP48 Thermal Resistance θJA 41 Unit °C/W Maximum Limit -0.3V~3.7V -0.3V~3.7V -0.6V~AVDD -0.3V~3.6V -40~85 °C 150 °C Condition No Airflow Electrical Specification 77 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PACKAGE DIMENSIONS 78 December 9, 2011 90E36 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ORDERING INFORMATION XXXXX Device Type XXX Package X Temperature Range I Industry (-40 ℃ to +85 ℃) ERG TQFP48 90E36 Poly-Phase High-Performance Wide-Span Energy Metering IC DATASHEET DOCUMENT HISTORY 12/9/2011 Pages. 23, 37, 38, 42, 52, 64, 65, 67, 69, 78 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com 79 for Sales: 86-21-64958900 for Tech Support: 86-21-64958900 email:powermeterhelp@idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.