92HD66B

DATASHEET FOUR CHANNEL HD AUDIO CODECS DUAL CAPLESS HEADPHONE AMPLIFIERS 92HD66B SOFTWARE SUPPORT • • Intuitive IDT HD Sound graphical user interface that allows configurability and preference settings 12 band fully parametric equalizer • Constant, system-level effects tuned to optimize a particular platform can be combined with user-mode “presets” tailored for specific acoustical environments and applications System-level effects automatically disabled when external audio connections made Enables improved voice articulation Compressor/limiter allows higher average volume level without resonances or damage to speakers. Enables multiple APOs to be used with the IDT Driver DESCRIPTION The 92HD66B is a low power optimized, high fidelity, 4-channel audio codec compatible with Intel’s High Definition (HD) Audio Interface. The 92HD66B provides high quality, HD Audio capability to notebook and desktop PC applications. • FEATURES • • 4 Channels (2 stereo ADCs) with 24-bit resolution Full HDA015-B and EuP low power support • • • • • • Audio inactivity transitions codec from D0 to D3 low power mode Resume from D3 to D0 with audio activity in < 10 msec D3 to D0 transition with < -65dB pop/click Port presence detect in D3 with or without bit clock PC beep wake up in D3 Additional vendor specific modes for even lower power • Dynamics Processing • • • • • IDT Vista APO wrapper • Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression Dynamic Stream Switching • Improved multi-streaming user experience with less support calls • • • • • • • • • • • • • • Microsoft WLP premium logo compliant 4 or 5 analog ports with port presence detect* 3 integrated headphone amplifiers 2 Capless headphone amplifiers 3 or 4 ports support adjustable microphone bias* Dual SPDIF outputs for WLP compliant support of simultaneous HDMI and SPDIF output SPDIF Input Two digital microphone inputs (mono, stereo or quad) High performance analog mixer Support for 1.5V and 3.3V HDA signaling Integrated AVDD LDO for improved PSRR +5V or +3.3V analog power supply Digital and Analog PC Beep to all outputs 48-pin or 40-pin QFN RoHS packages • Broad 3rd party branded software including Creative, Dolby, DTS, and SRS DEVICE OPTIONS • • 4 Channel, 48-pin QFN package 4 Channel, 40-pin QFN package • *40-pin package removes • • • Port E and related VREF_Out Mono Out GPIO 4 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS TABLE OF CONTENTS DESCRIPTION 10 Overview 10 Orderable Part Numbers 10 DETAILED DESCRIPTION 11 Port Functionality 11 Port Characteristics 11 Vref_Out 12 Jack Detect 12 SPDIF Output 13 SPDIF Input 15 Mono Output 16 Analog Mixer 16 ADC Multiplexers 16 Power Management 17 AFG D0 18 AFG D1 18 AFG D2 18 AFG D3 18 AFG D3cold 18 Vendor Specific Function Group Power States D4/D5 19 Vendor Specific Function Group Power State “D5 Kill” 19 Low-voltage HDA Signaling 19 Multi-channel capture 19 EAPD 21 Digital Microphone Support 24 Analog PC-Beep 28 PC_Beep Activity Monitor 29 Digital PC-Beep 31 Headphone Drivers 32 GPIO 32 GPIO Pin mapping and shared functions 32 Digital Microphone/GPIO Selection 32 SPDIF_OUT/GPIO/DMIC Selection 33 HD Audio ECR 15b support 33 Digital Core Voltage Regulator 34 Analog Core Voltage Regulator 34 Combo Jack 34 CHARACTERISTICS 35 Audio Fidelity 35 Electrical Specifications 35 Absolute Maximum Ratings 35 Recommended Operating Conditions 35 92HD66B Analog Performance Characteristics 36 Capless Headphone Supply Characteristics 41 AC Timing Specs 41 HD Audio Bus Timing 41 SPDIF Timing 42 Digital Microphone Timing 42 GPIO Characteristics 42 COMMON PORT CONFIGURATIONS 43 FUNCTIONAL DIAGRAMS 44 48-pin Package 44 40-pin Package 45 48-pin Package Widget Diagram 46 40-pin Package Widget Diagram 47 48-Pin Configuration Default Register Settings 48 40-Pin Configuration Default Register Settings 49 2 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS WIDGET INFORMATION 50 Widget List 50 Widget Descriptions 51 Widget Details 51 Device IDs 51 Reset Key 52 Root (NID = 00h): VendorID 52 Root (NID = 00h): RevID 53 Root (NID = 00h): NodeInfo 53 AFG (NID = 01h): NodeInfo 54 AFG (NID = 01h): FGType 54 AFG (NID = 01h): AFGCap 55 AFG (NID = 01h): PCMCap 56 AFG (NID = 01h): StreamCap 57 AFG (NID = 01h): InAmpCap 58 AFG (NID = 01h): PwrStateCap 59 AFG (NID = 01h): GPIOCnt 60 AFG (NID = 01h): OutAmpCap 60 AFG (NID = 01h): PwrState 61 AFG (NID = 01h): UnsolResp 62 AFG (NID = 01h): GPIO 62 AFG (NID = 01h): GPIOEn 63 AFG (NID = 01h): GPIODir 64 AFG (NID = 01h): GPIOWakeEn 65 AFG (NID = 01h): GPIOUnsol 66 AFG (NID = 01h): GPIOSticky 67 AFG (NID = 01h): SubID 67 AFG (NID = 01h): GPIOPlrty 68 AFG (NID = 01h): GPIODrive 69 AFG (NID = 01h): DMic 70 AFG (NID = 01h): DACMode 71 AFG (NID = 01h): ADCMode 72 AFG (NID = 01h): PortUse 73 AFG (NID = 01h): ComJack 74 AFG (NID = 01h): ComJackTime 75 AFG (NID = 01h): VSPwrState 77 AFG (NID = 01h): AnaPort 77 AFG (NID = 01h): AnaBeep 79 AFG (NID = 01h): AnaCapless 79 AFG (NID = 01h): Reset 82 PortA (NID = 0Ah): WCap 83 PortA (NID = 0Ah): PinCap 84 PortA (NID = 0Ah): ConLst 85 PortA (NID = 0Ah): ConLstEntry0 86 PortA (NID = 0Ah): InAmpLeft 86 PortA (NID = 0Ah): InAmpRight 87 PortA (NID = 0Ah): ConSelectCtrl 87 PortA (NID = 0Ah): PwrState 88 PortA (NID = 0Ah): PinWCntrl 88 PortA (NID = 0Ah): UnsolResp 89 PortA (NID = 0Ah): ChSense 90 PortA (NID = 0Ah): EAPDBTLLR 90 PortA (NID = 0Ah): ConfigDefault 91 PortB (NID = 0Bh): WCap 93 PortB (NID = 0Bh): PinCap 95 PortB (NID = 0Bh): ConLst 96 PortB (NID = 0Bh): ConLstEntry0 97 PortB (NID = 0Bh): InAmpLeft 97 PortB (NID = 0Bh): InAmpRight 98 3 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS PortB (NID = 0Bh): ConSelectCtrl 98 PortB (NID = 0Bh): PwrState 98 PortB (NID = 0Bh): PinWCntrl 99 PortB (NID = 0Bh): UnsolResp 100 PortB (NID = 0Bh): ChSense 101 PortB (NID = 0Bh): EAPDBTLLR 101 PortB (NID = 0Bh): ConfigDefault 101 PortC (NID = 0Ch): WCap 104 PortC (NID = 0Ch): PinCap 105 PortC (NID = 0Ch): ConLst 106 PortC (NID = 0Ch): ConLstEntry0 107 PortC (NID = 0Ch): InAmpLeft 107 PortC (NID = 0Ch): InAmpRight 108 PortC (NID = 0Ch): ConSelectCtrl 108 PortC (NID = 0Ch): PwrState 109 PortC (NID = 0Ch): PinWCntrl 109 PortC (NID = 0Ch): UnsolResp 110 PortC (NID = 0Ch): ChSense 111 PortC (NID = 0Ch): EAPDBTLLR 111 PortC (NID = 0Ch): ConfigDefault 112 NID = 0Dh Reserved 114 PortE (NID = 0Eh): WCap (Available only on 48-pin versions) 114 PortE (NID = 0Eh): PinCap (Available only on 48-pin versions) 116 PortE (NID = 0Eh): ConLst (Available only on 48-pin versions) 117 PortE (NID = 0Eh): ConLstEntry0 (Available only on 48-pin versions) 118 PortE (NID = 0Eh): InAmpLeft (Available only on 48-pin versions) 118 PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions) 118 PortE (NID = 0Eh): ConSelectCtrl (Available only on 48-pin versions) 119 PortE (NID = 0Eh): PwrState (Available only on 48-pin versions) 119 PortE (NID = 0Eh): PinWCntrl (Available only on 48-pin versions) 120 PortE (NID = 0Eh): UnsolResp (Available only on 48-pin versions) 121 PortE (NID = 0Eh): ChSense (Available only on 48-pin versions) 121 PortE (NID = 0Eh): EAPDBTLLR (Available only on 48-pin versions) 122 PortE (NID = 0Eh): ConfigDefault (Available only on 48-pin versions) 122 PortF (NID = 0Fh): WCap 125 PortF (NID = 0Fh): PinCap 126 PortF (NID = 0Fh): ConLst 127 PortF (NID = 0Fh): ConLstEntry0 128 PortF (NID = 0Fh): InAmpLeft 128 PortF (NID = 0Fh): InAmpRight 129 PortF (NID = 0Fh): ConSelectCtrl 129 PortF (NID = 0Fh): PwrState 130 PortF (NID = 0Fh): PinWCntrl 130 PortF (NID = 0Fh): UnsolResp 131 PortF (NID = 0Fh): ChSense 132 PortF (NID = 0Fh): EAPDBTLLR 132 PortF (NID = 0Fh): ConfigDefault 132 MonoOut (NID = 10h): WCap (Available only on 48-pin versions) 135 MonoOut (NID = 10h): PinCap (Available only on 48-pin versions) 136 MonoOut (NID = 10h): ConLst (Available only on 48-pin versions) 137 MonoOut (NID = 10h): ConLstEntry0 (Available only on 48-pin versions) 138 MonoOut (NID = 10h): PwrState (Available only on 48-pin versions) 138 MonoOut (NID = 10h): PinWCntrl (Available only on 48-pin versions) 139 MonoOut (NID = 10h): UnsolResp (Available only on 48-pin versions) 140 MonoOut (NID = 10h): ChSense (Available only on 48-pin versions) 140 MonoOut (NID = 10h): ConfigDefault (Available only on 48-pin versions) 141 DMic0 (NID = 11h): WCap 143 DMic0 (NID = 11h): PinCap 145 DMic0 (NID = 11h): InAmpLeft 146 4 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS DMic0 (NID = 11h): InAmpRight 146 DMic0 (NID = 11h): PwrState 147 DMic0 (NID = 11h): PinWCntrl 148 DMic0 (NID = 11h): ConfigDefault 148 DMic1Vol (NID = 12h): WCap 151 DMic1Vol (NID = 12h): ConLst 152 DMic1Vol (NID = 12h): ConLstEntry0 153 DMic1Vol (NID = 12h): InAmpLeft 153 DMic1Vol (NID = 12h): InAmpRight 153 DMic1Vol (NID = 12h): ConSelectCtrl 154 DMic1Vol (NID = 12h): PwrState 154 DAC0 (NID = 13h): WCap 155 DAC0 (NID = 13h): Cnvtr 157 DAC0 (NID = 13h): OutAmpLeft 158 DAC0 (NID = 13h): OutAmpRight 158 DAC0 (NID = 13h): PwrState 159 DAC0 (NID = 13h): CnvtrID 160 DAC0 (NID = 13h): EAPDBTLLR 160 DAC1 (NID = 14h): WCap 161 DAC1 (NID = 14h): Cnvtr 162 DAC1 (NID = 14h): OutAmpLeft 163 DAC1 (NID = 14h): OutAmpRight 164 DAC1 (NID = 14h): PwrState 164 DAC1 (NID = 14h): CnvtrID 165 DAC1 (NID = 14h): EAPDBTLLR 166 ADC0 (NID = 15h): WCap 166 ADC0 (NID = 15h): ConLst 168 ADC0 (NID = 15h): ConLstEntry0 168 ADC0 (NID = 15h): Cnvtr 169 ADC0 (NID = 15h): ProcState 170 ADC0 (NID = 15h): PwrState 170 ADC0 (NID = 15h): CnvtrID 171 ADC1 (NID = 1Bh): WCap 172 ADC1 (NID = 1Bh): ConLst 173 ADC1 (NID = 1Bh): ConLstEntry0 174 ADC1 (NID = 1Bh): Cnvtr 174 ADC1 (NID = 1Bh): ProcState 176 ADC1 (NID = 1Bh): PwrState 176 ADC1 (NID = 1Bh): CnvtrID 177 ADC0Mux (NID = 17h): WCap 177 ADC0Mux (NID = 17h): ConLst 179 ADC0Mux (NID = 17h): ConLstEntry4 179 ADC0Mux (NID = 17h): ConLstEntry0 180 ADC0Mux (NID = 17h): OutAmpCap 180 ADC0Mux (NID = 17h): OutAmpLeft 181 ADC0Mux (NID = 17h): OutAmpRight 182 ADC0Mux (NID = 17h): ConSelectCtrl 182 ADC0Mux (NID = 17h): PwrState 183 ADC0Mux (NID = 17h): EAPDBTLLR 183 ADC1Mux (NID = 18h): WCap 184 ADC1Mux (NID = 18h): ConLst 185 ADC1Mux (NID = 18h): ConLstEntry4 186 ADC1Mux (NID = 18h): ConLstEntry0 186 ADC1Mux (NID = 18h): OutAmpCap 187 ADC1Mux (NID = 18h): OutAmpLeft 188 ADC1Mux (NID = 18h): OutAmpRight 188 ADC1Mux (NID = 18h): ConSelectCtrl 189 ADC1Mux (NID = 18h): PwrState 189 ADC1Mux (NID = 18h): EAPDBTLLR 190 5 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS MonoMux (NID = 19h): WCap (Available only on 48-pin versions) 190 MonoMux (NID = 19h): ConLst (Available only on 48-pin versions) 192 MonoMux (NID = 19h): ConLstEntry0 (Available only on 48-pin versions) 192 MonoMux (NID = 19h): ConSelectCtrl (Available only on 48-pin versions) 193 MonoMux (NID = 19h): PwrState (Available only on 48-pin versions) 193 MonoMix (NID = 1Ah): WCap (Available only on 48-pin versions) 194 MonoMix (NID = 1Ah): ConLst (Available only on 48-pin versions) 196 MonoMix (NID = 1Ah): ConLstEntry0 (Available only on 48-pin versions) 196 MonoMix (NID = 1Ah): PwrState (Available only on 48-pin versions) 197 Mixer (NID = 1Bh): WCap 198 Mixer (NID = 1Bh): InAmpCap 199 Mixer (NID = 1Bh): ConLst 200 Mixer (NID = 1Bh): ConLstEntry4 201 Mixer (NID = 1Bh): ConLstEntry0 201 Mixer (NID = 1Bh): InAmpLeft0 202 Mixer (NID = 1Bh): InAmpRight0 202 Mixer (NID = 1Bh): InAmpLeft1 203 Mixer (NID = 1Bh): InAmpRight1 203 Mixer (NID = 1Bh): InAmpLeft2 204 Mixer (NID = 1Bh): InAmpRight2 204 Mixer (NID = 1Bh): InAmpLeft3 205 Mixer (NID = 1Bh): InAmpRight3 205 Mixer (NID = 1Bh): InAmpLeft4 206 Mixer (NID = 1Bh): InAmpRight4 206 Mixer (NID = 1Bh): InAmpLeft5 207 Mixer (NID = 1Bh): InAmpRight5 207 Mixer (NID = 1Bh): InAmpLeft6 208 Mixer (NID = 1Bh): InAmpRight6 209 Mixer (NID = 1Bh): InAmpLeft7 209 Mixer (NID = 1Bh): InAmpRight7 210 Mixer (NID = 1Bh): PwrState 210 MixerOutVol (NID = 1Ch): WCap 211 MixerOutVol (NID = 1Ch): ConLst 212 MixerOutVol (NID = 1Ch): ConLstEntry0 213 MixerOutVol (NID = 1Ch): OutAmpCap 213 MixerOutVol (NID = 1Ch): OutAmpLeft 214 MixerOutVol (NID = 1Ch): OutAmpRight 215 MixerOutVol (NID = 1Ch): PwrState 215 SPDIFOut0 (NID = 1Dh): WCap 216 SPDIFOut0 (NID = 1Dh): PCMCap 218 SPDIFOut0 (NID = 1Dh): StreamCap 220 SPDIFOut0 (NID = 1Dh): OutAmpCap 220 SPDIFOut0 (NID = 1Dh): Cnvtr 221 SPDIFOut0 (NID = 1Dh): OutAmpLeft 222 SPDIFOut0 (NID = 1Dh): OutAmpRight 223 SPDIFOut0 (NID = 1Dh): PwrState 223 SPDIFOut0 (NID = 1Dh): CnvtrID 224 SPDIFOut0 (NID = 1Dh): DigCnvtr 224 SPDIFOut1 (NID = 1Eh): WCap 225 SPDIFOut1 (NID = 1Eh): PCMCap 227 SPDIFOut1 (NID = 1Eh): StreamCap 229 SPDIFOut1 (NID = 1Eh): OutAmpCap 229 SPDIFOut1 (NID = 1Eh): Cnvtr 230 SPDIFOut1 (NID = 1Eh): OutAmpLeft 231 SPDIFOut1 (NID = 1Eh): OutAmpRight 232 SPDIFOut1 (NID = 1Eh): PwrState 232 SPDIFOut1 (NID = 1Eh): CnvtrID 233 SPDIFOut1 (NID = 1Eh): DigCnvtr 234 Dig0Pin (NID = 1Fh): WCap 235 6 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Dig0Pin (NID = 1Fh): PinCap 236 Dig0Pin (NID = 1Fh): ConLst 237 Dig0Pin (NID = 1Fh): ConLstEntry0 238 Dig0Pin (NID = 1Fh): PwrState 238 Dig0Pin (NID = 1Fh): PinWCntrl 239 Dig0Pin (NID = 1Fh): UnsolResp 240 Dig0Pin (NID = 1Fh): ChSense 240 Dig0Pin (NID = 1Fh): ConfigDefault 241 Dig1Pin (NID = 20h): WCap 243 Dig1Pin (NID = 20h): PinCap 245 Dig1Pin (NID = 20h): ConLst 246 Dig1Pin (NID = 20h): ConLstEntry0 247 Dig1Pin (NID = 20h): PwrState 247 Dig1Pin (NID = 20h): PinWCntrl 248 Dig1Pin (NID = 20h): UnsolResp 249 Dig1Pin (NID = 20h): ChSense 249 Dig1Pin (NID = 20h): ConfigDefault 249 DigBeep (NID = 21h): WCap 252 DigBeep (NID = 21h): OutAmpCap 253 DigBeep (NID = 21h): OutAmpLeft 253 DigBeep (NID = 21h): PwrState 254 DigBeep (NID = 21h): Gen 255 SPDIFIn (NID = 22h): WCap 255 SPDIFIn (NID = 22h): Cnvtr 258 SPDIFIn (NID = 22h): PCMCap 259 SPDIFIn (NID = 22h): StreamCap 260 SPDIFIn (NID = 22h): ConLst 261 SPDIFIn (NID = 22h): ConLstEntry0 261 SPDIFIn (NID = 22h): PwrState 262 SPDIFIn (NID = 22h): CnvtrID 263 SPDIFIn (NID = 22h): DigCnvtr 263 SPDIFIn (NID = 22h): InAmpCap 264 SPDIFIn (NID = 22h): InAmpLeft 265 SPDIFIn (NID = 22h): InAmpRight 265 SPDIFIn (NID = 22h): VS 266 SPDIFIn (NID = 22h): Status 266 NID = 23h Reserved 269 Dig2Pin (NID = 24h): WCap 270 Dig2Pin (NID = 24h): PinCap 271 Dig2Pin (NID = 24h): PwrState 272 Dig2Pin (NID = 24h): UnsolResp 274 Dig2Pin (NID = 24h): ChSense 274 Dig2Pin (NID = 24h): ConfigDefault 275 PINOUTS AND PACKAGE INFORMATION 278 48-Pin Pinout 278 40-Pin Pinout 279 Pin Table for 48-Pin 280 Pin Table for 40-Pin 281 48QFN Package Outline and Package Dimensions 283 40QFN Package Outline and Package Dimensions 284 Pb Free Process- Package Classification Reflow Temperatures 284 DISCLAIMER 285 DOCUMENT REVISION HISTORY 286 7 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS LIST OF FIGURES Multi-channel capture 20 Multi-channel timing diagram 20 EAPD System level Example 24 Single Digital Microphone (data is ported to both left and right channels 26 Stereo Digital Microphone Configuration 27 Quad Digital Microphone Configuration 28 Analog PCBeep Flow Chart 30 HD Audio Bus Timing 41 Common Port Configurations 43 48-pin Package Functional Diagram 44 40-pin Package Functional Diagram 45 48-pin Package Widget Diagram 46 40-pin Package Widget Diagram 47 48-Pin Pinout 278 40-Pin Pinout 279 48QFN Package Diagram 283 40QFN Package Diagram 284 8 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS LIST OF TABLES Port Functionality 11 Analog Output Port Behavior 11 Resistor Tolerance 13 48 pin Jack Detect 13 40 pin Jack Detect 13 SPDIF OUT 0 or 1 Behavior 14 SPDIF Behavior 15 Power Management 17 Example channel mapping 20 EAPD Pin Mode Select 22 Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations 22 BTL Amp Enable Configuration 22 EAPD Analog PC_Beep behavior 23 EAPD Behavior 23 Valid Digital Mic Configurations 25 DMIC_CLK and DMIC_0,1 Operation During Power States 25 Dig0Pin (Pin 48/40) Function Selection 33 Dig1Pin (Pin 46/38) Function Selection 33 Electrical Specification: Maximum Ratings 35 Recommended Operating Conditions 35 Analog Performance 36 Capless Headphone Supply 41 HD Audio Bus Timing 41 SPDIF Timing 42 Digital Mic timing 42 GPIO Characteristics 42 Pin Configuration Default Settings 48 High Definition Audio Widget 50 Widget Descriptions 51 48-PinTable 280 40-Pin Table 281 Reflow 284 9 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 1. DESCRIPTION 1.1. Overview The 92HD66B provide stereo 24- bit, full duplex resolution supporting sample rates up to 192kHz by the DAC and ADC. SPDIF outputs support sample rates of 192kHz, 96kHz, 88.2kHz, 48kHz, and 44.1kHz. SPDIF input supports 96KHz, 88.2KHz, 48KHz, and 44.1KHz sample rates. Additional sample rates are supported by the driver software. The 92HD66B supports a wide range of desktop and laptop 4-channel configurations. The 2 independent SPDIF output interfaces provides connectivity to consumer electronic equipment or to a home entertainment system. Simultaneous HDMI and SPDIF output is possible. All inputs can be programmed with 0-30 dB gain in 10 dB steps allowing for line or microphone use of any input. Port presence detect capabilities allow the CODEC to detect when audio devices are connected to the CODEC. The fully parametric IDT SoftEQ can be initiated upon headphone jack insertion and removal for protection of notebook speakers. The 92HD66B operates with a 3.3V digital supply and a 5V analog supply. It allows for 1.5V and 3.3V HDA signaling; the correct signalling level is selected based on the power supply voltage on the DVDD-IO pin. The 92HD66B is offered in a 48 or 40 pin QFN Environmental (ROHS) package. 1.2. Orderable Part Numbers 92HD66B1X5NDGXyyX 92HD66B1X3NDGXyyX 92HD66B2X5NDGXyyX 92HD66B2X3NDGXyyX 92HD66B3X5NLGXyyX 92HD66B3X3NLGXyyX 4ch,  40QFN, 1.5V HDA Signaling, 5V AVDD 4ch,  40QFN, 1.5V HDA Signaling, 3.3V AVDD 4ch,  40QFN, 3.3V HDA Signaling, 5V AVDD 4ch,  40QFN, 3.3V HDA Signaling, 3.3V AVDD 4ch,  48QFN, switchable 1.5V or 3.3V HDA Signaling, 5V AVDD 4ch,  48QFN, switchable 1.5V or 3.3V HDA Signaling, 3.3V AVDD yy = silicon stepping/revision, contact sales for current data. Add an “8” to the end for tape and reel delivery. 10 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2. DETAILED DESCRIPTION 2.1. Port Functionality Pins (48-pin) 29/30/39/40 31/32/42/43 19/20 15/16 17/18 48 46 45 4 (CLK=2) Port A B C D E F SPDIF_OUT0 SPDIF_OUT1 SPDIF_IN DMIC0 Yes Yes Yes 2 2 Pins (40-pin) 22/23/32/33 24/25/35/36 14/15 12/13 40 38 37 3 (CLK=2) Input Yes Yes Yes Output Yes Yes Yes Yes Yes Yes Yes Head phone Yes Yes Mic Bias (Vref pin) Yes1 Yes 1 Input boost amp Yes Yes Yes Yes Yes Yes3 Yes3 Yes Yes Yes Yes Yes Yes Yes Table 1. Port Functionality 1. Ports A and B provide internal microphone bias on the headphone out pins. No external VrefOut pin is needed. 2. DMIC1 3. Boost amp is only available for DMIC input and is not associated with the pin widget 2.1.1. Port Characteristics Universal (Bi-directional) jacks are supported on ports A, B, C, E (48-pin package only), and F. Ports A, B, and F are designed to drive 32 ohm (nominal) headphones or a 10K (nominal) load. Line Level outputs are intended to drive an external 10K load (nominal) and an on board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 2.8K ohms and above when implementing ports capable of operating as microphone inputs or line outputs. Input ports are 75K (nominal) at the pin. DAC full scale outputs and intended full scale input levels are greater than 1V rms at 5V (+5%/ -10%) to meet WLP requirements. Line output ports and Headphone output ports on the codec may be configured for +3dBV full scale output levels by using a vendor specific verb. Output ports implement anti-pop circuits to prevent pops/clicks associated with turning power on/off or charging and discharging output coupling capacitors (except for cap-less headphone ports). Unused ports should be left unconnected. When updating existing designs to use the codec, ensure that there are no conflicts between the output ports on the codec and existing circuitry. Used as output for analog PC_Beep Don’t care Don’t care AFG Power State D0-D2 Input Output Enable Enable 1 1 1 1 Used as output for DAC/Mixer Don’t care Don’t care Used as input for ADC, mixer Yes No Port Behavior Not allowed. Port is active as Input. Not allowed. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Table 2. Analog Output Port Behavior 11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS AFG Power State Used as output for DAC/Mixer NA NA Used as output for analog PC_Beep NA NA Used as input for ADC, mixer Yes No NA Input Output Enable Enable 1 1 0 0 0 1 Port Behavior Active - Port enabled as input Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Active - Port enabled as output 0 1 0 D3 1 1 0 0 1 0 1 currently used by DAC, mixer, beep, or is traditional line or headphone output not currently used by DAC, mixer, beep, and is cap-less headphone output NA NA NA NA NA NA NA Inactive (Power Down) Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Don’t care Don’t care Don’t care Not allowed. Port is active as Input. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Low power state. If enabled, Beep will output from the port Inactive (Power Down) 0 1 0 D3cold D4 D5 - 0 - currently used by DAC, mixer, beep, or is traditional line or headphone output not currently used by DAC, mixer, beep, and is cap-less headphone output NA NA Don’t care Don’t care Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Inactive (Power Down) - Port keeps output coupling caps charged if port uses caps. Off - Charge on coupling caps (if used) will not be maintained. Table 2. Analog Output Port Behavior 2.2. Vref_Out Ports A, B, C, & E (48-pin package only) support Vref_Out pins for biasing electret cartridge microphones. Settings of 80% AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read. 2.3. Jack Detect Plugs inserted to a jack are detected using SENSE inputs as described in the tables below. Per HDA015-B, the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both the CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is invalid. 12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will generate a Power State Change Request when a change in port connectivity is sensed and then generate an unsolicited response after the HD Audio link has been brought out of a low power state and the device has been enumerated. Per HDA015-B, this will take less than 10mS. The following table summarizes the proper resistor tolerances for different analog supply voltages. . AVdd Nominal Voltage (+/- 5%) 4.75V or 5.0V Resistor Tolerance Pull-Up Resistor Tolerance SENSE_A/B 1% Table 3. Resistor Tolerance 1% Resistor 39.2K 20.0K 10.0K 5.11K 2.49K SENSE_A PORT A PORT B PORT C PORT F SENSE_B PORT E Mono SPDIF0/DMIC1 SPDIF1/DMIC1 Pull-up to Avreg (X5) Pull-up to Avreg (X5) Pull-up to AVDD (X3) Pull-up to AVDD (X3) Table 4. 48 pin Jack Detect . Resistor 39.2K 20.0K 10.0K 5.11K 2.49K SENSE_A PORT A PORT B PORT C PORT F Pull-up to Avreg (X5) Pull-up to AVDD (X3) Table 5. 40 pin Jack Detect See reference design for more information on Jack Detect implementation. 2.4. SPDIF Output Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with all consumer audio gear and allows for convenient integration into home theater systems and media center PCs. Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle) which does not meet the IEC-60958-3 0.05UI requirement at 192KHz. The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached to the same stream, the two SPDIF output converters may be misaligned with respect to their frame boundaries. 13 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Per HDA015-B, the SPDIF outputs support the ability to provide clocking information even when no stream is selected for the converter, or when in a low power state. Also, as stated in the DCN, the SPDIF output ports support port presence detect. SPDIF Outputs are outlined in tables below. . AFG Power State D0-D4 D0-D4 D0-D4 RESET# Asserted (Low) De-Asserted (High) De-Asserted (High) De-Asserted (High) GPIO0 Input Output Enable Enable Enable 0 1 0 0 Keep Alive En Converter Stream Dig En ID GPIO SPDIF IN or DMIC IN Pin Mode Pin Behavior Hi-Z immediately after power on, otherwise the previous state is retained. Hi-Z Active - Pin reflects GPIO0 configuration (internal pull-down enabled) Pin functions as SPDIF input or DMIC input Active - Pin drives 0 Active - Pin drives SPDIF-format, but data is zeroes Active - Pin drives SPDIFOut1 data Active - Pin drives SPDIF-format, but data is zeroes Active - Pin drives SPDIF-format, but data is zeroes Active - Pin drives SPDIFOut1 data Active - Pin drives 0 Active - Pin drives 0 SPDIF OUT Active - Pin drives SPDIF-format, but data is zeroes Active - Pin drives SPDIF-format, but data is zeroes Hi-Z Hi-Z Active - Pin drives SPDIF-format, but data is zeroes Active - Pin drives SPDIF-format, but data is zeroes Hi-Z Hi-Z Hi-Z D0-D4 0 1 0 - 0 0 1-15 0 De-Asserted (High) 1 D0 0 0 1 1 0 0 1-15 1 0 0 D1-D2 De-Asserted (High) 0 0 1 1 1 0 0 D3 De-Asserted (High) 0 0 1 1 1 D3cold D4 D5 De-Asserted (High) De-Asserted (High) 0 0 0 0 1 1 0 1 0 1 0 1 0 1 - - Table 6. SPDIF OUT 0 or 1 Behavior 14 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.5. SPDIF Input SPDIF IN can operate at 44.1 KHz, 48 KHz, or 96 KHz, and implements internal Jack Sensing (Port presence Detect). A sophisticated digital PLL allows automatic rate detection and accurate data recovery. The ability to directly accept consumer SPDIF voltage levels eliminates the need for costly external receiver ICs. Status flags from the input stream are updated only after the entire valid block has been received (or at least when all bits of a particular status flag have been received) to ensure that software does not read an invalid mixture of old and new data. In general, the SPDIF input block does not alter the data received. However, it is sometimes necessary to alter the data when the converter widget settings do not match the stream format. The following table outlines a few cases and the expected behavior. Port presence detect for SPDIF_IN operates differently from other ports. Once the PLL has locked and valid framing (no errors) has been detected, then the port presence detect bit is set. In D3, and D3 without a clock, it is not possible to check for proper framing. Monitoring of activity (rising and falling edges) is sufficient to verify a change in connectivity in D3. If no clock is present, then the internal oscillator is used until a clock is restored. When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will generate a Power State Change Request when a change in SPDIF_IN port connectivity is sensed and then generate an unsolicited response after the HD Audio link has been brought out of a low power state and the device has been enumerated. Per HDA015-B, this will take less than 10mS. Conflict Behavior Resolution Program the converter widget with the same rate as indicated by the input stream. Although the SPDIF input block is designed to handle inputs slightly above or below the Converter widget rate does not programmed rate, samples may be lost if equal the stream rate the input rate is much higher than the rate programmed into the converter widget. If the input stream indicates non PCM data, Converter widget programmed the data will be truncated to the requested Program the converter widget with the word for a word length less than the word length. If LPCM data is indicated in the length indicated in the input stream. word length provided by the input stream, the CODEC will round the input stream 1 received data to the requested length. Regardless of content, 24 bits per channel of data will be transferred from the SPDIF Converter widget programmed input stream to the HD Audio bus interface. with a word length greater than Truncation or rounding to the requested the word length provided by word length will be handled as described as the input stream. above. Any non-zero data in the incoming stream will cause problems. Program the converter widget with the word length indicated in the input stream. Although not recommended, application or driver software may program the converter widget with a word length of 24 bits, truncate the input to the word length indicated by the input stream, then right extend the data using 0s to the desired word length. 1. Table 7. SPDIF Behavior Rounding may be disabled by setting the disable bit (AFG vendor specific verb -see widget list) or setting the SPDIF_IN converter widget Frmt StrmType field to 1 (non-PCM) 15 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.6. Mono Output The Mono Out port source selection, power state, and mute characteristics are all independently controlled by the mono output port controls. The mono output pin is not available on the 40-pin package options. The following sources are available for the Mono Out pin: • • • DAC0 Output: When selected (by using the port connection list), the DAC0 left and right outputs are summed together. DAC1 Output: When selected (by using the port connection list), the DAC1 left and right outputs are summed together. Mixer Output: When selected (by using the port connection list), the mixer left and right outputs are summed together. The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of the two inputs. The full scale output at mono out is designed to be about 0dBV. Like the stereo line and headphone outputs, it is not possible to adjust to a +3dBV output level using a vendor defined verb. 2.7. Analog Mixer The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as independent mutes on each input. The following inputs are available: The output of the mixer may be sent to the ADC where the ADC record gain can adjust the volume. If the output of the mixer is sent to an analog port, then a separate volume control is provided to adjust the output volume. This mixer output volume control supports a gain range of -46.5dB to 0dB in 1.5dB steps. (Selecting -46.5dB will automatically mute the output.) • • • • • • • Port A Port B Port C Port E (not available on 40-pin option) Port F DAC0 DAC1 2.8. ADC Multiplexers The codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC record gain function (-16 to +30dB gain in 1dB steps) as an output amp and allow a preselection of one of these possible inputs: • • • • • • • • Port A Port B Port C Port E (not available on 40-pin option) Port F Mixer Output DMIC 0 DMIC 1 16 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.9. Power Management The HD Audio specification defines power states, power state widgets, and power state verbs. Power management is implemented at several levels. The Audio Function Group (AFG) , all converter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are active in D0 and inactive in D1-D3. The following table describes what functionality is active in each power state. Function SPDIF Outputs SPDIF Input D0 On On On On On On On On On On On On On On On On On On On On On On On D11 On Off Off Off Off Off Off Off Off On On On On On On On On On On On On On On D2 On (idle) Off Off Off Off Off Off Off Off On Off Off Off Off On On On On On On On On On D3 On (idle)6 Off Off Off Off Off Off Off Off On 6 D3cold Off Off Off Off Off Off Off Off Off On Off Off Off Off Off Off 3 4 Vendor Vendor 2 Specific D4 SpecificD52 Off Off Off Off Off Off Off Off Off On Off Off Off Off Off Off 3 Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off 3 Digital Microphone inputs DAC D2S ADC ADC Volume Control Ref ADC Analog Clocks GPIO pins VrefOut Pins Input Boost Analog mixer Mixer Volumes Analog PC_Beep Digital PC_Beep Lo/HP Amps VAG amp Port Sense Reference Bias generator Reference Bandgap core HD Audio-Link PLL Off Off Off Off On On 6 Low Drive On5 On On On 6 Low Drive Off On On Limited Off9 7 Low Drive Off On On Off Off Off Off Off Off Off Off Off Low Drive Low Drive Low Drive Off8 Table 8. Power Management 1. No DAC or ADC streams are active. Analog mixing and loop thru are supported. 2. D4 and D5 power states are entered only when D3cold is requested. D4 and D5 may be viewed as D3cold behavioral options. 3. VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be attenuated and distorted depending on load impedance. 4. VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but in a low power state. 5. Both AVDD and DVDD must be available for Port Sense to operate. 6. Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME) 7. Only double function group reset verbs and link reset supported per ECR15b 17 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 8. PLL remains on if SPDIF_Out Keep Alive is enabled. PLL disabled only after DAC fading is complete and SDM has settled. 9. PLL disabled only after DAC fading is complete and SDM has settled. The D3-default state is available for HD Audio compliance. The programmable values, exposed via vendor-specific settings, are under IDT Device Driver control for further power reduction. The analog mixer, line and headphone amps, port presence detect, and internal references may be disabled using vendor specific verbs. Use of these vendor specific verbs will cause pops. The default power state for the Audio Function Group after reset is D3. 2.10. AFG D0 The AFG D0 state is the active state for the device. All functions are active if their power state (if they support power management at their node level) has been set to D0. 2.11. AFG D1 D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions are active. The part will resume from theD1 to theD0 state within 1 mS. 2.12. AFG D2 The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers and internal references remain active to keep port coupling caps charged and the system ready for a quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state within 2mS. 2.13. AFG D3 The D3-default state is available for HD Audio compliance. All converters are shut down. Port amplifiers and references are active but in a low power state to prevent pops. Resume times may be longer than those from D2, but still less than 10mS to meet Intel low power goals. The default power state for the Audio Function Group after power is applied is D3. While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3 state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behavior is as follows (see the HDA015-B section for more information): Function HDA Bus active Port Presence Detect state change Unsolicited Response GPIO state change Unsolicited Response HDA Bus stopped Wake Event followed by an unsolicited response Wake Event followed by an unsolicited response 2.13.1. AFG D3cold The D3cold power state is the lowest power state available that does not use vendor specific verbs. While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (double AFG reset, link reset). However, audio processing, port presence detect, and other functions are disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from D3cold is less than 200mS. 18 V 1.0 2/12 92HD66B ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.14. Vendor Specific Function Group Power States D4/D5 The codec introduces vendor specific power states. A vendor defined verb is added to the Audio Function Group that combines multiple vendor specific power control bits into logical power states for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 further reduces power consumption on the digital supply by turning off GPIO drivers, and reduces analog power consumption by turning off all analog circuitry except for reset circuits. States D4/D5 are not entered until D3cold has been requested so are actually D3cold options rather than true, independent, power states. Software can pre-program the D4 or D5 state as a re-definition of how the part will behave when the D3cold power state is requested or software may enter D3cold, then set the D4 or D5 before performing the power state get command. The preferred method is to request D3cold, then select D4 or D5 as desired.This will reduce the severity of pops encountered when entering D4 or D5. Both power states require a link reset or removal of DVDD to exit. The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for example) may take several seconds. 2.15. Vendor Specific Function Group Power State “D5 Kill” Vendor specific “D5 Kill” places the device in a low power, non responsive, state that is intended to disable the CODEC when, for security reasons, it is desired that no audio playback or recording take place. State “D5 Kill” is not entered until D3cold has been requested. Software pre-programs both the D4 and D5 state request bits (D4 and D5 = 1) then request D3cold. After responding to the Function Group Power State Get verb (needed to enter D3cold), the CODEC will no longer respond to any link activity. The only way to exit this state is to remove power (Power on reset will set the power state to D3.) “D5 Kill” is identical to vendor specific D5 with the exception that the CODEC will only exit this state when power is removed. 2.16. Low-voltage HDA Signaling The codec is compatible with either 1.5V or 3.3V HDA bus signaling; in the 48-QFN package the voltage selection is done dynamically based on the input voltage of DVDD_IO. DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be used for the HDA bus signals. When in 1.5V mode, the codec can correctly decode BITCLK, SYNC, RESET# and SDO as they operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected, as they always function at their nominal voltage (DVDD or AVDD). 2.17. Multi-channel capture The capability to assign multiple ADC Converters to the same stream is supported to meet the microphone array requirements of Vista and future operating systems. Single converter streams are 19 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS still supported this is done by assigning unique non zero Stream IDs to each converter. All capture devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restrictions regarding digital microphones. The ADC Converters can be associated with a single stream as long the sample rate and the bits per sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget and is restricted to even values. The ADC converters will always put out a stereo sample and therefore require 2 channels per converter. The stream will not be generated unless all entries for the targeted converters are set identically, and the total number of assigned converter channels matches the value in the NmbrChan field. These are listed the “Multi-Converter Stream Critical Entries.” table. An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying channels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the number of channels must be set to 4 channels “NmbrChan = 0011”. ADC1 CnvtrID ADC0 CnvtrID (NID = 0x08) [3:0] (NID = 0x07) Ch = 2 Ch=0 [3:0] Table 9. Example channel mapping Figure 1. Multi-channel capture ADC0.CnvrtID.Channel = 0 ADC1.CnvrtID.Channel = 2 ADC0.CnvrtID.Channel = 2 ADC1.CnvrtID.Channel = 0 Stream ID Data Length Data Length ADC0 Left Channel ADC1 Left Channel ADC0 Right Channel ADC1 Right Channel ADC1 Left Channel ADC0 Left Channel ADC1 Right Channel ADC0 Right Channel Stream ID The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1. Figure 2. Multi-channel timing diagram BITCLK SDI 0 0 0 1 0 0 1 1 0 0 ADC0 L23 ADC0 L0 ADC0 R23 ADC0 R0 ADC1 L23 ADC1 L0 ADC1 R23 ADC1 R0 STREAM ID STREAM TAG DATA LENGTH LEFT ADC0 RIGHT LEFT ADC1 DATA BLOCK RIGHT 20 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS ADC[1:0] Cnvtr Bit Number [15] Sub Field Name StrmType Description Stream Type (TYPE): 0: PCM 1: Non-PCM (not supported) Sample Base Rate 0= 48kHz 1=44.1KHz Sample Base Rate Multiple 000=48kHz/44.1kHz or less 001= x2 010= x3 (not supported) 011= x4 192kHz only, 176.4 not supported 100-111= Reserved Sample Base Rate Divisor 000= Divide by 1 001= Divide by 2 (not supported) 010= Divide by 3 (not supported) 011= Divide by 4 (not supported) 100= Divide by 5 (not supported) 101= Divide by 6 (not supported) 110= Divide by 7 (not supported) 111= Divide by 8 (not supported) Bits per Sample 000= 8 bits (not supported) 001= 16 bits 010= 20 bits 011= 24 bits 100-111= Reserved Number of Channels Number of channels for this stream in each “sample block” of the “packets” in each “frame” on the link. 0000=1 channel (not supported) 0001 = 2 channels … 1111= 16 channels. Software-programmable integer representing link stream ID used by the converter widget. By convention stream 0 is reserved as unused. Integer representing lowest channel used by converter. 0 and 2 are valid Entries If assigned to the same stream, one ADC must be assigned a value of 0 and the other ADC assigned a value of 2. [14] FrmtSmplRate [13:11] SmplRateMultp [10:8] SmplRateDiv [6:4] BitsPerSmpl [3:0] NmbrChan [7:4] Strm [3:0] Ch Table 10: Multi-channel 2.18. EAPD The EAPD pin (pin 47) is a dedicated, bi-directional control pin. Although named External Amplifier Power Down (EAPD) by the HD Audio specification, this pin operates as an external amplifier power up signal. The EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power up (equivalent to D0), and a 0 causes it to power down (equivalent to D3.) When the EAPD value = 21 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 1, the EAPD pin must be placed in a state appropriate to the current power state of the associated Pin Widget even though the EAPD value (in the register) may remain 1. The pin defaults to an open-drain configuration (an external pull-up is recommended.) Per the HD Audio specification and HDA015-B, multiple ports may control EAPD. The EAPD pin assumes the highest power state of all the EAPD bits in all of the pin complexes. The default value of EAPD is 1 (powered on), but the FG power state will override and the pin will be low. Vendor specific verbs are available to configure this pin. These verbs retain their values across link and single function group resets but are set to their default values by power on reset: MODE1 0 0 1 1 MODE0 0 1 0 1 EAPD Pin Function Open Drain I/O CMOS Output CMOS Input CMOS Input Description Value at pin is wired-AND of EAPD bit and external signal.(default) Value of EAPD bit in pin widget is forced at pin External signal controls internal amps. EAPD bit in pin widget ignored External signal controls internal amps. EAPD bit in pin widget ignored Table 11. EAPD Pin Mode Select Control Flag EAPD PIN MODE 1:0 HP SD HP SD MODE HP SD INV Description Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain) 0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only 0 = Amp will mute when disabled (default) / 1 = Amp will shut down (enter a low power state) when disabled 0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute) when EAPD pin is high. Table 12. Control bit descriptions for BTL amplifier and Headphone amplifier enable configurations HP SD 0 0 0 0 0 0 0 0 1 1 HP SD MODE 0 0 0 0 1 1 1 1 0 1 HP SD INV 0 0 1 1 0 0 1 1 NA NA EAPD Pin State 0 1 0 1 0 1 0 1 NA NA Headphone Amp State Amplifier is mute (default1) Amplifier is active Amplifier is active Amplifier is mute Amplifier is in a low power state Amplifier is active Amplifier is active Amplifier is in a low power state Amplifier follows pin/function group power state and will mute when disabled Amplifier follows pin/function group power state and will enter a low power state when disabled Table 13. BTL Amp Enable Configuration 1. EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in D0. The state after a single or double function group reset will be compliant with HDA015-B. Each Headphone port has its own configuration bits for SD, SD MODE, and SD INV. 22 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Analog BEEP enabled 0 1 EAPD Pin value1 Description Forced to low when in D2 or D3 Forced low in D2 or D3 unless port is enabled as output 1. Follows description in HD Audio spec. External amplifier is shut down when pin or function group power state is D2 or D3 independent of value in EAPD bit. Power state is ignored if port is enabled as output and port EAPD=1 to allow PC_Beep support in D2 and D3 Table 14. EAPD Analog PC_Beep behavior When pin is enabled as Open Drain or CMOS output. RESET# Asserted (Low) Asserted (Low) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) De-Asserted (High) Analog PC_BEEP Enabled1 Disabled Disabled Enabled Disabled Enabled Port Power State D0-D1 D0-D2 D0-D2 D0-D3 D0-D3 Pin Behavior Active high immediately after power on, otherwise the previous state is retained across FG and link reset events The previous state is retained across FG and link reset events Active - Pin reflects EAPD bit unless held low by external source. Active - Pin reflects EAPD bit unless held low by external source. Pin forced low to disable external amp Active - EAPD Pin high if any port EAPD bit =1 and that port also enabled as output. Pin forced low to disable external amp Active - EAPD Pin high if any port EAPD bit=1 and that port also enabled as output. Pin forced low to disable external amp Pin forced low to disable external amp Pin Hi-Z (off) AFG Power State D0-D3 D0-D3 D0 D1 D2 D2 D3 D3 D3cold D4 D5 1. Table 15. EAPD Behavior PC_Beep is automatically routed to ports A, B, D, and F after power-on reset while link reset is active and EAPD will be high to enable an external amplifier. This may be disabled using a vendor specific verb. If the automatic beep path is disabled, beep will still be supported with EAPD active in link reset if Analog Beep is manually enabled and at least one port is configured as an output before entering link reset. If the automatic Beep routing is disabled and Analog Beep has not been manually configured before entering link reset, then the EAPD pin will retain its current state. 23 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS HP AUDIO CONTROL BLOCK DIAGRAM SYNC FROM KBC TO OS OS SCAN CODES SYNC FROM AUDIO GUI TO KBC MUTE + UP/DOWN BUTTONS (MUTE LED ON SAME BOARD) KBC A_EAPD A_SD GPIO_1 CODEC SPKR_EN# SPKR AMP Figure 3. EAPD System level Example 2.19. Digital Microphone Support The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry individual channels of digital microphone data to the ADC. In the event that a single microphone is used, the data is ported to both ADC channels. This mode is selected using a vendor specific verb and the left time slot is copied to the ADC left and right inputs. The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is synchronous to the internal master clock. The default frequency is 2.352Mhz. The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the analog ports. Although the internal implementation is different between the analog ports and the digital microphones, the functionality is the same. In most cases, the default values for the DMIC clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected. When switching from the digital microphone to an analog input to the ADC, the analog portion of the ADC will be brought back to a full power state and allowed to stabilize before switching from the digital microphone to the analog input. This should take less than 10mS. The DMIC capable pin widgets (NID 1Fh and NID 20h) support port presence detect using SENSE-B input on 2/3 DAC parts in a 48-pin package but not in a 40-pin package. However, the DMIC0 pin widget (NID 11h) does not support presence detect. 24 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Digital Mics 0 Data Sample N/A ADC Conn. N/A Notes No Digital Microphones Available on either DMIC_0 or DMIC_1 When using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone for “Left” and select mono operation using the vendor specific verb. “Left” D-mic data is used for ADC left and right channels. Available on either DMIC_0 or DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge (multiplexed output) capability. Requires both DMIC_0 and DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge (multiplexed output) capability. Two ADC units are required to support this configuration Connected to DMIC_0 and DMIC_1, External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge capability. Two ADC units are required to support this configuration Table 16. Valid Digital Mic Configurations 1 Single Edge 0, or 1 2 Double Edge on either DMIC_0 or 1 Double Edge on one DMIC pin and Single Edge on the second DMIC pin. 0, or 1 3 0, or 1 4 Double Edge 0, or 1 Power State D0 D1-D3 D0-D3 D4 D5 DMIC Widget Enabled? Yes Yes No - DMIC_CLK Output Clock Capable Clock Disabled Clock Disabled Clock Disabled Clock Disabled DMIC_0,1 Input Capable Input Disabled Input Disabled Input Disabled Input Disabled Notes DMIC_CLK Output is Enabled when either DMIC_0 or DMIC_1 Input Widget is Enabled. Otherwise, the DMIC_CLK remains Low DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down DMIC_CLK is HIGH-Z with Weak Pull-down Table 17. DMIC_CLK and DMIC_0,1 Operation During Power States 25 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Figure 4. Single Digital Microphone (data is ported to both left and right channels Off-Chip Digital Microphone DMIC_0 OR DMIC_1 Pin DMIC_CLK Pin On-Chip Single Line In Stereo Channels Output STEREO ADC0 or 1 PCM On-Chip Multiplexer Single Microphone not supporting multiplexed output. DMIC_0 Or DMIC_1 Valid Data Right Channel Left Channel Valid Data Valid Data MUX DMIC_CLK Single “Left” Microphone, DMIC input set to mono input mode. DMIC_0 Or DMIC_1 Valid Data Valid Data Valid Data Valid Data Left & Right Channel DMIC_CLK 26 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Figure 5. Stereo Digital Microphone Configuration Off-Chip External Multiplexer DMIC_0 Or DMIC_1 MUX On-Chip Digital Microphones On-Chip Multiplexer Stereo Channels Output Pin STEREO ADC0 or 1 PCM MUX DMIC_CLK Pin DMIC_0 Or DMIC_1 Valid Data R Valid Data L Valid Data R Valid Data L Valid Data R Right Channel Left Channel DMIC_CLK Note: Some Digital Microphone Implementations support data on either edge, therefore, the external mux may not be required. 27 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Figure 6. Quad Digital Microphone Configuration Off-Chip Digital Microphones External Multiplexer DMIC_0 MUX On-Chip On-Chip Multiplexer Stereo Channels Output For DMIC_0 L&R Pin STEREO ADC0 PCM MUX DMIC_CLK Pin On-Chip Multiplexer DMIC_1 MUX Pin STEREO ADC1 PCM Stereo Channels Output For DMIC_1 L&R MUX Digital Microphones External Multiplexer DMIC_0 Valid Data R0 Valid Data L0 Valid Data R0 Valid Data L0 Valid Data R0 DMIC_1 Valid Data R1 Valid Data L1 Valid Data R1 Valid Data L1 Valid Data R1 Right Channel Left Right Channel Channel Left Channel DMIC_CLK Note: Some Digital Microphone Implementations support data on either edge, in this case the external multiplexer is not required. 2.20. Analog PC-Beep The codec supports automatic routing of the PC_Beep pin to several outputs when the HD-Link is in reset. The codec will route PC_Beep to ports A, B, and F by default when reset is applied. To prevent pops, beep is not enabled immediately when power is applied. 92HD90 will mute outputs and wait until references and amplifiers have stabilized before enabling beep pass thru after power on reset. To prevent pops when removing power, automatic routing of PC_Beep is not supported in D3cold, D4, or D5. 28 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Analog PC-Beep may also be supported during HD-Link Reset if analog PC_Beep is manually enabled before entering reset. Analog PC_Beep is mixed at the port and only ports enabled as outputs will pass PC_Beep. Analog PC_Beep (or a digital equivalent) must not prevent passing WLP when analog PC_Beep is enabled. Analog PC_Beep, when enabled, must not prevent other audio sources from playing (we must mix not mux.) Beeps from ICH (from Beep.sys) can have a frequency of about 37Hz to about 32KHz. Beep duration is programmable from 1mS to about 32 seconds. A typical beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS. Due to external XOR gates used as mixers, the idle state may be logic 0 or logic 1. PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load impedance seen by the output amplifier since all ports are in a low power state while in D3. Load impedances of 10K or larger can support full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. Analog PC_Beep is not supported in D3 Cold, or the vendor specific states D4/D5. Analog PC_Beep is typically used during POST to route error beep codes to internal speakers for diagnostic purposes. When using a legacy OS such as DOS, analog PC_Beep routes “Bell” and “Alarm” tones from the south bridge to internal speakers or headphones. Keyboard controller “Keyclick” sounds are also routed to internal speakers using the analog beep function in both Windows and legacy operating systems. 2.20.1. PC_Beep Activity Monitor An activity monitor will allow the cap-less headphone amplifiers to remain in shutdown when the function group is in D3 until the beep pin is active and then quickly change to an active state (within 10mS) to pass the beep tone. Beep activity monitoring is only required when the analog beep path is enabled and the CODEC or amplifier is in a low power state (D3). 2.20.1.1. • • • • • • • • Input Characteristics: There is no correlation between frequency of the tone and duration of the tone. There will always be at least one complete cycle A minimum input level of -23dBV (200mVpp) is required for proper detection. (Inputs are typically driven by 3.3V CMOS logic followed by 12-20dB attenuation and filtering) Beeps from ICH (from Beep.sys) can have a frequency of about 37Hz to about 32KHz and are 1-bit (PFM) Beeps from the Keyboard or system management controller are typically PWM (rate unknown but typically 48KHz or less.) Beep duration may be from 1mS to ~32 seconds if provided by ICH under OS control. A typical beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS Due to external XOR gates used as mixers, the idle state may be logic 0 or logic 1 2.20.1.2. Firmware/Software Requirements: The reconfiguration outlined in this chapter must be enabled by default (without the help of firmware or OS driver.) This autonomous mode must not interfere with normal operation. 29 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Figure 7. Analog PCBeep Flow Chart POR Wait 64mS IDLE NO Analog PC_Beep Enabled? NO Link Reset Active? NO NO NO YES YES Activity on Pin? YES Turn on Amplifiers / Enable Beep Path YES Activity on Pin? Activity on Pin? NO NO Inactivity over threshold? YES Disable Beep Path / Turn off Amplifiers Digital detector will detect the “BEEP_SENSE” following the state machine in Figure above and output a signal called “BEEP_PRESENCE”. BEEP_PRESENCE is 1 when the state is Beep _Presence. Otherwise, it is 0. In the 1ms window, the signal will be sampled and counted in first 500us of 1ms window. The counter will be reset during the second 500us of 1ms window. So the actual sample period is 500us. The 30 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS main clock is typically 810KHZ. The threshold_high is 150 cycles (~37%) and the threshold_low is 30 cycles (~7.5%). If BEEP_PRESENCE=1, it will be cleared until counter is lower than threshold in 1ms window and it repeat for N times. N(1 is for 1ms) can be programmable to one among 64ms, 64ms*2, 64ms*4 and 64ms*8. 2.20.1.3. Logic control • Phase 1: analog beep auto-routing phase in the period after digital POR, before the first rising edge of link reset. • Once Analog PCbeep is detected(BEEP_PRESENCE=1) after 64ms delays (after POR), the Amplifier will be turned on(port_pwd=0, port_output_en=1, there is a timing between these two signals) and analog_beep_en=1. If BEEP_PRESENCE=0 for longer than the threshold time, the amplifiers will be turned off to save power and prevent unwanted system noise from being heard. Phase 2: When not in phase 1 • If analog beep function is disabled by driver. Analog beep auto-detect will also be disabled. • If analog beep function is enabled by driver. • Once analog PCbeep is detected(BEEP_PRESENCE=1), analog pc_beep will be enabled If in D0-D2, enabled simply means muting or un-muting beep to avoid hearing system noise on the beep input pin but it is acceptable to turn off port amplifiers if not currently used by DACs, mixer, or beep to save power. If in D3, enabled means that the necessary amplifiers are turned on so that the beep signal may be heard on all ports configured as outputs (see analog pc-beep description section above) All needed amplifiers are enabled until BEEP_PRESENCE=0 for longer than the idle threshold 2.21. Digital PC-Beep This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio sources are disabled when digital PC_Beep is active. It should be noted that digital PC Beep is disabled if the divider = 00h. 31 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load impedance seen by the output amplifier since all ports are in a low power state while in D3. Load impedances of 10K or larger can support full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to indicate that the part requires a clock. 2.22. Headphone Drivers The codec implements headphone capable outputs on some ports. The Microsoft Windows Logo Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Microsoft allows device and system manufactures to limit output voltages to address EU safety requirements. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.) The 92HD90 codec does not implement power limiting. Power limiting may be implemented through the use of an external series resistance. Although 3 Headphone amplifiers are present, only two may be used simultaneously. Headphone performance will degrade if more than one port is driving a 32 ohm load. 2.23. GPIO 2.23.1. GPIO # 0 1 2 3 4 GPIO Pin mapping and shared functions 40 pin package 38 2 3 40 Supply DVDD DVDD DVDD DVDD DVDD YES SPDIF In SPDIF Out YES EAPD GPI/O YES YES YES YES YES VrefOut DMIC IN CLK IN IN Pull Up Pull Down 50K 50K 50K 50K 50K 48 pin package 46 2 4 48 44 2.23.2. Digital Microphone/GPIO Selection 2 functions are available on the DMIC_CLK/GPIO1 and the DMIC_0/GPIO2 pins. To determine which function is enabled, the order of precedence is followed: 1. If GPIOs are not enabled through the AFG, then at reset, the pins are pulled low by an internal pull-down resistor. 2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF use) and pin2 becomes GPIO with an internal pull-down. 3. If GPIO2 is enabled through the AFG, pin 4 (3 on 40-pin package) becomes a GPIO and is pulled low by an internal pull-down resistor. 4. If the port is enabled as an input, the digital microphone will be used. 5. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone path will be mute. 32 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.23.3. SPDIF_OUT/GPIO/DMIC Selection 3 functions are available on the SPDF0/GPIO3/DMIC1 and SPDF1/GPIO0/DMIC1 pins. To determine which function is enabled, the order of precedence is followed: 1. Default at power-on is SPDIF_OUT/DMIC1 for pin 48 (40) and SPDIF_OUT/DMIC1 for pin 46(38) 2. If GPIO is enabled for that pin, it overrides the SPDIF_OUT and DMIC functions for that pin. 3. If the GPIO function is not enabled for that pin, then the DMIC or SPDIF_OUT function may be enabled by setting the pin input or output enable to 1, respectively. (Setting input and output enable to 1 at the same time will only enable DMIC) Note: If the pin selected for DMIC1 input is configured as an output or GPIO, the DMIC block will behave as if silence is present at the input. GPIO3 Enable Dig0Pin Input Enable 0 0 0 1 1 NA Dig0Pin Output Enable 0 1 NA NA Selected by DMIC1Vol (NID 0x12) NA NA No Yes NA Function Unused (input) SPDIF0 output Unused (input) DMIC1 input GPIO3 Table 18. Dig0Pin (Pin 48/40) Function Selection Selected by DMIC1Vol (NID 0x12) NA NA No Yes NA GPIO0 Enable Dig1Pin Input Enable 0 Dig1Pin Output Enable 0 1 NA NA Function Unused (input) SPDIF1 output Unused (input) DMIC1 input GPIO0 0 0 1 1 NA Table 19. Dig1Pin (Pin 46/38) Function Selection 2.24. HD Audio ECR 15b support The codec implements complete support for the HDA015-B specification building on the support already present in previous products. HDA015-B features supported are: 1. Persistence of many configuration options through bus and function group reset. 2. The ability to support port presence detect in D3 even when the HD Audio bus is in a low power state (no clock.) 3. Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0. 4. Notification if persistent register settings have been unexpectedly reset. 5. SPDIF Out active in D3 (required) 6. The ability to notify the driver that a clock is necessary so entering D3 with the clock stopped is not permissible 33 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 2.25. Digital Core Voltage Regulator The digital core operates from 1.8V (+/- 10%). Many systems require that the CODEC use a single 3.3V digital supply, so an integrated regulator is included on die. The regulator uses pin 9, DVDD, as its voltage source. The output of the LDO is connected to pin 1 and the digital core. A 10uF capacitor must be placed on pin 1 for proper load regulation and regulator stability. The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V and may precede or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the application of power and the removal of power is neither defined nor guaranteed. It is common for desktop systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely, the condition where AVDD is active but DVDD and DVDDIO are inactive. 2.26. Analog Core Voltage Regulator Many systems provide only a noisy 5 volt supply that is inappropriate for analog audio so an integrated regulator is included on die to generate the core analog supply of 4.5V. The regulator uses AVDD1 as its voltage source. A 10uF capacitor must be placed on the LDO output pin for proper load regulation and regulator stability. 92HD66B may be ordered with the analog core LDO enabled (5V operation) or bypassed (3.3V operation). 2.27. Combo Jack The codec implements a sophisticated microphone detection algorithm to differentiate between headphones and headsets when implementing 4-conductor “combo” jacks. A programmable sense window (2s to ∞) provides flexibility in managing problematic slow plug insertions and partial insertions. Programmable de-bounce, anti-pop delay, and headphone-microphone unsolicited response delay controls help ensure a robust, pleasing, experience for the end user. Support for a lanyard (“turbo”) switch using IDT’s driver further enhances combo-jack implementations by supporting many common cellular headsets. 34 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 3. CHARACTERISTICS 3.1. Audio Fidelity • 5V • DAC SNR: >95dB, A-Weighted 4.75V - 5.25V • ADC SNR: >90dB, A-Weighted 4.75V - 5.25V 3.3V • DAC SNR: >90dB, A-Weighted 3.3V • ADC SNR: >85dB, A-Weighted 3.3V • 3.2. Electrical Specifications 3.2.1. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 92HD66B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Analog maximum supply voltage Digital maximum supply voltage VREFOUT output current Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature Pin AVdd DVdd PVdd 6 Volts 5.5 Volts 6 Volts 5 mA Vss - 0.3V to Vdd + 0.3V 0 oC to +70 oC -55 oC to +125 oC Soldering temperature information for all available in the package section. Table 20. Electrical Specification: Maximum Ratings Maximum Rating 3.2.2. Recommended Operating Conditions Parameter DVDD_Core Min. 1.6 3.135 1.418 3.135 4.500 4.750 3.135 0 Tcase Table 21. Recommended Operating Conditions DVDD_IO (3.3V signaling) DVDD_IO (1.5V signaling) + 3.3V Digital + 4.75V Analog + 5.0V Analog + 3.3V Analog Typ. 1.8 3.3 1.5 3.3 4.750 5.000 3.3 Max. 1.98 3.465 1.583 3.465 5.000 5.250 03.465 +70 +90 V °C °C Units V V V V V Power Supplies Power Supply Voltage Ambient Operating Temperature Case Temperature 35 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS ESD: The 92HD66B is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD66B implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or performance. 3.3. 92HD66B Analog Performance Characteristics • 5V AVDD (Tambient = 25 ºC, AVdd = 4.75V (4.5-5.25V), DVdd = 3.3V ± 5% or 1.8V± 10%, AVss=DVss=0V; 20Hz to 20KHz swept sinusoidal input; Sample Frequency = 48 kHz; 0dB FS = 1Vrms for AVdd = 4.75V, 10KΩ//50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages) • 3.3V AVDD (Tambient = 25 ºC, AVdd = 3.3V, DVdd = 3.3V ± 5% or 1.8V ± 10%, AVss=DVss=0V; 20Hz to 20KHz swept sinusoidal input; Sample Frequency = 48 kHz; 0dB FS = 0.707Vrms for AVdd = 3.3V, 10KΩ//50pF load, Testbench Characterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages) Parameter Conditions AVdd Min Typ 24 95 93 98 95 88 83 98 95 88 83 98 95 71 70 Max Unit Bits dB dB dB dB dB dB dB dB dB Digital to Analog Converters Resolution Dynamic Range : PCM to All Analog Outputs 1 All -60dB FS signal level 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V All All All All All All All 5 SNR2 - DAC to All Mono/Line-Out Ports Analog Mixer Disabled, PCM data THD+N3 - DAC to All Mono/Line-Out Ports SNR2 - DAC to All Headphone Ports THD+N3 - DAC to All Headphone Ports SNR2 - DAC to All Headphone Ports THD+N3 - DAC to All Headphone Ports Any Analog Input (ADC) to DAC Crosstalk Any Analog Input (ADC) to DAC Crosstalk DAC L/R crosstalk DAC L/R crosstalk Gain Error Interchannel Gain Mismatch D/A Digital Filter Pass Band4 D/A Digital Filter Pass Band Ripple Table 22. Analog Performance 36 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Analog Mixer Disabled, -3 dB FS Signal, PCM data Analog Mixer Disabled, 10KΩ load, PCM data Analog Mixer Disabled, -3 dB FS Signal, 10Kv load, PCM data Analog Mixer Disabled, 32Ω load, PCM data Analog Mixer Disabled, -3 dB FS Signal, 32Ω load, PCM data 10KHz Signal Frequency 1KHz Signal Frequency DAC to LO or HP 20-15KHz into 10KΩ load DAC to HP 20-15KHz into 32Ω load Analog Mixer Disabled Analog Mixer Disabled -65 -65 -65 -65 70 75 0.5 0.5 20 21,000 0.1 dB dB dB dB Hz +/- dB All V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Parameter D/A Digital Filter Transition Band Conditions AVdd Min 21,00 0 31,00 0 -100 -55 Typ Max 31,000 Unit Hz All D/A Digital Filter Stop Band D/A Digital Filter Stop Band Rejection6 D/A Out-of-Band Rejection7 Group Delay (48KHz sample rate) Attenuation, Gain Step Size DIGITAL DAC Offset Voltage Deviation from Linear Phase All All All All All All All 5V 3.3V 5V 3.3V 5V 3.3V All All Hz dB dB 1 0.75 10 1 20 10 ms dB mV deg. Analog Outputs Full Scale All Mono/Line-Outs Full Scale All Mono/Line-Outs All Headphone Capable Outputs Amplifier output impedance External load Capacitance DAC PCM Data DAC PCM Data 32Ω load Mono/Line Outputs Headphone Outputs Mono/Line Outputs Headphone Outputs 0dB Boost @4.75V (input voltage required for 0dB FS output) 10dB Boost 20dB Boost 30dB Boost 1.00 0.707 2.83 2.00 40 31 60 42 150 0.1 220 Vrms Vp-p mW (peak) Ohms pF Analog Inputs Full Scale Input Voltage All Analog Inputs with boost All Analog Inputs with boost All Analog Inputs with boost Boost Gain Accuracy8 Input Impedance Input Capacitance Table 22. Analog Performance 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V All All All 1.05 0.71 0.320 0.225 0.105 0.071 0.032 0.023 -2 50 15 2 Vrms Vrms Vrms Vrms dB KΩ pF 37 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Parameter Conditions AVdd Min 90 87 85 80 65 60 93 93 85 80 72 72 - Typ Max Unit Analog Mixer Dynamic Range: PCM to All Analog Outputs SNR2 - All Line-In to all Line-Outs THD+N3 - All Line-In to all Line-Out SNR2 - DAC to All Line-Out Ports SNR2 - DAC to All Ports THD+N3 - DAC to All Ports Attenuation, Gain Step Size ANALOG -60dB FS signal level Analog Beep enabled all other mixer inputs mute All inputs unmuted, but only one driven with test signal. 0dBFS Input on one input. All others silent. Analog Beep Enabled, PCM data. all other inputs mute Analog Mixer Enabled, PCM data all other inputs unmuted/silent Analog Mixer Enabled, 0dB FS Signal, PCM data. all other inputs unmuted/silent 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V All All 0dB Boost (input voltage required to generate 0dBFS per AES 17) High Pass Filter Enabled, -60dB FS, No boost 20dB Boost (input voltage required to generate 0dBFS per AES 17) 20dB Boost High Pass Filter Enabled, -60dB FS High Pass Filter enabled, -1/-3 dB FS signal level 20dB Boost, High Pass Filter enabled, -1/-3 dB FS signal level 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V All All All All All All 48 KHz sample rate Table 22. Analog Performance dB dB dB dB dB dB 1.5 24 dB Bits Vrms 93 87 dB Vrms 87 83 83 75 80 75 Analog to Digital Converter Resolution Full Scale Input Voltage Dynamic Range1, All Analog Inputs to A/D Full Scale Input Voltage Dynamic Range1, All Analog Inputs to A/D THD+N All Analog Inputs to A/D THD+N All Analog Inputs to A/D Analog Frequency Response9 A/D Digital Filter Pass Band4 A/D Digital Filter Pass Band Ripple5 A/D Digital Filter Transition Band A/D Digital Filter Stop Band A/D Digital Filter Stop Band Rejection6 Group Delay 1.05 0.71 0.105 0.071 dB dB dB 30,000 21,000 0.1 Hz Hz +/- dB Hz Hz dB 1 ms 10 20 21,00 0 31,00 0 -100 31,000 All 38 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Parameter Any unselected analog Input to ADC Crosstalk Any unselected analog Input to ADC Crosstalk ADC L/R crosstalk DAC to ADC crosstalk Spurious Tone Rejection 10 Conditions AVdd Min -65 -65 -65 -65 Typ Max Unit dB dB dB dB 10KHz Signal Frequency 1KHz Signal Frequency Any selected input to ADC 20-15Khz Any DAC output to ADC 20-15Khz All All All All All All All -100 1.5 0.5 2.8 1.65 35 3.3 1.8 50 -60 -70 25 60 20 34 7 30 7 15 2 7 2 5 1 5 0.4 5 0.4 0.6 4 8 3.8 1.95 dB dB dB V V mA dB dB mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Attenuation, Gain Step Size (analog) Interchannel Gain Mismatch ADC Power Supply Digital Vreg Core Input Voltage Digital Vreg Core Output Voltage Digital Core Vreg Output Current Power Supply Rejection Ratio Power Supply Rejection Ratio D0 Didd11 11 12 10kHz 1kHz 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V All All D0 Aidd D0 Didd D1 Didd D1 Aidd D2 Aidd D2 Didd D0 Aidd12 13 13 D3 (Beep enabled) D3 Didd 13 Didd14 13 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V D3 (Beep enabled) Aidd D3 Aidd13 D3cold Didd D3cold Aidd 13 13 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V 3.3V, 1.8V 5V, 3.3V Table 22. Analog Performance Vendor D4 Didd Vendor D4 Aidd Vendor D5 Didd Vendor D5 Aidd One Stereo ADC Didd One Stereo ADC Aidd 39 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Parameter One Stereo DAC Didd One Stereo DAC Aidd Conditions AVdd Min Typ 4 6 0.5 X AVdd 1.6 0.45 X AVdd 96 150 Max Unit mA mA 3.3V, 1.8V 5V, 3.3V Voltage Reference Outputs VREFOut15 VREFOut Drive16 VREFILT (VAG) All All All V mA V Phased Locked Loop PLL lock time PLL (or Azalia Bit CLK) 24MHz clock jitter All All 200 500 usec psec ESD / Latchup IEC1000-4-2 JESD22-A114-B JESD22-C101 Table 22. Analog Performance All All All 1 2 4 Level Class Class 1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17 as SNR in the presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth. 2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, swept over 20 Hz to 20 kHz bandwidth as required by WLP 3.09. Results at the jack are dependent on external components and will likely be 1 - 2dB worse. 4.48 kHz or 44.1 kHz Sample Frequency. -1dB upper band limit. -3dB lower band limit. 5.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit. 6.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 7.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. 8.Boost gain may be within +/-2dB of target, but actual gain will always ensure that the WLP FSIV requirement will be met and that the boost implementation will not interfere with the +/-0.5dB gain accuracy for the ADC record gain as exposed in the ADC mux widget. 9.± 1dB limits for Line Output & 0 dB gain, at -20dBV 10.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither. 11.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA analog current per stereo 32 ohm headphone. 12.One stereo DAC and corresponding pin widgets enabled (playback mode) 13.Mixer enabled 14.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on) 15.Can be set to 50% or 80% of AVdd. 16.Designed to mimic 80% and 50% of 3.3V. 80% setting is nominal 2.6V, 50% setting is nominal 1.6V 40 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 3.4. Capless Headphone Supply Characteristics Parameter LDO idle current Capless Headphone Amp idle current Charge Pump idle current Charge Pump shutdown time Charge Pump start-up time Frequency C1/C2 cap value Table 23. Capless Headphone Supply Min Typ 1 2 4 1 10 384 2.2 Max 2 3 6 mA mS mS KHz uF Unit mA 3.5. AC Timing Specs 3.5.1. Parameter HD Audio Bus Timing Definition Average BCLK frequency Period of BCLK including jitter High phase of BCLK Low phase of BCLK BCLK jitter Time after rising edge of BCLK that SDI becomes valid Setup for SDO at both rising and falling edges of BCLK Hold for SDO at both rising and falling edges of BCLK T_tco T_su T_h 3 5 5 Tcyc T_high T_low Symbol Min 23.9976 41.163 17.5 17.5 150 Typ 24.0 41.67 Max 24.0024 42.171 24.16 24.16 500 11 Units Mhz ns ns ns ps ns ns ns BCLK Frequency BCLK Period BCLK High Phase BCLK Low Phase BCLK jitter SDI delay SDO setup SDO hold Table 24. HD Audio Bus Timing Figure 8. HD Audio Bus Timing 41 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 3.5.2. Parameter SPDIF_OUT Frequency SPDIF Timing Definition highest rate of encoded signal 64 times the sample rate 1/(128 times the sample rate) SPDIF_OUT jitter T_rise T_fall Table 25. SPDIF Timing UI Symbol Min 2.8224 177.15 Typ 3.072 162.76 Max 12.288 40.69 4.43 15 15 Units MHz ns ns ns ns SPDIF_OUT unit interval SPDIF_OUT jitter SPDIF_OUT rise time SPDIF_OUT fall time 3.5.3. Parameter DMIC_CLK Frequency DMIC_CLK Period DMIC_CLK jitter DMIC Data setup DMIC Data hold Digital Microphone Timing Definition Average DMIC_CLK frequency Period of DMIC_CLK DMIC_CLK jitter Setup for the microphone data at both rising and falling edges of DMIC_CLK Hold for the microphone data at both rising and falling edges of DMIC_CLK Tdmic_su Tdmic_h 5 5 Tdmic_cyc Symbol Min 1.176 850.34 Typ 2.352 425.17 Max 4.704 212.59 5000 Units MHz ns ps ns ns Table 26. Digital Mic timing 3.5.4. Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input rise/fall time Input/Tristate High Leakage Current GPIO Characteristics Definition input level at or above which a 1 is reliably recorded input level at or below which a 0 is reliably recorded VDD may be DVDD or AVDD iout = 4mA VDD may be DVDD or AVDD depending on pin iout = -4mA VDD may be DVDD or AVDD depending on pin transition time between 10% and 90% of supply Vin = VDD VDD may be DVDD or AVDD depending on pin (does not include pull-up or pull-down resistor if present) Symbol Vih Vil Voh Vol T_rise/T_fall 0.9 x VDD 0.1 x VDD 10 Min 0.6 x VDD 0.35 x VDD Typ Max Units V V V V ns 0.5 uA Vin = 0 Input/Tristate Low Leakage VDD may be DVDD or AVDD depending on pin Current (does not include pull-up or pull-down resistor if present) Table 27. GPIO Characteristics -50 uA 42 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 4. COMMON PORT CONFIGURATIONS Consumer Desktop (default configuration) Stereo + RTC + Rear Line/Mic or 5.1 Rear 4Ch C ADC1 LI DAC 1 FRONT ADC1 MIC Front 6Ch ADC1/DAC0 LI / CTR-LFE DAC 1 FRONT ADC1/DAC2 MIC / REAR SURR DAC0 / ADC0 HP / MIC,LI ADC0 / DAC0 MIC,LI / HP A SPDIF_OUT F B SPDIF_IN E Mobile 4 Ch Side A E DAC 0 HP ADC 0 MIC Dock B C DAC 1 HP ADC 1 MIC SPDIF_OUT HDMI/Display Port A M P F DAC 0 EAPD Digital Mic Array Figure 9. Common Port Configurations 43 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5. FUNCTIONAL DIAGRAMS 5.1. 48-pin Package SPDIF IN Stream & Channel Select Digital PC Beep MixerOutVol Analog Beep SPDIF IN to PCM Digital Mute MUX ADC0 ADC1 MUX Pin 45 SPDIF OUT1 GPIO 3 DMIC 1 DAC0 DAC1 MUX Σ HP Boost +0/+10/+20/+30 dB Mic Bias Port A Digital PC Beep MixerOutVol Analog Beep PORT A Pin Complex Pins 28/29/40/41 Stream & Channel Select PCM to SPDIF OUT Digital Mute ADC0 ADC1 Pin 46 SPDIF OUT0 GPIO 0 DMIC 1 MUX MUX Stream & Channel Select PCM to SPDIF OUT Digital Mute Pin 48 DAC0 DAC1 MUX Σ HP Boost +0/+10/+20/+30 dB Mic Bias Port B Digital PC Beep Analog Beep PORT B Pin Complex Pins 31/32/43/44 Vendor Specific Stream & Channel Select MUX vol Digital Mute DAC 0 DAC0 DAC0 DAC1 MUX MixerOutVol MUX Σ LO Boost +0/+10/+20/+30 dB Mic Bias Port C Digital PC Beep MixerOutVol Analog Beep PORT C Pin Complex Pins 19/20 MUX Stream & Channel Select MUX vol Digital Mute DAC 1 DAC1 DAC0 DAC1 MUX Σ LO Boost +0/+10/+20/+30 dB Mic Bias Port E Digital PC Beep Analog Beep PORT E Pin Complex Pins 15/16 Mixer -16 to +30 dB In 1 dB steps HD Audio LINK LOGIC Stream & Channel Select Port B MUX vol Port C Port E Port F DMIC0 DMIC1 Mixer DAC0 DAC1 MUX Port A MixerOutVol MUX Σ HP Boost +0/+10/+20/+30 dB No Bias Port F PORT F Pin Complex Pins 17/18 ADC0 mute Gain -16 to +30 dB In 1 dB steps Stream & Channel Select Port A Port B vol MUX Port C Port E Port F DMIC0 DMIC1 mute mute vol vol vol vol vol vol vol DAC0 DAC1 Port A Port B Port C Port E Port F Digital Microphone volume and mute is done after the ADC but shown here and in widget list as same as analog path. +0/+10/+20/+30 dB DMIC_0 DMIC_1 Boost DMIC DMIC DMIC_0 Pin 4 Pin 46 or 48 Boost +0/+10/+20/+30 dB DMIC_1 ADC1 mute Gain Mixer MixerOutVol mute Vol Σ -34.5 to +12 dB In 1.5 dB steps mute mute mute mute mute -46.5 to 0 dB In 1.5 dB steps Beep_Active Detect/Convert Analog Beep mute vol 0,-6,-12,-18dB To all ports enabled as output Analog PC_BEEP Figure 10. 48-pin Package Functional Diagram 44 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5.2. 40-pin Package MUX Stream & Channel Select Digital Mute MUX ADC0 ADC1 MixerOutVol MUX SPDIF IN to PCM OR PCM to SPDIF OUT SPDIF IN Pin 37 SPDIF OUT1 GPIO 3 DMIC 1 Pin 38 SPDIF OUT0 GPIO 0 DMIC 1 Pin 40 Digital PC Beep Analog Beep DAC0 DAC1 Σ HP Boost +0/+10/+20/+30 dB Mic Bias Stream & Channel Select Digital Mute ADC0 ADC1 SPDIF IN to PCM OR PCM to SPDIF OUT Port A Digital PC Beep MixerOutVol Analog Beep PORT A Pin Complex Pins 21/22/32/33 MUX Stream & Channel Select Digital Mute SPDIF IN to PCM OR PCM to SPDIF OUT MUX DAC0 DAC1 MUX Σ HP Boost +0/+10/+20/+30 dB Mic Bias Port B Digital PC Beep Analog Beep PORT B Pin Complex Pins 24/25/35/36 Vendor Specific Stream & Channel Select MUX vol Digital Mute DAC 0 DAC0 DAC0 DAC1 MUX MixerOutVol MUX Σ LO Boost +0/+10/+20/+30 dB Mic Bias Port C PORT C Pin Complex Pins 14/15 Stream & Channel Select MUX vol Digital Mute DAC 1 DAC1 Digital PC Beep Analog Beep Mixer -16 to +30 dB In 1 dB steps HD Audio LINK LOGIC Stream & Channel Select Port B MUX vol Port C Port F DMIC0 DMIC1 Mixer DAC0 DAC1 MUX Port A MixerOutVol MUX Σ HP Boost +0/+10/+20/+30 dB No Bias Port F PORT F Pin Complex Pins 12/13 ADC0 mute Gain -16 to +30 dB In 1 dB steps Stream & Channel Select Port A Port B vol MUX Port C Port F DMIC0 DMIC1 mute mute vol vol vol vol vol vol DAC0 DAC1 Port A Port B Port C Port F Digital Microphone volume and mute is done after the ADC but shown here and in widget list as same as analog path. +0/+10/+20/+30 dB DMIC_0 DMIC_1 Boost DMIC DMIC DMIC_0 Pin 3 Pin 38 or 40 Boost +0/+10/+20/+30 dB DMIC_1 ADC1 mute Gain Mixer MixerOutVol mute Vol Σ -34.5 to +12 dB In 1.5 dB steps mute mute mute mute -46.5 to 0 dB In 1.5 dB steps Beep_Active Detect/Convert Analog Beep mute vol 0,-6,-12,-18dB To all ports enabled as output Analog PC_BEEP Figure 11. 40-pin Package Functional Diagram 45 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5.3. 48-pin Package Widget Diagram NID = 13h DAC0 -95.25 to 0dB 0.75dB step VOLUME MUTE DAC0 DAC0 DAC1 MixerOutVol Port A DAC0 DAC1 DAC1 MixerOutVol Port B DAC0 DAC1 NID = 0Ah HP IN VOL 10/20/30 Port A BIAS NID = 0Bh HP IN VOL 10/20/30 NID = 14h DAC1 -95.25 to 0dB 0.75dB step VOLUME MUTE Port B BIAS NID = 0Ch LO IN VOL 10/20/30 NID = 23h VSW NID = 17h VOLUME Mute MixerOutVol Port C Port C BIAS NID = 0Dh VSW Mixer Port A Port B Port C Port E Port F DMIC0 DMIC1 DAC0 DAC1 Mixer Port A Port B Port C Port E Port F DMIC0 DMIC1 MixerOutVol Port E DAC0 DAC1 MixerOutVol Port F NID = 15h ADC0 ADC0 MUX DAC0 DAC1 MixerOutVol NID = 19h Mono Mux NID = 1Ah Mono Mix NID = 10h LO -16 to 30dB 1dB step Mono NID = 0Eh LO IN VOL 10/20/30 ADC0 MUX NID = 18h VOLUME Mute Port E BIAS NID = 16h ADC1 HDA Link ADC1 MUX NID = 0Fh HP IN VOL 10/20/30 -16 to 30dB 1dB step Port F ADC1 MUX NID = 1Bh NID = 1Ch MixerOutVol MixerOutVol Mute Volume -46.5 to 0dB in 1.5dB steps NID = 11h VOL Mixer Mute Volume DAC0 DAC1 Port A Port B Port C Port E Port F DMIC0 Analog* DMIC0 10/20/30 Σ -34.5 to +12dB in 1.5dB steps Mute Volume Mute Volume Mute Volume Mute Volume Mute Volume Mute Volume NID = 21h To all ports enabled as an output Digital PC_BEEP PC_BEEP (Pin 12) Mixer To all ports enabled as an output VSV Mute Volume 0,-6,-12,-18dB Vendor Specific Test NID = 1Fh Dig0Pin D NID = 1Dh SPDIF OUT0 Digital ADC0 MUX ADC1 MUX D Vendor Specific Test NID = 20h Dig1Pin D NID = 1Eh SPDIF OUT1 NID = 22h SPDIF IN MUTE Digital ADC0 MUX ADC1 MUX NID = 12h DMIC1 Analog* VOL D DMIC1 VOL (VSW) 10/20/30 Digital Digital D NID = 24h Digital D – Nodes are Digital Capable Dig2Pin D Figure 12. 48-pin Package Widget Diagram 46 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5.4. 40-pin Package Widget Diagram NID = 13h DAC0 -95.25 to 0dB 0.75dB step VOLUME MUTE DAC0 DAC0 DAC1 MixerOutVol Port A DAC0 DAC1 MixerOutVol DAC1 Port B DAC0 DAC1 MixerOutVol NID = 0Ah HP IN VOL 10/20/30 Port A BIAS NID = 0Bh HP IN VOL 10/20/30 NID = 14h DAC1 -95.25 to 0dB 0.75dB step VOLUME MUTE Port B BIAS NID = 0Ch LO IN VOL 10/20/30 Port C BIAS NID = 23h VSW NID = 17h VOLUME Mute Port C NID = 0Dh VSW NID = 15h ADC0 Mixer Port A Port B Port C Port F DMIC0 DMIC1 NID = 19h VSW NID = 1Ah VSW NID = 10h VSW NID = 0Eh VSW NID = 0Fh HP IN VOL 10/20/30 ADC0 MUX -16 to 30dB 1dB step ADC0 MUX NID = 18h VOLUME Mute NID = 16h ADC1 HDA Link Mixer Port A Port B Port C Port F DMIC0 DMIC1 DAC0 DAC1 MixerOutVol Port F ADC1 MUX -16 to 30dB 1dB step Port F ADC1 MUX NID = 1Bh NID = 1Ch MixerOutVol MixerOutVol Mute Volume -46.5 to 0dB in 1.5dB steps NID = 11h VOL Mixer Mute Volume DAC0 DAC1 Port A Port B Port C Port F DMIC0 Analog* DMIC0 10/20/30 Σ -34.5 to +12dB in 1.5dB steps Mute Volume Mute Volume Mute Volume Mute Volume Mute Volume Mute Volume NID = 21h To all ports enabled as an output Digital PC_BEEP PC_BEEP (Pin 12) Mixer To all ports enabled as an output VSV Mute Volume 0,-6,-12,-18dB Vendor Specific Test NID = 1Fh Dig0Pin D NID = 1Dh SPDIF OUT0 Digital ADC0 MUX ADC1 MUX D Vendor Specific Test NID = 20h Dig1Pin D NID = 1Eh SPDIF OUT1 NID = 22h SPDIF IN MUTE Digital ADC0 MUX ADC1 MUX NID = 12h DMIC1 Analog* VOL D DMIC1 VOL (VSW) 10/20/30 Digital Digital D NID = 24h Digital D – Nodes are Digital Capable Dig2Pin D Figure 13. 40-pin Package Widget Diagram 47 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5.5. 48-Pin Configuration Default Register Settings The following table shows the Pin Widget Configuration Default settings. Consumer Desktop 5-jack implementation with 2 jacks in front and 3 jacks in rear. The front panel headphone and mic are dedicated to RTC as suggested by Microsoft. SPDIF_OUT is implemented as an SPDIF optical out jack. SPDIF_In is implemented as an optical input. Digital Microphones are listed as part of the muxed capture device. Pin Name PortAPin PortBPin PortCPin PortEPin PortFPin MonoOutPin DMIC0Pin Dig0Pin Dig1Pin Port Jack 00b Jack 00b Jack 00b Jack 00b Jack 00b No Connect 01b Internal 10b Jack 00b Jack 10b Jack 00b Location Main Front 2h Main Front 2h Main Rear 1h Main Rear 1h Main Rear 1h NA 000000b Internal 010000b Main Rear 000001b Internal 011000b Main Rear 000001b Device HP Out 2h Mic In Ah Line In 8h Mic In Ah Line Out 0h Other Fh Mic In Ah SPDIF Out 4h Digital Other Out 5h SPDIF IN Ch Connection 1/8 inch Jack 1h 1/8 inch Jack 1h 1/8 inch Jack 1h 1/8 inch Jack 1h 1/8 inch Jack 1h Unknown 0h ATAPI 3h optical 5h Other Digital 6h optical 5h Color Green 4h Pink 9h Blue 3h Pink 9h Green 4h Unknown 0h Unknown 0h Black 1h Unknown 0h Gray 2h Misc Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=1 Jack Detect Override=1 Jack Detect Override=1 Jack Detect Override=0 Assoc. Seq 1h 2h 4h 4h 3h Fh 4h 5h 6h 0h 0h Eh 0h 0h 0h 1h 0h 0h Dig2Pin 7h 0h Table 28. Pin Configuration Default Settings 48 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 5.6. 40-Pin Configuration Default Register Settings The following table shows the Pin Widget Configuration Default settings. Common Desktop 4-jack implementation with 2 jacks in front and 2 jacks in rear. The front panel headphone and mic are dedicated to RTC as suggested by Microsoft. SPDIF_OUT is implemented as an SPDIF optical out jack. SPDIF_In is implemented as an optical input. Digital Microphones are listed as part of the muxed capture device. Pin Name PortAPin PortBPin PortCPin PortFPin DMIC0Pin Dig0Pin Dig1Pin Port Jack 00b Jack 00b Jack 00b Jack 00b Internal 10b Jack 00b Jack 10b Jack 00b Location Main Front 2h Main Front 2h Main Rear 1h Main Rear 1h Internal 010000b Main Rear 000001b Internal 011000b Main Rear 000001b Device HP Out 2h Mic In Ah Line In 8h Line Out 0h Mic In Ah SPDIF Out 4h Digital Other Out 5h SPDIF IN Ch Connection 1/8 inch Jack 1h 1/8 inch Jack 1h 1/8 inch Jack 1h 1/8 inch Jack 1h ATAPI 3h optical 5h Other Digital 6h optical 5h Color Green 4h Pink 9h Blue 3h Green 4h Unknown 0h Black 1h Unknown 0h Gray 2h Misc Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=0 Jack Detect Override=1 Jack Detect Override=1 Jack Detect Override=1 Jack Detect Override=0 Assoc. Seq 1h 2h 4h 3h 4h 5h 6h 0h 0h Eh 0h 1h 0h 0h Dig2Pin 7h 0h 49 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6. WIDGET INFORMATION 6.1. Widget List Node ID 48-Pin Package 40-Pin Package 00h 01h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h Root AFG Port A Port B Port C VSW Port E Port F Mono Out DMIC0 VSW (DMIC1 VOL) DAC0 DAC1 ADC0 ADC1 ADC0Mux ADC1Mux MonoMux MonoMix Mixer MixerOutVol SPDIFOut0 SPDIFOut1 Dig0Pin Dig1Pin DigBeep SPDIFIN VSW Dig2Pin Root AFG Port A Port B Port C VSW VSW Port F VSW DMIC0 VSW (DMIC1 VOL) DAC0 DAC1 ADC0 ADC1 ADC0Mux ADC1Mux VSW VSW Mixer MixerOutVol SPDIFOut0 SPDIFOut1 Dig0Pin Dig1Pin DigBeep SPDIFIN VSW Dig2Pin Table 29. High Definition Audio Widget 50 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.2. Widget Descriptions Widget Name Root AFG Port X Port MonoOut DigMic N DACN ADCN ADCNMux Mono Mux Mono Mix Mixer MixerOutVol SPDIFOutN DigNPin PCBeep InPortNMux VSWN Description Root Node Audio Function Group Port X (A, B, Etc.) Pin Widget Port MonoOut Pin Widget (output only) Digital Microphone Pin Widget (N represents the instance) Stereo Output Converter to DAC (N represents the instance) Stereo Input Converter to ADC (N represents the instance) ADC N Mux with volume and mute Mono output source select Stereo to mono conversion Input/Output Mixer (Input Ports, DACs) Volume control for analog mixer Digital Output Converter for SPDIF_Out (N represents the instance) Digital I/O Pin for SPDIF In/Out (N represents the instance) Digital PC Beep Widget Input port pre-select for mixer (N represents the instance) Vendor Specific Widget (N represents the instance) Table 30. Widget Descriptions 6.3. Widget Details Detailed widget information will be provided in a future datasheet update. 6.4. Device IDs 4ch,  40QFN, 1.5V HDA Signaling, 5V AVDD 4ch,  40QFN, 1.5V HDA Signaling, 3.3V AVDD 4ch,  40QFN, 3.3V HDA Signaling, 5V AVDD 4ch,  40QFN, 3.3V HDA Signaling, 3.3V AVDD 4ch,  48QFN, switchable 1.5V or 3.3V HDA Signaling, 5V AVDD 4ch,  48QFN, switchable 1.5V or 3.3V HDA Signaling, 3.3V AVDD 76E8h 76EEh 76E9h 76EFh 76EAh 76F0h 92HD66B1X5NDGXyyX 92HD66B1X3NDGXyyX 92HD66B2X5NDGXyyX 92HD66B2X3NDGXyyX 92HD66B3X5NLGXyyX 92HD66B3X3NLGXyyX 51 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.5. Reset Key Description Power On Reset. Single AFG Reset - One single write to the Reset Verb in the AFG Node. Double AFG Reset - Two consecutive Single AFG Resets with only idle frames (if any) and no Link Resets between. Single And Double AFG Reset - Either one will cause reset. Link Reset - Level sensitive reset anytime the HDA Reset is set low. Exiting Link Reset - Edge sensitive reset any time the HDA Reset transitions from low to high. Unexpected Link Reset - Level sensitive reset anytime the HDA Reset is set low when the ClkStopOK indicator is currently set to 0. Power State Change - Reset anytime the Actual Power State changes for the Widget in question. Abbreviation POR SAFG DAFG S&DAFG LR ELR ULR PS 6.6. Reg Set Get Root (NID = 00h): VendorID Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0000h Field Name Vendor Bits 31:16 Vendor ID. R/W R Default 111Dh Reset N/A DeviceFix 15:8 Device ID. R see below N/A DeviceProg 7:0 Device ID. R see below N/A Device Device ID 92HD66B1X5 92HD66B2X5 92HD66B3X5 92HD66B1X3 92HD66B2X3 92HD66B3X3 76E8h 76E9h 76EAh 76EEh 76EFh 76F0h 52 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.6.1. Reg Set Get Root (NID = 00h): RevID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0002h Field Name Rsvd Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Major 23:20 R 1h N/A (Hard-coded) Major rev number of compliant HD Audio spec. Minor 19:16 R 0h N/A (Hard-coded) Minor rev number of compliant HD Audio spec. RevisionFix 15:12 R xh N/A (Hard-coded) Vendor's rev number for this device. RevisionProg 11:8 R xh N/A (Hard-coded) Vendor's rev number for this device. SteppingFix 7:4 R xh N/A (Hard-coded) Vendor stepping number within the Vendor RevID. SteppingProg 3:0 R xh N/A (Hard-coded) Vendor stepping number within the Vendor RevID. 6.6.2. Reg Set Get Root (NID = 00h): NodeInfo Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0004h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 53 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name StartNID Bits 23:16 R/W R Default 01h Reset N/A (Hard-coded) Starting node number (NID) of first function group Rsvd1 15:8 Reserved. TotalNodes 7:0 R 01h N/A (Hard-coded) R 00h N/A (Hard-coded) Total number of nodes 6.7. Reg Set Get AFG (NID = 01h): NodeInfo Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0004h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) StartNID 23:16 R 0Ah N/A (Hard-coded) Starting node number for function group subordinate nodes. Rsvd1 15:8 Reserved. TotalNodes 7:0 R 1Bh N/A (Hard-coded) R 00h N/A (Hard-coded) Total number of nodes. 6.7.1. Reg Set Get AFG (NID = 01h): FGType Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0005h 54 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:9 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) UnSol 8 R 1h N/A (Hard-coded) Unsolicited response supported: 1 = yes, 0 = no. NodeType 7:0 R 1h N/A (Hard-coded) Function group type: 00h = Reserved 01h = Audio Function Group 02h = Vendor Defined Modem Function Group 03h-7Fh = Reserved 80h-FFh = Vendor Defined Function Group 6.7.2. Reg Set Get AFG (NID = 01h): AFGCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0008h Field Name Rsvd3 Bits 31:17 Reserved. R/W R Default 00h Reset N/A (Hard-coded) BeepGen 16 R 1h N/A (Hard-coded) Beep generator present: 1 = yes, 0 = no. Rsvd2 15:12 Reserved. InputDelay 11:8 R Dh N/A (Hard-coded) R 0h N/A (Hard-coded) Typical latency in frames. Number of samples between when the sample is received as an analog signal at the pin and when the digital representation is transmitted on the HD Audio link. Rsvd1 7:4 Reserved. R 0h N/A (Hard-coded) 55 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name OutputDelay Bits 3:0 R/W R Default Dh Reset N/A (Hard-coded) Typical latency in frames. Number of samples between when the signal is received from the HD Audio link and when it appears as an analog signal at the pin. 6.7.3. Reg Set Get AFG (NID = 01h): PCMCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ah Field Name Rsvd2 Bits 31:21 Reserved. R/W R Default 000h Reset N/A (Hard-coded) B32 20 R 0h N/A (Hard-coded) 32 bit audio format support: 1 = yes, 0 = no. B24 19 R 1h N/A (Hard-coded) 24 bit audio format support: 1 = yes, 0 = no. B20 18 R 1h N/A (Hard-coded) 20 bit audio format support: 1 = yes, 0 = no. B16 17 R 1h N/A (Hard-coded) 16 bit audio format support: 1 = yes, 0 = no. B8 16 R 0h N/A (Hard-coded) 8 bit audio format support: 1 = yes, 0 = no. Rsvd1 15:12 Reserved. R12 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) 384kHz rate support: 1 = yes, 0 = no. R11 10 R 1h N/A (Hard-coded) 192kHz rate support: 1 = yes, 0 = no. 56 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name R10 Bits 9 R/W R Default 0h Reset N/A (Hard-coded) 176.4kHz rate support: 1 = yes, 0 = no. R9 8 R 1h N/A (Hard-coded) 96kHz rate support: 1 = yes, 0 = no. R8 7 R 1h N/A (Hard-coded) 88.2kHz rate support: 1 = yes, 0 = no. R7 6 R 1h N/A (Hard-coded) 48kHz rate support: 1 = yes, 0 = no. R6 5 R 1h N/A (Hard-coded) 44.1kHz rate support: 1 = yes, 0 = no. R5 4 R 0h N/A (Hard-coded) 32kHz rate support: 1 = yes, 0 = no. R4 3 R 0h N/A (Hard-coded) 22.05kHz rate support: 1 = yes, 0 = no. R3 2 R 0h N/A (Hard-coded) 16kHz rate support: 1 = yes, 0 = no. R2 1 R 0h N/A (Hard-coded) 11.025kHz rate support: 1 = yes, 0 = no. R1 0 R 0h N/A (Hard-coded) 8kHz rate support: 1 = yes, 0 = no. 6.7.4. Reg Set Get AFG (NID = 01h): StreamCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Bh 57 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) AC3 2 R 0h N/A (Hard-coded) AC-3 formatted data support: 1 = yes, 0 = no. Float32 1 R 0h N/A (Hard-coded) Float32 formatted data support: 1 = yes, 0 = no. PCM 0 R 1h N/A (Hard-coded) PCM-formatted data support: 1 = yes, 0 = no. 6.7.5. Reg Set Get AFG (NID = 01h): InAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Dh Field Name Mute Bits 31 R/W R Default 0h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 27h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 03h N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 58 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Offset Bits 6:0 R/W R Default 00h Reset N/A (Hard-coded) Indicates which step is 0dB 6.7.6. Reg Set Get AFG (NID = 01h): PwrStateCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Fh Field Name EPSS Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Extended power states support: 1 = yes, 0 = no. ClkStop 30 R 1h N/A (Hard-coded) D3 clock stop support: 1 = yes, 0 = no. LPD3Sup 29 R 1h N/A (Hard-coded) Codec state intended during system S3 state: 1 = D3Hot, 0 = D3Cold. Rsvd 28:5 Reserved. D3ColdSup 4 R 1h N/A (Hard-coded) R 000000h N/A (Hard-coded) D3Cold power state support: 1 = yes, 0 = no. D3Sup 3 R 1h N/A (Hard-coded) D3 power state support: 1 = yes, 0 = no. D2Sup 2 R 1h N/A (Hard-coded) D2 power state support: 1 = yes, 0 = no. D1Sup 1 R 1h N/A (Hard-coded) D1 power state support: 1 = yes, 0 = no. D0Sup 0 R 1h N/A (Hard-coded) D0 power state support: 1 = yes, 0 = no. 59 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.7.7. Reg Set Get AFG (NID = 01h): GPIOCnt Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0011h Field Name GPIWake Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Wake capability. Assuming the Wake Enable Mask controls are enabled, GPIO's configured as inputs can cause a wake (generate a Status Change event on the link) when there is a change in level on the pin. GPIUnsol 30 R 1h N/A (Hard-coded) GPIO unsolicited response support: 1 = yes, 0 = no. Rsvd 29:24 Reserved. NumGPIs 23:16 R 00h N/A (Hard-coded) R 00h N/A (Hard-coded) Number of GPI pins supported by function group. NumGPOs 15:8 R 00h N/A (Hard-coded) Number of GPO pins supported by function group. NumGPIOs 7:0 R 05h N/A (Hard-coded) Number of GPIO pins supported by function group. 6.7.8. Reg Set Get AFG (NID = 01h): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. 60 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd3 Bits 30:23 Reserved. R/W R Default 00h Reset N/A (Hard-coded) StepSize 22:16 R 02h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 7Fh N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 7Fh N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.7.9. Reg Set Get AFG (NID = 01h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd3 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Function Group have been reset. Cleared by PwrState 'Get' to this Widget. ClkStopOK 9 R 1h POR - DAFG - ULR Bit clock can currently be removed: 1 = yes, 0 = no. Error 8 R 0h POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. 61 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 7 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Act 6:4 R 3h POR - DAFG - LR Actual power state of this widget. Rsvd1 3 Reserved. Set 2:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.7.10. Reg Set Get AFG (NID = 01h): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable: 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.7.11. Reg Set Get AFG (NID = 01h): GPIO Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 715h F1500h Byte 4 (Bits 31:24) 62 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Data4 4 RW 0h POR - DAFG - ULR Data for GPIO4. If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing "0". For details of read back value, refer to HD Audio spec. section 7.3.3.22 (Available only on 48-pin versions) Data3 3 RW 0h POR - DAFG - ULR Data for GPIO3. If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing "0". For details of read back value, refer to HD Audio spec. section 7.3.3.22 Data2 2 RW 0h POR - DAFG - ULR Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing "0". For details of read back value, refer to HD Audio spec. section 7.3.3.22 Data1 1 RW 0h POR - DAFG - ULR Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing "0". For details of read back value, refer to HD Audio spec. section 7.3.3.22 Data0 0 RW 0h POR - DAFG - ULR Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input, it can be cleared by writing "0". For details of read back value, refer to HD Audio spec. section 7.3.3.22 6.7.12. Reg Set Get AFG (NID = 01h): GPIOEn Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 716h F1600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) 63 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mask4 Bits 4 R/W RW Default 0h Reset POR - DAFG - ULR Enable for GPIO4: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control (Available only on 48-pin versions) Mask3 3 RW 0h POR - DAFG - ULR Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control Mask2 2 RW 0h POR - DAFG - ULR Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control Mask1 1 RW 0h POR - DAFG - ULR Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control Mask0 0 RW 0h POR - DAFG - ULR Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior determined by GPIO Direction control 6.7.13. Reg Set Get AFG (NID = 01h): GPIODir Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 717h F1700h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Control4 4 RW 0h POR - DAFG - ULR Direction control for GPIO4: 0 = GPIO is configured as input; 1 = GPIO is configured as output (Available only on 48-pin versions) Control3 3 RW 0h POR - DAFG - ULR Direction control for GPIO3: 0 = GPIO is configured as input; 1 = GPIO is configured as output 64 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Control2 Bits 2 R/W RW Default 0h Reset POR - DAFG - ULR Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is configured as output Control1 1 RW 0h POR - DAFG - ULR Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is configured as output Control0 0 RW 0h POR - DAFG - ULR Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is configured as output 6.7.14. Reg Set Get AFG (NID = 01h): GPIOWakeEn Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 718h F1800h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) W4 4 RW 0h POR - DAFG - ULR Wake enable for GPIO4: 0 = wake-up event is disabled; 1 = When HD Audio link is powered down (RST# is asserted), a wake-up event will trigger a Status Change Request event on the link. (Available only on 48-pin versions) W3 3 RW 0h POR - DAFG - ULR Wake enable for GPIO3: 0 = wake-up event is disabled; 1 = When HD Audio link is powered down (RST# is asserted), a wake-up event will trigger a Status Change Request event on the link. W2 2 RW 0h POR - DAFG - ULR Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio link is powered down (RST# is asserted), a wake-up event will trigger a Status Change Request event on the link. 65 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name W1 Bits 1 R/W RW Default 0h Reset POR - DAFG - ULR Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio link is powered down (RST# is asserted), a wake-up event will trigger a Status Change Request event on the link. W0 0 RW 0h POR - DAFG - ULR Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio link is powered down (RST# is asserted), a wake-up event will trigger a Status Change Request event on the link. 6.7.15. Reg Set Get AFG (NID = 01h): GPIOUnsol Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 719h F1900h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) EnMask4 4 RW 0h POR - DAFG - ULR Unsolicited enable mask for GPIO4. If set, and the Unsolicited Response control for this widget has been enabled, an unsolicited response will be sent when GPIO2 is configured as input and changes state. (Available only on 48-pin versions) EnMask3 3 RW 0h POR - DAFG - ULR Unsolicited enable mask for GPIO3. If set, and the Unsolicited Response control for this widget has been enabled, an unsolicited response will be sent when GPIO2 is configured as input and changes state. EnMask2 2 RW 0h POR - DAFG - ULR Unsolicited enable mask for GPIO2. If set, and the Unsolicited Response control for this widget has been enabled, an unsolicited response will be sent when GPIO2 is configured as input and changes state. EnMask1 1 RW 0h POR - DAFG - ULR Unsolicited enable mask for GPIO1. If set, and the Unsolicited Response control for this widget has been enabled, an unsolicited response will be sent when GPIO1 is configured as input and changes state. 66 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name EnMask0 Bits 0 R/W RW Default 0h Reset POR - DAFG - ULR Unsolicited enable mask for GPIO0. If set, and the Unsolicited Response control for this widget has been enabled, an unsolicited response will be sent when GPIO0 is configured as input and changes state. 6.7.16. Reg Set Get AFG (NID = 01h): GPIOSticky Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 71Ah F1A00h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Mask4 4 RW 0h POR - DAFG - ULR GPIO4 input type (when configured as input): 0 = Non-Sticky (level-sensitive); 1 = Sticky (edge-sensitive). (Available only on 48-pin versions) Mask3 3 RW 0h POR - DAFG - ULR GPIO3 input type (when configured as input): 0 = Non-Sticky (level-sensitive); 1 = Sticky (edge-sensitive). Mask2 2 RW 0h POR - DAFG - ULR GPIO2 input type (when configured as input): 0 = Non-Sticky (level-sensitive); 1 = Sticky (edge-sensitive). Mask1 1 RW 0h POR - DAFG - ULR GPIO1 input type (when configured as input): 0 = Non-Sticky (level-sensitive); 1 = Sticky (edge-sensitive). Mask0 0 RW 0h POR - DAFG - ULR GPIO0 input type (when configured as input): 0 = Non-Sticky (level-sensitive); 1 = Sticky (edge-sensitive). 6.7.17. Reg Set AFG (NID = 01h): SubID Byte 3 (Bits 23:16) 722h Byte 4 (Bits 31:24) 723h Byte 2 (Bits 15:8) 721h Byte 1 (Bits 7:0) 720h 67 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.7.17. Reg Get AFG (NID = 01h): SubID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F2300h / F2200h / F2100h / F2000h Field Name Subsys3 Bits 31:24 R/W RW Default 00h Reset POR Subsystem ID (byte 3) Subsys2 23:16 RW 00h POR Subsystem ID (byte 2) Subsys1 15:8 RW 01h POR Subsystem ID (byte 1) Assembly 7:0 RW 00h POR Assembly ID (Not applicable to codec vendors). 6.7.18. Reg Set Get AFG (NID = 01h): GPIOPlrty Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 770h F7000h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) GP4 4 RW 1h POR - DAFG - ULR GPIO4 Polarity: If configured as output or non-sticky input: 0 = inverting 1 = non-inverting If configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected (Available only on 48-pin versions) 68 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name GP3 Bits 3 R/W RW Default 1h Reset POR - DAFG - ULR GPIO3 Polarity: If configured as output or non-sticky input: 0 = inverting 1 = non-inverting If configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected GP2 2 RW 1h POR - DAFG - ULR GPIO2 Polarity: If configured as output or non-sticky input: 0 = inverting 1 = non-inverting If configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected GP1 1 RW 1h POR - DAFG - ULR GPIO1 Polarity: If configured as output or non-sticky input: 0 = inverting 1 = non-inverting If configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected GP0 0 RW 1h POR - DAFG - ULR GPIO0 Polarity: If configured as output or non-sticky input: 0 = inverting 1 = non-inverting If configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected 6.7.19. Reg Set Get AFG (NID = 01h): GPIODrive Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 771h F7100h Byte 4 (Bits 31:24) 69 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:5 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) OD4 4 RW 0h POR - DAFG - ULR GPIO4 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). (Available only on 48-pin versions) OD3 3 RW 0h POR - DAFG - ULR GPIO3 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). OD2 2 RW 0h POR - DAFG - ULR GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). OD1 1 RW 0h POR - DAFG - ULR GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). OD0 0 RW 0h POR - DAFG - ULR GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float for 1). 6.7.20. Reg Set Get AFG (NID = 01h): DMic Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 778h F7800h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:6 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) Mono1 5 RW 0h POR DMic1 mono select: 0 = stereo operation, 1 = mono operation (left channel duplicated to the right channel). 70 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mono0 Bits 4 R/W RW Default 0h Reset POR DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel duplicated to the right channel). PhAdj 3:2 RW 0h POR Selects what phase of the DMic clock the data should be latched: 0h = left data rising edge/right data falling edge 1h = left data center of high/right data center of low 2h = left data falling edge/right data rising edge 3h = left data center of low/right data center of high Rate 1:0 RW 2h POR Selects the DMic clock rate: 0h = 4.704MHz 1h = 3.528MHz 2h = 2.352MHz 3h = 1.176MHz. 6.7.21. Reg Set Get AFG (NID = 01h): DACMode Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 780h F8000h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SDMSettleDisable 7 RW 0h POR SDM wait-to-settle disable: 1 = at mute, the SDM switches to the mute pattern immediately 0 = at mute, the SDM switches to the mute pattern after settling (can take up to ~45ms) SDMCoeffSel 6 RW 0h POR DAC SDM coefficient select (stages 1, 2, 3): 1 = 1/16, 1/2, 1/4 0 = 1/16, 1/4, 1/2 SDMLFHalf 5 RW 0h POR DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048. 71 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SDMLFDisable Bits 4 R/W RW Default 0h Reset POR DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feedback enabled. InvertValid 3 RW 0h POR DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid strobe is not inverted. InvertData 2 RW 0h POR DAC Data Invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not inverted. Atten6dBDisable 1 RW 1h POR Disable built-in -6dB digital attenuation: 1 = -6dB disabled, 0 = -6dB enabled. Fade 0 RW 1h POR DAC Gain Fade Enable: 1 = gain will be slowly faded from old value to new value (~10ms) 0 = gain will jump immediately to new value. 6.7.22. Reg Set Get AFG (NID = 01h): ADCMode Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 784h F8400h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:4 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) InvertValid 3 RW 0h POR ADC Valid Invert: 1 = 14.112MHz valid strobe is inverted, 0 = 14.112MHz valid strobe is not inverted. InvertData 2 RW 0h POR ADC Data Invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted. ADCClkDelay 1 RW 0h POR Delay ADC clock. 72 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name DACClkDelay Bits 0 R/W RW Default 0h Reset POR Delay DAC clock. 6.7.23. Reg Set Get AFG (NID = 01h): PortUse Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7C0h FC000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) Mono 6 RW 1h POR 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable PortF 5 RW 1h POR 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable PortE 4 RW 1h POR 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable (Available only on 48-pin versions) Rsvd1 3 Reserved. PortC 2 RW 1h POR R 0h N/A (Hard-coded) 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable PortB 1 RW 1h POR 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable PortA 0 RW 1h POR 1=power down port if not input or output enabled, 0=do not force power down based on input or output enable. 73 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.7.24. Reg Set Get AFG (NID = 01h): ComJack Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 7C7h FC700h/FC600h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) 7C6h Field Name Rsvd3 Bits 31:14 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) ComJackSupport 11 RW 1h POR Combo Jack support enable, 0 = disable; 1 = enable RbCon 10:8 RW 4h POR Combo jack detection reference voltage 000 = 0.18*AVDD 001 = 0.16*AVDD 010 = 0.14*AVDD 011 = 0.12*AVDD 100 = 0.10*AVDD 101 = 0.08*AVDD 110 = 0.06*AVDD 111 = 0.04*AVDD MasterPort 7:5 RW 0h POR Port tied to the jack presence detection switch 000 = Port A 001 = Port B 010 = Port C 011 = Port D 100 = Port E 101 = Port F Rsvd1 4 Reserved. R 0h N/A (Hard-coded) 74 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SlavePort Bits 3:1 R/W RW Default 0h Reset POR Port used as microphone input When combo jack detection is enabled, Port presence detection as shown in the pin complex is not sensed directly by the sense input but is inferred by the load placed on the Vref_Output associated with the port 010 = Port C;100 = Port E (Available only on 48-pin versions) others revserved. Det_en 0 R 0h POR 0h = disable combo jact detection 1h = enable combo jact detection 6.7.25. Reg Set Get AFG (NID = 01h): ComJackTime Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 7CAh FCA00h / FC900h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) 7C9h Field Name Rsvd3 Bits 31:16 Reserved. R/W R Default 00000h Reset N/A (Hard-coded) bouncetimer_bypass 15 RW 0h POR 0 = all the combjack debounce time in normal; 1= all the comjack debounce time in simulation mode(debounce time is short). t_delay_slave_port_usr 14:12 RW 3h POR 000 = 2frame 001 =4frame 010 =8frame 011 =16frame 100 = 32frame 101 =64frame 110 = 128frame 111 = 256frame 75 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name t_stable Bits 11:8 R/W RW Default 7h Reset POR 0000 = 0.1ms 0001 =0.5ms 0010 =1ms 0011 =2ms 0100 = 4ms 0101 =8ms 0110 = 16ms 0111 = 32ms 1000 = 64ms 1001 =128ms;1010 =256ms;1011 =512ms 1100 = 1024ms 1101 =1024ms 1110 = 1024ms 1111 = 1024ms Rsvd2 7 Reserved. t_long_realtime_detect 6:4 000 = 2s 001 =4s 010 =8s 011 =16s 100 = 32s 101 =64s 110 = 128s 111 = infinite Rsvd1 3 Reserved. t_delay_verfout 2:0 000 = 0.1ms 001 =50ms 010 = 125ms 011 =250ms 100 = 500ms 101 = 1s 110 = 2s 111 = 4s RW 3h POR R 0h N/A (Hard-coded) RW 5h POR R 0h N/A (Hard-coded) 76 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.7.26. Reg Set Get AFG (NID = 01h): VSPwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7D8h FD800h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) D5 1 RW 0h POR - ELR Vendor specific D5 power state, only entered once the part is already in D3cold (this bit must be set before the command to enter D3cold). If set, this bit overrides the D4 bit (bit 0). Includes the power savings of D4, but additionally powers down GPIO pins, the VAG amp, and the HP amps. Exits this power state via POR or rising edge of Link Reset. D4 0 RW 0h POR - ELR Vendor specific D4 power state, only entered once the part is already in D3cold (this bit must be set before the command to enter D3cold). If the D5 bit (bit 1) is set, this bit is overridden. Includes the power savings of D3cold, but additionally powers down the HDA interface (no responses). Exit this power state via POR or rising edge of Link Reset. 6.7.27. Reg Set Get AFG (NID = 01h): AnaPort Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 7EDh FED00h / FEC00h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) 7ECh Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) MonoPwd 6 RW 0h POR Power down Mono Output. (Available only on 48-pin versions) FPwd 5 RW 0h POR Power down Port F 77 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name EPwd Bits 4 R/W RW Default 0h Reset POR Power down Port E (Available only on 48-pin versions) Rsvd1 3 Reserved. CPwd 2 RW 0h POR R 0h N/A (Hard-coded) Power down Port C. BPwd 1 RW 0h POR Power down Port B. APwd 0 RW 0h POR Power down Port A. 78 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.7.28. Reg Set Get AFG (NID = 01h): AnaBeep Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7EEh FEE00h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:9 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Detect 8 R 0h POR - DAFG - ULR 0: no beep present; 1: beep present ConvertEn 7 RW 1h POR analog pc beep quantization enable (enabled only when both d2a_ana_pc_beep_det_en and d2a_ana_pc_beep_convert_en are 1) DetectEn 6 RW 1h POR Analog pc beep detection enable 0h = disable 1h = enable Gain 5:4 RW 3h POR Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB. CntSel 3:2 RW 0h POR Select counter delay.0h=64ms,1h = 128ms, 2h = 256ms, 3h = 512ms. Mode 1:0 RW 2h POR Analog PC Beep Mode: 00b = Always disabled 01b = Always enabled 1Xb = Enabled during HDA Link Reset only 6.7.29. Reg Set Get AFG (NID = 01h): AnaCapless Byte 3 (Bits 23:16) 7FAh Byte 4 (Bits 31:24) 7FBh Byte 2 (Bits 15:8) 7F9h Byte 1 (Bits 7:0) 7F8h FFB00h / FFA00h / FF900h / FF800h 79 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:30 Reserved. R/W R Default 0h Reset N/A (Hard-coded) VRegSCDet 29 R 0h POR Capless regulator short circuit detect indicator. ChargePumpSCDet 28 R 0h POR Capless charge pump short circuit detect indicator. VRegSel 27:24 RW ZA=5h ZB=6h POR Capless regulator output voltage multiply ratio Bits [3..2] Reserved Bits [1..0]: 00b = 2*Vbg 01b = 2.1*Vbg 10b = 2.2*Vbg 11b = 2.3*Vbg VRegSCRstB 23 RW 0h POR Capless regulator short circuit detect reset: 0 = short circuit detect disabled, 1 = short circuit detect enabled. VRegGndShort 22 RW 0h POR Ground the capless regulator output. VRegPwd 21 RW 0h POR Capless regulator powerdown. ChargePumpSCRstB 20 RW 0h POR Capless charge pump short circuit detect reset: 0 = short circuit detect disabled, 1 = short circuit detect enabled. ChargePumpHiZ 19 RW 0h POR Hi-Z the capless charge pump outputs. ChargePumpPwd 18 RW 0h POR Capless charge pump powerdown. ChargePumpSplyDetOverride 17 RW 0h POR Capless charge pump supply detect override. 80 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ChargePumpFreqBypass Bits 16 R/W RW Default 1h Reset POR Capless charge pump frequency reg bypass. ChargePumpClkRate 15:12 RW 8h POR Capless charge pump clock rate: 0000b = 800.0kHz (24MHz/30) 0001b = 750.0kHz (24MHz/32) 0010b = 706.9kHz (24MHz/34) 0011b = 666.7kHz (24MHz/36) 0100b = 631.6kHz (24MHz/38) 0101b = 600.0kHz (24MHz/40) 0110b = 571.4kHz (24MHz/42) 0111b = 545.5kHz (24MHz/44) 1000b = 800.0kHz (24MHz/30) 1001b = 857.1kHz (24MHz/28) 1010b = 923.1kHz (24MHz/26) 1011b = 1.000MHz (24MHz/24) 1100b = 1.091MHz (24MHz/22) 1101b = 1.200MHz (24MHz/20) 1110b = 1.333MHz (24MHz/18) 1111b = 1.500MHz (24MHz/16) ChargePumpClkDiv 11:9 RW 2h POR Capless charge pump analog clock divider: 001b = No divide 010b = Divide by 2, 50% duty cycle 100b = Divide by 4, 50% duty cycle 110b = Divide by 2, 75% duty cycle 011b = Divide by 4, 75% duty cycle 111b = Divide by 4, 87.5% duty cycle Other values undefined ChargePumpClkSel 8 RW 0h POR Capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock defined by AFGCaplessChargePumpClkRate[3:0] field below. PortBPadGnd 7 RW 0h POR Ground the output pad of the capless amplifiers. PortBInputGnd 6 RW 0h POR Ground the input to the capless output amplifiers. Rsvd3 5 Reserved. R 0h N/A (Hard-coded) 81 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortBAntiPopBypass Bits 4 R/W RW Default 0h Reset POR 0 = Enable anti-pop on the capless headphone; 1 = bypass anti-pop on the capless headphone. PortAPadGnd 3 RW 0h NA Ground the output pad of the capless amplifiers. PortAInputGnd 2 RW 0h POR Ground the input to the capless output amplifiers. Rsvd1 1 Reserved. PortAAntiPopBypass 0 RW 0h POR R 0h N/A (Hard-coded) 0 = Enable anti-pop on the capless headphone; 1 = bypass anti-pop on the capless headphone. 6.7.30. Reg Set Get AFG (NID = 01h): Reset Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7FFh FFF00h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Execute 7:0 W 00h N/A (Hard-coded) Function Reset. Function Group reset is executed when the Set verb 7FF is written with 8-bit payload of 00h. The codec should issue a response to acknowledge receipt of the verb, and then reset the affected Function Group and all associated widgets to their power-on reset values. Some controls such as Configuration Default controls should not be reset. Overlaps Response. 82 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.8. Reg Set Get PortA (NID = 0Ah): WCap Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0009h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 4h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 83 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.8.1. Reg Set Get PortA (NID = 0Ah): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 1h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. 84 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name VrefCntrl Bits 15:8 R/W R Default 17h Reset N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 1h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.8.2. Reg Set Get PortA (NID = 0Ah): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 85 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 6.8.3. Reg Set Get PortA (NID = 0Ah): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved. ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.8.4. Reg Set Get PortA (NID = 0Ah): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) 86 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.8.5. Reg Set Get PortA (NID = 0Ah): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.8.6. Reg Set Get PortA (NID = 0Ah): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 87 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.8.7. Reg Set Get PortA (NID = 0Ah): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.8.8. Reg Set Get PortA (NID = 0Ah): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) 88 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) HPhnEn 7 RW 0h POR - DAFG - ULR Headphone amp enable: 1 = enabled, 0 = disabled. OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. InEn 5 RW 0h POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:3 Reserved. VRefEn 2:0 RW 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Vref selection (See VrefCntrl field of PinCap parameter for supported selections): 000b= HI-Z 001b= 50% 010b= GND 011b= Reserved 100b= 80% 101b= 100% 110b= Reserved 111b= Reserved 6.8.9. Reg Set Get PortA (NID = 0Ah): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 89 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name En Bits 7 R/W RW Default 0h Reset POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.8.10. Reg Set Get PortA (NID = 0Ah): ChSense Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.8.11. Reg Set Get PortA (NID = 0Ah): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) 90 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name EAPD Bits 1 R/W RW Default 1h Reset POR - DAFG - ULR EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0 = set EAPD pin to 0. Rsvd1 0 Reserved. R 0h N/A (Hard-coded) 6.8.12. Reg Set Get PortA (NID = 0Ah): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved RW 02h POR 91 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Device Bits 23:20 R/W RW Default 2h Reset POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other ConnectionType 19:16 RW 1h POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other 92 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Color Bits 15:12 R/W RW Default 4h Reset POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 1h POR Default assocation. Sequence 3:0 Sequence. RW 0h POR 6.9. Reg Set Get PortB (NID = 0Bh): WCap Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0009h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 93 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 4h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 94 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 0h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.9.1. Reg Set Get PortB (NID = 0Bh): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 1h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. VrefCntrl 15:8 R 17h N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 95 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BalancedIO Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 1h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.9.2. Reg Set Get PortB (NID = 0Bh): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 96 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.9.3. Reg Set Get PortB (NID = 0Bh): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved. ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.9.4. Reg Set Get PortB (NID = 0Bh): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget. 97 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.9.5. Reg Set Get PortB (NID = 0Bh): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget. 6.9.6. Reg Set Get PortB (NID = 0Bh): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 6.9.7. Reg Set Get PortB (NID = 0Bh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 98 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SettingsReset Bits 10 R/W R Default 1h Reset POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.9.8. Reg Set Get PortB (NID = 0Bh): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) HPhnEn 7 RW 0h POR - DAFG - ULR Headphone amp enable: 1 = enabled, 0 = disabled. OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. 99 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name InEn Bits 5 R/W RW Default 0h Reset POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:3 Reserved. VRefEn 2:0 RW 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Vref selection (See VrefCntrl field of PinCap parameter for supported selections): 000b= HI-Z 001b= 50% 010b= GND 011b= Reserved 100b= 80% 101b= 100% 110b= Reserved 111b= Reserved 6.9.9. Reg Set Get PortB (NID = 0Bh): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 100 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.9.10. Reg Set Get PortB (NID = 0Bh): ChSense Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.9.11. Reg Set Get PortB (NID = 0Bh): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) EAPD 1 RW 1h POR - DAFG - ULR EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0 = set EAPD pin to 0. Rsvd1 0 Reserved. R 0h N/A (Hard-coded) 6.9.12. Reg Set Get PortB (NID = 0Bh): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h 101 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved Device 23:20 RW Ah POR RW 02h POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other 102 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnectionType Bits 19:16 R/W RW Default 1h Reset POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other Color 15:12 RW 9h POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 2h POR Default association. Sequence 3:0 Sequence. RW 0h POR 103 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.10. PortC (NID = 0Ch): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 4h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 104 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.10.1. Reg Set Get PortC (NID = 0Ch): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 1h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. 105 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name VrefCntrl Bits 15:8 R/W R Default 17h Reset N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.10.2. Reg Set Get PortC (NID = 0Ch): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 106 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 6.10.3. Reg Set Get PortC (NID = 0Ch): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 converter widget (0x23) on 92HD66C. 92HD66B this is reserved. ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.10.4. Reg Set Get PortC (NID = 0Ch): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) 107 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.10.5. Reg Set Get PortC (NID = 0Ch): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.10.6. Reg Set Get PortC (NID = 0Ch): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 108 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.10.7. Reg Set Get PortC (NID = 0Ch): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.10.8. Reg Set Get PortC (NID = 0Ch): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) 109 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. InEn 5 RW 0h POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:3 Reserved. VRefEn 2:0 RW 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Vref selection (See VrefCntrl field of PinCap parameter for supported selections): 000b= HI-Z 001b= 50% 010b= GND 011b= Reserved 100b= 80% 101b= 100% 110b= Reserved 111b= Reserved 6.10.9. Reg Set Get PortC (NID = 0Ch): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. 110 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 6 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Tag 5:0 RW 00h POR - DAFG - ULR Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.10.10. PortC (NID = 0Ch): ChSense Reg Set Get F0900h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.10.11. PortC (NID = 0Ch): EAPDBTLLR Reg Set Get F0C00h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) EAPD 1 RW 1h POR - DAFG - ULR EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0 = set EAPD pin to 0. 111 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 0 Reserved. R/W R Default 0h Reset N/A (Hard-coded) 6.10.12. PortC (NID = 0Ch): ConfigDefault Reg Set Get Byte 4 (Bits 31:24) 71Fh Byte 3 (Bits 23:16) 71Eh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved RW 01h POR 112 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Device Bits 23:20 R/W RW Default 8h Reset POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other ConnectionType 19:16 RW 1h POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other 113 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Color Bits 15:12 R/W RW Default 3h Reset POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 4h POR Default association. Sequence 3:0 Sequence. RW Eh POR 6.11. NID = 0Dh Reserved 6.12. PortE (NID = 0Eh): WCap (Available only on 48-pin versions) Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 114 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 4h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 115 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 0h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.12.1. Reg Set Get PortE (NID = 0Eh): PinCap (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 1h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. VrefCntrl 15:8 R 17h N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 116 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BalancedIO Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.12.2. Reg Set Get PortE (NID = 0Eh): ConLst (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 117 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.12.3. Reg Set Get PortE (NID = 0Eh): ConLstEntry0 (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved. ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.12.4. Reg Set Get PortE (NID = 0Eh): InAmpLeft (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.12.5. Reg Set PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h Byte 4 (Bits 31:24) 118 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.12.5. Reg Get PortE (NID = 0Eh): InAmpRight (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) B0000h Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.12.6. Reg Set Get PortE (NID = 0Eh): ConSelectCtrl (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 6.12.7. Reg Set Get PortE (NID = 0Eh): PwrState (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 119 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SettingsReset Bits 10 R/W R Default 1h Reset POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.12.8. Reg Set Get PortE (NID = 0Eh): PinWCntrl (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. InEn 5 RW 0h N/A (Hard-coded) Input enable: 1 = enabled, 0 = disabled. 120 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 4:3 Reserved. R/W R Default 0h Reset N/A (Hard-coded) VRefEn 2:0 RW 0h POR - DAFG - ULR Vref selection (See VrefCntrl field of PinCap parameter for supported selections): 000b= HI-Z 001b= 50% 010b= GND 011b= Reserved 100b= 80% 101b= 100% 110b= Reserved 111b= Reserved. 6.12.9. Reg Set Get PortE (NID = 0Eh): UnsolResp (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.12.10. PortE (NID = 0Eh): ChSense (Available only on 48-pin versions) Reg Set 121 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.12.10. PortE (NID = 0Eh): ChSense (Available only on 48-pin versions) Reg Get Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0900h Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.12.11. PortE (NID = 0Eh): EAPDBTLLR (Available only on 48-pin versions) Reg Set Get F0C00h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) EAPD 1 RW 1h POR - DAFG - ULR EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0 = set EAPD pin to 0. Rsvd1 0 Reserved. R 0h N/A (Hard-coded) 6.12.12. PortE (NID = 0Eh): ConfigDefault (Available only on 48-pin versions) Reg Set Get Byte 4 (Bits 31:24) 71Fh Byte 3 (Bits 23:16) 71Eh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h 122 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved Device 23:20 RW Ah POR RW 01h POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other 123 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnectionType Bits 19:16 R/W RW Default 1h Reset POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other Color 15:12 RW 9h POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 4h POR Default association. Sequence 3:0 Sequence. RW 0h POR 124 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.13. PortF (NID = 0Fh): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 4h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 125 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.13.1. Reg Set Get PortF (NID = 0Fh): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 1h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. 126 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name VrefCntrl Bits 15:8 R/W R Default 00h Reset N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 1h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.13.2. Reg Set Get PortF (NID = 0Fh): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 127 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 6.13.3. Reg Set Get PortF (NID = 0Fh): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved. ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.13.4. Reg Set Get PortF (NID = 0Fh): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) 128 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.13.5. Reg Set Get PortF (NID = 0Fh): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.13.6. Reg Set Get PortF (NID = 0Fh): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 129 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.13.7. Reg Set Get PortF (NID = 0Fh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.13.8. Reg Set Get PortF (NID = 0Fh): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) 130 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) HPhnEn 7 RW 0h POR - DAFG - ULR Headphone amp enable: 1 = enabled, 0 = disabled. OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. InEn 5 RW 0h POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:0 Reserved. R 0h N/A (Hard-coded) 6.13.9. Reg Set Get PortF (NID = 0Fh): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 131 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.13.10. PortF (NID = 0Fh): ChSense Reg Set Get F0900h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.13.11. PortF (NID = 0Fh): EAPDBTLLR Reg Set Get F0C00h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) EAPD 1 RW 1h POR - DAFG - ULR EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0 = set EAPD pin to 0. Rsvd1 0 Reserved. R 0h N/A (Hard-coded) 6.13.12. PortF (NID = 0Fh): ConfigDefault Reg Set Get Byte 4 (Bits 31:24) 71Fh Byte 3 (Bits 23:16) 71Eh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h 132 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved Device 23:20 RW 0h POR RW 01h POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other 133 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnectionType Bits 19:16 R/W RW Default 1h Reset POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other Color 15:12 RW 4h POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 3h POR Default association. Sequence 3:0 Sequence. RW 0h POR 134 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.14. MonoOut (NID = 10h): WCap (Available only on 48-pin versions) Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 4h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 135 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 0h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.14.1. Reg Set Get MonoOut (NID = 10h): PinCap (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 0h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. 136 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name VrefCntrl Bits 15:8 R/W R Default 00h Reset N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 0h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.14.2. Reg Set Get MonoOut (NID = 10h): ConLst (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 137 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.14.3. Reg Set Get MonoOut (NID = 10h): ConLstEntry0 (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 1Ah N/A (Hard-coded) MonoMix Summing widget (0x1A) 6.14.4. Reg Set Get MonoOut (NID = 10h): PwrState (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) 138 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.14.5. Reg Set Get MonoOut (NID = 10h): PinWCntrl (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. 139 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 5:0 Reserved. R/W R Default 0h Reset N/A (Hard-coded) 6.14.6. Reg Set Get MonoOut (NID = 10h): UnsolResp (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.14.7. Reg Set Get MonoOut (NID = 10h): ChSense (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. 140 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B R 00000000h N/A (Hard-coded) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.14.8. Reg Set Get MonoOut (NID = 10h): ConfigDefault (Available only on 48-pin versions) Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h Field Name PortConnectivity Bits 31:30 R/W RW Default 1h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved RW 00h POR 141 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Device Bits 23:20 R/W RW Default Fh Reset POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other ConnectionType 19:16 RW 0h POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other 142 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Color Bits 15:12 R/W RW Default 0h Reset POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW Fh POR Default assocation. Sequence 3:0 Sequence. RW 0h POR 6.15. DMic0 (NID = 11h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 143 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 4h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. DigitalStrm 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnsolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 144 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 0h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.15.1. Reg Set Get DMic0 (NID = 11h): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 0h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. VRefCntrl 15:8 R 00h N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 145 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BalancedIO Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 0h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HPhnDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 0h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.15.2. Reg Set Get DMic0 (NID = 11h): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.15.3. Reg Set DMic0 (NID = 11h): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h Byte 4 (Bits 31:24) 146 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.15.3. Reg Get DMic0 (NID = 11h): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) B0000h Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.15.4. Reg Set Get DMic0 (NID = 11h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. 147 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 3:2 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Set 1:0 RW 0h POR - DAFG - LR Current power state setting for this widget. 6.15.5. Reg Set Get DMic0 (NID = 11h): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:6 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) InEn 5 RW 0h POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:0 Reserved. R 00h N/A (Hard-coded) 6.15.6. Reg Set Get DMic0 (NID = 11h): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h 148 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortConnectivity Bits 31:30 R/W RW Default 2h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved Device 23:20 RW Ah POR RW 10h POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other 149 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnectionType Bits 19:16 R/W RW Default 3h Reset POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other Color 15:12 RW 0h POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 1h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 4h POR Default assocation. Sequence 3:0 Sequence. RW 1h POR 150 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.16. DMic1Vol (NID = 12h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R Fh N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. DigitalStrm 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnsolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 151 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.16.1. Reg Set Get DMic1Vol (NID = 12h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 02h N/A (Hard-coded) Number of NID entries in connection list. 152 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.16.2. Reg Set Get DMic1Vol (NID = 12h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 20h N/A (Hard-coded) Dig1Pin Pin widget (0x20) ConL0 7:0 R 1Fh N/A (Hard-coded) Dig1Pin Pin widget (0x1F) 6.16.3. Reg Set Get DMic1Vol (NID = 12h): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.16.4. Reg Set Get DMic1Vol (NID = 12h): InAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h 153 V 1.0 2/12 92HD66B Byte 4 (Bits 31:24) ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 31:2 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Gain 1:0 RW 0h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.16.5. Reg Set Get DMic1Vol (NID = 12h): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:1 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 0 RW 0h POR - DAFG - ULR Connection select control index. 6.16.6. Reg Set Get DMic1Vol (NID = 12h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. 154 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B R 0h N/A (Hard-coded) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Error Bits 8 R/W R Default 0h Reset POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.17. DAC0 (NID = 13h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 0h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined 155 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Delay Bits 19:16 R/W R Default Dh Reset N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 1h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 156 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.17.1. Reg Set Get DAC0 (NID = 13h): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) StrmType 15 R 0h N/A (Hard-coded) Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. SmplRateMultp 13:11 RW 0h POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 157 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BitsPerSmpl Bits 6:4 R/W RW Default 3h Reset POR - DAFG - ULR Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.17.2. Reg Set Get DAC0 (NID = 13h): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Gain 6:0 RW 7Fh POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.17.3. Reg Set Get DAC0 (NID = 13h): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) 158 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Gain 6:0 RW 7Fh POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.17.4. Reg Set Get DAC0 (NID = 13h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. R 0h N/A (Hard-coded) 159 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Set Bits 1:0 R/W RW Default 3h Reset POR - DAFG - LR Current power state setting for this widget. 6.17.5. Reg Set Get DAC0 (NID = 13h): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 6.17.6. Reg Set Get DAC0 (NID = 13h): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) SwapEn 2 RW 0h POR - DAFG - ULR Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled. Rsvd1 1:0 Reserved. 160 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B R 0h N/A (Hard-coded) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.18. DAC1 (NID = 14h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 0h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R Dh N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 1h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 161 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.18.1. Reg Set Get DAC1 (NID = 14h): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) StrmType 15 R 0h N/A (Hard-coded) Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. 162 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SmplRateMultp Bits 13:11 R/W RW Default 0h Reset POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.18.2. Reg Set Get DAC1 (NID = 14h): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) 163 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Gain 6:0 RW 7Fh POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.18.3. Reg Set Get DAC1 (NID = 14h): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Gain 6:0 RW 7Fh POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.18.4. Reg Set Get DAC1 (NID = 14h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 164 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SettingsReset Bits 10 R/W R Default 1h Reset POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.18.5. Reg Set Get DAC1 (NID = 14h): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 165 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.18.6. Reg Set Get DAC1 (NID = 14h): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) SwapEn 2 RW 0h POR - DAFG - ULR Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled. Rsvd1 1:0 Reserved. R 0h N/A (Hard-coded) 6.19. ADC0 (NID = 15h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 1h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined 166 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Delay Bits 19:16 R/W R Default Dh Reset N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 1h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 167 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.19.1. Reg Set Get ADC0 (NID = 15h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.19.2. Reg Set Get ADC0 (NID = 15h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 17h N/A (Hard-coded) ADC0Mux Selector widget (0x17) 168 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.19.3. Reg Set Get ADC0 (NID = 15h): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) StrmType 15 R 0h N/A (Hard-coded) Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. SmplRateMultp 13:11 RW 0h POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 169 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BitsPerSmpl Bits 6:4 R/W RW Default 3h Reset POR - DAFG - ULR Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.19.4. Reg Set Get ADC0 (NID = 15h): ProcState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 703h F0300h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) HPFOCDIS 7 RW 0h POR - DAFG - ULR HPF offset calculation disable. 1 = calculation disabled; 0 = calculation enabled. Rsvd1 6:2 Reserved. ADCHPFByp 1:0 RW 1h POR - DAFG - ULR R 00h N/A (Hard-coded) Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is enabled ("on" or "benign"). 6.19.5. Reg Set Get ADC0 (NID = 15h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) 170 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.19.6. Reg Set Get ADC0 (NID = 15h): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. 171 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Ch Bits 3:0 R/W RW Default 0h Reset POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 6.20. ADC1 (NID = 1Bh): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 1h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R Dh N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. 172 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Dig Bits 9 R/W R Default 0h Reset N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 1h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.20.1. Reg Set Get ADC1 (NID = 1Bh): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 173 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.20.2. Reg Set Get ADC1 (NID = 1Bh): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 18h N/A (Hard-coded) ADC1Mux widget (0x18) 6.20.3. Reg Set Get ADC1 (NID = 1Bh): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) 174 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) StrmType 15 R 0h N/A (Hard-coded) Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. SmplRateMultp 13:11 RW 0h POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 175 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.20.4. Reg Set Get ADC1 (NID = 1Bh): ProcState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 703h F0300h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) HPFOCDIS 7 RW 0h POR - DAFG - ULR HPF offset calculation disable. 1 = calculation disabled; 0 = calculation enabled. Rsvd1 6:2 Reserved. ADCHPFByp 1:0 RW 1h POR - DAFG - ULR R 00h N/A (Hard-coded) Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is enabled ("on" or "benign"). 6.20.5. Reg Set Get ADC1 (NID = 1Bh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. R 0h N/A (Hard-coded) 176 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Error Bits 8 R/W R Default 0h Reset POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.20.6. Reg Set Get ADC1 (NID = 1Bh): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 6.21. ADC0Mux (NID = 17h): WCap Reg Set Get F0009h 177 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 3h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 1h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. DigitalStrm 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnsolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. 178 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name FormatOvrd Bits 4 R/W R Default 0h Reset N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParamOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.21.1. Reg Set Get ADC0Mux (NID = 17h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 08h N/A (Hard-coded) Number of NID entries in connection list 6.21.2. Reg Set Get ADC0Mux (NID = 17h): ConLstEntry4 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0204h 179 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL7 Bits 31:24 R/W R Default 0Eh Reset N/A (Hard-coded) Port E Pin widget (0x0E) (Available only on 48-pin versions) ConL6 23:16 R 12h N/A (Hard-coded) Port DMIC1 widget (0x12) ConL5 15:8 R 11h N/A (Hard-coded) Port DMIC0 widget (0x11) ConL4 7:0 R 0Fh N/A (Hard-coded) Port F Pin widget (0x0F) 6.21.3. Reg Set Get ADC0Mux (NID = 17h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 0Ch Reset N/A (Hard-coded) Port C Pin widget (0x0C) ConL2 23:16 R 0Bh N/A (Hard-coded) Port B Pin widget (0x0B ConL1 15:8 R 0Ah N/A (Hard-coded) Port A Pin widget (0x0A) ConL0 7:0 R 1Bh N/A (Hard-coded) Mixer Summing widget (0x1B) 6.21.4. Reg Set Get ADC0Mux (NID = 17h): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h 180 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 03h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 2Eh N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 10h N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.21.5. Reg Set Get ADC0Mux (NID = 17h): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6 Reserved. R 0h N/A (Hard-coded) 181 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Gain Bits 5:0 R/W RW Default 10h Reset POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.21.6. Reg Set Get ADC0Mux (NID = 17h): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6 Reserved. Gain 5:0 RW 10h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.21.7. Reg Set Get ADC0Mux (NID = 17h): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 2:0 RW 0h POR - DAFG - ULR Connection select control index. 182 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.21.8. Reg Set Get ADC0Mux (NID = 17h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.21.9. Reg Set Get ADC0Mux (NID = 17h): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) 183 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) SwapEn 2 RW 0h POR - DAFG - ULR Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled. Rsvd1 1:0 Reserved. R 0h N/A (Hard-coded) 6.22. ADC1Mux (NID = 18h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 3h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. R 0h N/A (Hard-coded) 184 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SwapCap Bits 11 R/W R Default 1h Reset N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. DigitalStrm 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnsolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParamOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.22.1. Reg Set Get ADC1Mux (NID = 18h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 185 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 08h N/A (Hard-coded) Number of NID entries in connection list. 6.22.2. Reg Set Get ADC1Mux (NID = 18h): ConLstEntry4 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0204h Field Name ConL7 Bits 31:24 R/W R Default 0Eh Reset N/A (Hard-coded) Port E Pin widget (0x0E) (Available only on 48-pin versions). ConL6 23:16 R 12h N/A (Hard-coded) Port DMIC1 widget (0x12). ConL5 15:8 R 11h N/A (Hard-coded) Port DMIC0 widget (0x11) ConL4 7:0 R 0Fh N/A (Hard-coded) Port F Pin widget (0x0F) 6.22.3. Reg Set Get ADC1Mux (NID = 18h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h 186 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL3 Bits 31:24 R/W R Default 0Ch Reset N/A (Hard-coded) Port C Pin widget (0x0C) ConL2 23:16 R 0Bh N/A (Hard-coded) Port B Pin widget (0x0B) ConL1 15:8 R 0Ah N/A (Hard-coded) Port A Pin widget (0x0A) ConL0 7:0 R 1Bh N/A (Hard-coded) Mixer Summing widget (0x1B) 6.22.4. Reg Set Get ADC1Mux (NID = 18h): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 03h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 2Eh N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 187 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Offset Bits 6:0 R/W R Default 10h Reset N/A (Hard-coded) Indicates which step is 0dB 6.22.5. Reg Set Get ADC1Mux (NID = 18h): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6 Reserved. Gain 5:0 RW 10h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.22.6. Reg Set Get ADC1Mux (NID = 18h): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. 188 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 6 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Gain 5:0 RW 10h POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.22.7. Reg Set Get ADC1Mux (NID = 18h): ConSelectCtrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) Index 2:0 RW 0h POR - DAFG - ULR Connection select control index. 6.22.8. Reg Set Get ADC1Mux (NID = 18h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. 189 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B R 0h N/A (Hard-coded) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Error Bits 8 R/W R Default 0h Reset POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.22.9. Reg Set Get ADC1Mux (NID = 18h): EAPDBTLLR Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ch F0C00h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) SwapEn 2 RW 0h POR - DAFG - ULR Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled. Rsvd1 1:0 Reserved. R 0h N/A (Hard-coded) 6.23. MonoMux (NID = 19h): WCap (Available only on 48-pin versions) Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 190 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 3h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. 191 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name FormatOvrd Bits 4 R/W R Default 0h Reset N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.23.1. Reg Set Get MonoMux (NID = 19h): ConLst (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 04h N/A (Hard-coded) Number of NID entries in connection list. 6.23.2. Reg Set Get MonoMux (NID = 19h): ConLstEntry0 (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h 192 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL3 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 Converter widget (0x23) on 92HD66C. 92HD66B this is reserved ConL2 23:16 R 1Ch N/A (Hard-coded) MixerOutVol Selector widget (0x1C) ConL1 15:8 R 14h N/A (Hard-coded) DAC1 Converter widget (0x14) ConL0 7:0 R 13h N/A (Hard-coded) DAC0 Converter widget (0x13) 6.23.3. Reg Set Get MonoMux (NID = 19h): ConSelectCtrl (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 701h F0100h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:2 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) Index 1:0 RW 0h POR - DAFG - ULR Connection select control index. 6.23.4. Reg Set Get MonoMux (NID = 19h): PwrState (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) 193 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.24. MonoMix (NID = 1Ah): WCap (Available only on 48-pin versions) Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 194 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 2h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 195 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 0h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 0h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.24.1. Reg Set Get MonoMix (NID = 1Ah): ConLst (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.24.2. Reg Set Get MonoMix (NID = 1Ah): ConLstEntry0 (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h 196 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 19h N/A (Hard-coded) MonoMux Selector widget (0x19) 6.24.3. Reg Set Get MonoMix (NID = 1Ah): PwrState (Available only on 48-pin versions) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. 197 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 3:2 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Set 1:0 RW 0h POR - DAFG - LR Current power state setting for this widget. 6.25. Mixer (NID = 1Bh): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 2h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. 198 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Dig Bits 9 R/W R Default 0h Reset N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.25.1. Reg Set Get Mixer (NID = 1Bh): InAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Dh 199 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 05h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 1Fh N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 17h N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.25.2. Reg Set Get Mixer (NID = 1Bh): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 08h N/A (Hard-coded) Number of NID entries in connection list. 200 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.25.3. Reg Set Get Mixer (NID = 1Bh): ConLstEntry4 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0204h Field Name ConL7 Bits 31:24 R/W R Default 23h Reset N/A (Hard-coded) DAC2 widget (0x23) on 92HD66C. 92HD66B this is reserved. Uses InAmpLeft7/InAmpRight7 controls ConL6 23:16 R 0Eh N/A (Hard-coded) Port E Pin widget (0x0E). Uses InAmpLeft6/InAmpRight6 controls (Available only on 48-pin versions) ConL5 15:8 R 0Fh N/A (Hard-coded) Port F Pin widget (0x0F). Uses InAmpLeft5/InAmpRight5 controls ConL4 7:0 R 0Ch N/A (Hard-coded) Port C Pin widget (0x0C). Uses InAmpLeft4/InAmpRight4 controls 6.25.4. Reg Set Get Mixer (NID = 1Bh): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 0Bh Reset N/A (Hard-coded) Port B Pin widget (0x0B). Uses InAmpLeft3/InAmpRight3 controls. ConL2 23:16 R 0Ah N/A (Hard-coded) Port A Pin widget (0x0A). Uses InAmpLeft2/InAmpRight2 controls. ConL1 15:8 R 14h N/A (Hard-coded) DAC1 widget (0x14). Uses InAmpLeft1/InAmpRight1 controls. 201 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL0 Bits 7:0 R/W R Default 13h Reset N/A (Hard-coded) DAC0 widget (0x13). Uses InAmpLeft0/InAmpRight0 controls. 6.25.5. Reg Set Get Mixer (NID = 1Bh): InAmpLeft0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.6. Reg Set Get Mixer (NID = 1Bh): InAmpRight0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h B0000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. 202 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 6:5 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Gain 4:0 RW 17h POR - DAFG - ULR Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.7. Reg Set Get Mixer (NID = 1Bh): InAmpLeft1 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 361h B2001h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.8. Reg Set Get Mixer (NID = 1Bh): InAmpRight1 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 351h B0001h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 203 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mute Bits 7 R/W RW Default 1h Reset POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.9. Reg Set Get Mixer (NID = 1Bh): InAmpLeft2 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 362h B2002h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.10. Mixer (NID = 1Bh): InAmpRight2 Reg Set Get B0002h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 352h 204 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.11. Mixer (NID = 1Bh): InAmpLeft3 Reg Set Get B2003h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 363h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.12. Mixer (NID = 1Bh): InAmpRight3 Reg Set Get B0003h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 353h 205 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.13. Mixer (NID = 1Bh): InAmpLeft4 Reg Set Get B2004h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 364h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.14. Mixer (NID = 1Bh): InAmpRight4 Reg Set Get B0004h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 354h 206 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.15. Mixer (NID = 1Bh): InAmpLeft5 Reg Set Get B2005h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 365h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.16. Mixer (NID = 1Bh): InAmpRight5 Reg Set Get B0005h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 355h 207 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.17. Mixer (NID = 1Bh): InAmpLeft6 Reg Set Get B2006h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 366h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 208 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.25.18. Mixer (NID = 1Bh): InAmpRight6 Reg Set Get B0006h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 356h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.19. Mixer (NID = 1Bh): InAmpLeft7 Reg Set Get B2007h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 367h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 209 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.25.20. Mixer (NID = 1Bh): InAmpRight7 Reg Set Get B0007h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 357h Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 17h POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see InAmpCap parameter pertaining to this widget). 6.25.21. Mixer (NID = 1Bh): PwrState Reg Set Get F0500h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. 210 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 7:6 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Act 5:4 R 3h POR - DAFG - LR Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.26. MixerOutVol (NID = 1Ch): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 3h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. R 0h N/A (Hard-coded) 211 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SwapCap Bits 11 R/W R Default 0h Reset N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 0h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.26.1. Reg Set Get MixerOutVol (NID = 1Ch): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 212 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.26.2. Reg Set Get MixerOutVol (NID = 1Ch): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 1Bh N/A (Hard-coded) Mixer Summing widget (0x1B) 6.26.3. Reg Set Get MixerOutVol (NID = 1Ch): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h 213 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 05h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 1Fh N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 1Fh N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.26.4. Reg Set Get MixerOutVol (NID = 1Ch): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. R 0h N/A (Hard-coded) 214 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Gain Bits 4:0 R/W RW Default 1Fh Reset POR - DAFG - ULR Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.26.5. Reg Set Get MixerOutVol (NID = 1Ch): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 1h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:5 Reserved. Gain 4:0 RW 1Fh POR - DAFG - ULR R 0h N/A (Hard-coded) Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.26.6. Reg Set Get MixerOutVol (NID = 1Ch): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. 215 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd3 Bits 9 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Error 8 R 0h POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.27. SPDIFOut0 (NID = 1Dh): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 216 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 0h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 4h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 1h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 217 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 1h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.27.1. Reg Set Get SPDIFOut0 (NID = 1Dh): PCMCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ah Field Name Rsvd2 Bits 31:21 Reserved. R/W R Default 000h Reset N/A (Hard-coded) B32 20 R 0h N/A (Hard-coded) 32 bit audio format support: 1 = yes, 0 = no. B24 19 R 1h N/A (Hard-coded) 24 bit audio format support: 1 = yes, 0 = no. B20 18 R 1h N/A (Hard-coded) 20 bit audio format support: 1 = yes, 0 = no. B16 17 R 1h N/A (Hard-coded) 16 bit audio format support: 1 = yes, 0 = no. B8 16 R 0h N/A (Hard-coded) 8 bit audio format support: 1 = yes, 0 = no. 218 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 15:12 Reserved. R/W R Default 0h Reset N/A (Hard-coded) R12 11 R 0h N/A (Hard-coded) 384kHz rate support: 1 = yes, 0 = no. R11 10 R 1h N/A (Hard-coded) 192kHz rate support: 1 = yes, 0 = no. R10 9 R 0h N/A (Hard-coded) 176.4kHz rate support: 1 = yes, 0 = no. R9 8 R 1h N/A (Hard-coded) 96kHz rate support: 1 = yes, 0 = no. R8 7 R 1h N/A (Hard-coded) 88.2kHz rate support: 1 = yes, 0 = no. R7 6 R 1h N/A (Hard-coded) 48kHz rate support: 1 = yes, 0 = no. R6 5 R 1h N/A (Hard-coded) 44.1kHz rate support: 1 = yes, 0 = no. R5 4 R 0h N/A (Hard-coded) 32kHz rate support: 1 = yes, 0 = no. R4 3 R 0h N/A (Hard-coded) 22.05kHz rate support: 1 = yes, 0 = no. R3 2 R 0h N/A (Hard-coded) 16kHz rate support: 1 = yes, 0 = no. R2 1 R 0h N/A (Hard-coded) 11.025kHz rate support: 1 = yes, 0 = no. R1 0 R 0h N/A (Hard-coded) 8kHz rate support: 1 = yes, 0 = no. 219 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.27.2. Reg Set Get SPDIFOut0 (NID = 1Dh): StreamCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Bh Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) AC3 2 R 1h N/A (Hard-coded) AC-3 formatted data support: 1 = yes, 0 = no. Float32 1 R 0h N/A (Hard-coded) Float32 formatted data support: 1 = yes, 0 = no. PCM 0 R 1h N/A (Hard-coded) PCM-formatted data support: 1 = yes, 0 = no. 6.27.3. Reg Set Get SPDIFOut0 (NID = 1Dh): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 00h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. R 0h N/A (Hard-coded) 220 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name NumSteps Bits 14:8 R/W R Default 00h Reset N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 00h N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.27.4. Reg Set Get SPDIFOut0 (NID = 1Dh): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) FrmtNonPCM 15 RW 0h POR - DAFG - ULR Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. SmplRateMultp 13:11 RW 0h POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved 221 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SmplRateDiv Bits 10:8 R/W RW Default 0h Reset POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.27.5. Reg Set Get SPDIFOut0 (NID = 1Dh): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. 222 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 6:0 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 6.27.6. Reg Set Get SPDIFOut0 (NID = 1Dh): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:0 Reserved. R 00h N/A (Hard-coded) 6.27.7. Reg Set Get SPDIFOut0 (NID = 1Dh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. 223 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B R 0h N/A (Hard-coded) 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Error Bits 8 R/W R Default 0h Reset POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.27.8. Reg Set Get SPDIFOut0 (NID = 1Dh): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 6.27.9. Reg Set Get SPDIFOut0 (NID = 1Dh): DigCnvtr Byte 3 (Bits 23:16) 73Eh F0E00h / F0D00h Byte 4 (Bits 31:24) 73Fh Byte 2 (Bits 15:8) 70Eh Byte 1 (Bits 7:0) 70Dh 224 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) KeepAlive 23 RW 0h POR - DAFG - ULR Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock information not required during D3. Rsvd1 22:15 Reserved. CC 14:8 RW 00h POR - DAFG - ULR R 00h N/A (Hard-coded) CC: Category Code. L 7 RW 0h POR - DAFG - ULR L: Generation Level. PRO 6 RW 0h POR - DAFG - ULR PRO: Professional. AUDIO 5 RW 0h POR - DAFG - ULR /AUDIO: Non-Audio. COPY 4 RW 0h POR - DAFG - ULR COPY: Copyright. PRE 3 RW 0h POR - DAFG - ULR PRE: Preemphasis. VCFG 2 RW 0h POR - DAFG - ULR VCFG: Validity Config. V 1 V: Validity. DigEn 0 RW 0h POR - DAFG - ULR RW 0h POR - DAFG - ULR Digital enable: 1 = converter enabled, 0 = converter disable. 6.28. SPDIFOut1 (NID = 1Eh): WCap Reg Set Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 225 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.28. SPDIFOut1 (NID = 1Eh): WCap Reg Get Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) F0009h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 0h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 4h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 226 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 1h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.28.1. Reg Set Get SPDIFOut1 (NID = 1Eh): PCMCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ah Field Name Rsvd2 Bits 31:21 Reserved. R/W R Default 000h Reset N/A (Hard-coded) B32 20 R 0h N/A (Hard-coded) 32 bit audio format support: 1 = yes, 0 = no. B24 19 R 1h N/A (Hard-coded) 24 bit audio format support: 1 = yes, 0 = no. 227 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name B20 Bits 18 R/W R Default 1h Reset N/A (Hard-coded) 20 bit audio format support: 1 = yes, 0 = no. B16 17 R 1h N/A (Hard-coded) 16 bit audio format support: 1 = yes, 0 = no. B8 16 R 0h N/A (Hard-coded) 8 bit audio format support: 1 = yes, 0 = no. Rsvd1 15:12 Reserved. R12 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) 384kHz rate support: 1 = yes, 0 = no. R11 10 R 1h N/A (Hard-coded) 192kHz rate support: 1 = yes, 0 = no. R10 9 R 0h N/A (Hard-coded) 176.4kHz rate support: 1 = yes, 0 = no. R9 8 R 1h N/A (Hard-coded) 96kHz rate support: 1 = yes, 0 = no. R8 7 R 1h N/A (Hard-coded) 88.2kHz rate support: 1 = yes, 0 = no. R7 6 R 1h N/A (Hard-coded) 48kHz rate support: 1 = yes, 0 = no. R6 5 R 1h N/A (Hard-coded) 44.1kHz rate support: 1 = yes, 0 = no. R5 4 R 0h N/A (Hard-coded) 32kHz rate support: 1 = yes, 0 = no. R4 3 R 0h N/A (Hard-coded) 22.05kHz rate support: 1 = yes, 0 = no. R3 2 R 0h N/A (Hard-coded) 16kHz rate support: 1 = yes, 0 = no. 228 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name R2 Bits 1 R/W R Default 0h Reset N/A (Hard-coded) 11.025kHz rate support: 1 = yes, 0 = no. R1 0 R 0h N/A (Hard-coded) 8kHz rate support: 1 = yes, 0 = no. 6.28.2. Reg Set Get SPDIFOut1 (NID = 1Eh): StreamCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Bh Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) AC3 2 R 1h N/A (Hard-coded) AC-3 formatted data support: 1 = yes, 0 = no. Float32 1 R 0h N/A (Hard-coded) Float32 formatted data support: 1 = yes, 0 = no. PCM 0 R 1h N/A (Hard-coded) PCM-formatted data support: 1 = yes, 0 = no. 6.28.3. Reg Set Get SPDIFOut1 (NID = 1Eh): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. 229 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd3 Bits 30:23 Reserved. R/W R Default 00h Reset N/A (Hard-coded) StepSize 22:16 R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 00h N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 00h N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.28.4. Reg Set Get SPDIFOut1 (NID = 1Eh): Cnvtr Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h A0000h Byte 4 (Bits 31:24) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) FrmtNonPCM 15 RW 0h POR - DAFG - ULR Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. 230 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SmplRateMultp Bits 13:11 R/W RW Default 0h Reset POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved NmbrChan 3:0 RW 1h POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.28.5. Reg Set Get SPDIFOut1 (NID = 1Eh): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) 231 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:0 Reserved. R 00h N/A (Hard-coded) 6.28.6. Reg Set Get SPDIFOut1 (NID = 1Eh): OutAmpRight Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 390h B8000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:0 Reserved. R 00h N/A (Hard-coded) 6.28.7. Reg Set Get SPDIFOut1 (NID = 1Eh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 232 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SettingsReset Bits 10 R/W R Default 1h Reset POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.28.8. Reg Set Get SPDIFOut1 (NID = 1Eh): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 233 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.28.9. Reg Set Get SPDIFOut1 (NID = 1Eh): DigCnvtr Byte 3 (Bits 23:16) 73Eh F0E00h / F0D00h Byte 4 (Bits 31:24) 73Fh Byte 2 (Bits 15:8) 70Eh Byte 1 (Bits 7:0) 70Dh Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) KeepAlive 23 RW 0h POR - DAFG - ULR Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock information not required during D3. Rsvd1 22:15 Reserved. CC 14:8 RW 00h POR - DAFG - ULR R 00h N/A (Hard-coded) CC: Category Code. L 7 RW 0h POR - DAFG - ULR L: Generation Level. PRO 6 RW 0h POR - DAFG - ULR PRO: Professional. AUDIO 5 RW 0h POR - DAFG - ULR /AUDIO: Non-Audio. COPY 4 RW 0h POR - DAFG - ULR COPY: Copyright. PRE 3 RW 0h POR - DAFG - ULR PRE: Preemphasis. VCFG 2 RW 0h POR - DAFG - ULR VCFG: Validity Config. V 1 V: Validity. RW 0h POR - DAFG - ULR 234 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name DigEn Bits 0 R/W RW Default 0h Reset POR - DAFG - ULR Digital enable: 1 = converter enabled, 0 = converter disable. 6.29. Dig0Pin (NID = 1Fh): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 4h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). 235 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnList Bits 8 R/W R Default 1h Reset N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.29.1. Reg Set Get Dig0Pin (NID = 1Fh): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) 236 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name EapdCap Bits 16 R/W R Default 0h Reset N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. VrefCntrl 15:8 R 00h N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.29.2. Reg Set Get Dig0Pin (NID = 1Fh): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh 237 V 1.0 2/12 92HD66B ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.29.3. Reg Set Get Dig0Pin (NID = 1Fh): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 1Dh N/A (Hard-coded) SPDIFOut0 Converter widget (0x1D) 6.29.4. Reg Set Get Dig0Pin (NID = 1Fh): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) 238 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.29.5. Reg Set Get Dig0Pin (NID = 1Fh): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. 239 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name InEn Bits 5 R/W RW Default 0h Reset POR - DAFG - ULR Input enable; 1 = enabled, 0 = disabled Rsvd1 4:0 Reserved. R 00h N/A (Hard-coded) 6.29.6. Reg Set Get Dig0Pin (NID = 1Fh): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.29.7. Reg Set Get Dig0Pin (NID = 1Fh): ChSense Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) 240 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.29.8. Reg Set Get Dig0Pin (NID = 1Fh): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved RW 01h POR 241 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Device Bits 23:20 R/W RW Default 4h Reset POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other ConnectionType 19:16 RW 5h POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other 242 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Color Bits 15:12 R/W RW Default 1h Reset POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 1h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 5h POR Default assocation. Sequence 3:0 Sequence. RW 0h POR 6.30. Dig1Pin (NID = 20h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 243 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 4h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. 244 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AmpParOvrd Bits 3 R/W R Default 0h Reset N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.30.1. Reg Set Get Dig1Pin (NID = 20h): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 0h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. VrefCntrl 15:8 R 00h N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. R 0h N/A (Hard-coded) 245 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name BalancedIO Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no. InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no. OutCap 4 R 1h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no. PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no. ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no. 6.30.2. Reg Set Get Dig1Pin (NID = 20h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 246 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.30.3. Reg Set Get Dig1Pin (NID = 20h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. ConL1 15:8 R 00h N/A (Hard-coded) Unused list entry. ConL0 7:0 R 1Eh N/A (Hard-coded) SPDIFOut1 Converter widget (0x1E) 6.30.4. Reg Set Get Dig1Pin (NID = 20h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. R 0h N/A (Hard-coded) 247 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Error Bits 8 R/W R Default 0h Reset POR - DAFG - ULR Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 6.30.5. Reg Set Get Dig1Pin (NID = 20h): PinWCntrl Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h F0700h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 0000000h Reset N/A (Hard-coded) OutEn 6 RW 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. InEn 5 RW 0h POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled. Rsvd1 4:0 Reserved. R 00h N/A (Hard-coded) 248 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.30.6. Reg Set Get Dig1Pin (NID = 20h): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.30.7. Reg Set Get Dig1Pin (NID = 20h): ChSense Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.30.8. Reg Set Get Dig1Pin (NID = 20h): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h 249 V 1.0 2/12 92HD66B ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PortConnectivity Bits 31:30 R/W RW Default 2h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved Device 23:20 RW 5h POR RW 18h POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other 250 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConnectionType Bits 19:16 R/W RW Default 6h Reset POR Connection type: 0h = Unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other Color 15:12 RW 0h POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 1h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 6h POR Default assocation. Sequence 3:0 Sequence. RW 0h POR 251 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.31. DigBeep (NID = 21h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd4 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 7h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Rsvd3 19:11 Reserved. PwrCntrl 10 R 1h N/A (Hard-coded) R 000h N/A (Hard-coded) Power state support: 1 = yes, 0 = no." Rsvd2 9:4 Reserved R 00h N/A (Hard-coded) AmpParOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 1h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. Rsvd1 1:0 Reserved. R 0h N/A (Hard-coded) 252 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.31.1. Reg Set Get DigBeep (NID = 21h): OutAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0012h Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 17h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 03h N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). Rsvd1 7 Reserved. Offset 6:0 R 03h N/A (Hard-coded) R 0h N/A (Hard-coded) Indicates which step is 0dB 6.31.2. Reg Set Get DigBeep (NID = 21h): OutAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 3A0h BA000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) 253 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Mute Bits 7 R/W RW Default 0h Reset POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:2 Reserved. Gain 1:0 RW 1h POR - DAFG - ULR R 00h N/A (Hard-coded) Amp gain step number (see OutAmpCap parameter pertaining to this widget). 6.31.3. Reg Set Get DigBeep (NID = 21h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. R 0h N/A (Hard-coded) 254 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Set Bits 1:0 R/W RW Default 0h Reset POR - DAFG - LR Current power state setting for this widget. 6.31.4. Reg Set Get DigBeep (NID = 21h): Gen Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 70Ah F0A00h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Divider 7:0 RW 00h POR - DAFG - LR Enable internal PC-Beep generation. Divider == 00h disables internal PC Beep generation and enables normal operation of the codec. Divider != 00h generates the beep tone on all Pin Complexes that are currently configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). 6.31.5. Reg Set Get SPDIFIn (NID = 22h): WCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0009h Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) 255 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Type Bits 23:20 R/W R Default 1h Reset N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 4h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 1h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 0h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. ProcWidget 6 R 0h N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 1h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 1h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. 256 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name OutAmpPrsnt Bits 2 R/W R Default 0h Reset N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 1h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 257 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.32. SPDIFIn (NID = 22h): Cnvtr Reg Set Get A0000h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) 2h Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) FrmtNonPCM 15 RW 0h POR - DAFG - ULR Stream type: 1 = Non-PCM, 0 = PCM. FrmtSmplRate 14 RW 0h POR - DAFG - ULR Sample base rate: 1 = 44.1kHz, 0 = 48kHz. SmplRateMultp 13:11 RW 0h POR - DAFG - ULR Sample base rate multiple: 000b= x1 (48kHz/44.1kHz or less) 001b= x2 (96kHz/88.2kHz/32kHz) 010b= x3 (144kHz) 011b= x4 (192kHz/176.4kHz) 100b-111b Reserved SmplRateDiv 10:8 RW 0h POR - DAFG - ULR Sample base rate divider: 000b= Divide by 1 (48kHz/44.1kHz) 001b= Divide by 2 (24kHz/20.05kHz) 010b= Divide by 3 (16kHz/32kHz) 011b= Divide by 4 (11.025kHz) 100b= Divide by 5 (9.6kHz) 101b= Divide by 6 (8kHz) 110b= Divide by 7 111b= Divide by 8 (6kHz) Rsvd1 7 Reserved. BitsPerSmpl 6:4 RW 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= Reserved 258 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name NmbrChan Bits 3:0 R/W RW Default 1h Reset POR - DAFG - ULR Total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 6.32.1. Reg Set Get SPDIFIn (NID = 22h): PCMCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ah Field Name Rsvd2 Bits 31:21 Reserved. R/W R Default 000h Reset N/A (Hard-coded) B32 20 R 0h N/A (Hard-coded) 32 bit audio format support: 1 = yes, 0 = no. B24 19 R 1h N/A (Hard-coded) 24 bit audio format support: 1 = yes, 0 = no. B20 18 R 1h N/A (Hard-coded) 20 bit audio format support: 1 = yes, 0 = no. B16 17 R 1h N/A (Hard-coded) 16 bit audio format support: 1 = yes, 0 = no. B8 16 R 0h N/A (Hard-coded) 8 bit audio format support: 1 = yes, 0 = no. Rsvd1 15:12 Reserved. R12 11 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) 384kHz rate support: 1 = yes, 0 = no. R11 10 R 1h N/A (Hard-coded) 192kHz rate support: 1 = yes, 0 = no. R10 9 R 0h N/A (Hard-coded) 176.4kHz rate support: 1 = yes, 0 = no. 259 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name R9 Bits 8 R/W R Default 1h Reset N/A (Hard-coded) 96kHz rate support: 1 = yes, 0 = no. R8 7 R 0h N/A (Hard-coded) 88.2kHz rate support: 1 = yes, 0 = no. R7 6 R 1h N/A (Hard-coded) 48kHz rate support: 1 = yes, 0 = no. R6 5 R 1h N/A (Hard-coded) 44.1kHz rate support: 1 = yes, 0 = no. R5 4 R 0h N/A (Hard-coded) 32kHz rate support: 1 = yes, 0 = no. R4 3 R 0h N/A (Hard-coded) 22.05kHz rate support: 1 = yes, 0 = no. R3 2 R 0h N/A (Hard-coded) 16kHz rate support: 1 = yes, 0 = no. R2 1 R 0h N/A (Hard-coded) 11.025kHz rate support: 1 = yes, 0 = no. R1 0 R 0h N/A (Hard-coded) 8kHz rate support: 1 = yes, 0 = no. 6.32.2. Reg Set Get SPDIFIn (NID = 22h): StreamCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Bh Field Name Rsvd Bits 31:3 Reserved. R/W R Default 00000000h Reset N/A (Hard-coded) AC3 2 R 1h N/A (Hard-coded) AC-3 formatted data support: 1 = yes, 0 = no. 260 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Float32 Bits 1 R/W R Default 0h Reset N/A (Hard-coded) Float32 formatted data support: 1 = yes, 0 = no. PCM 0 R 1h N/A (Hard-coded) PCM-formatted data support: 1 = yes, 0 = no. 6.32.3. Reg Set Get SPDIFIn (NID = 22h): ConLst Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Eh Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) LForm 7 R 0h N/A (Hard-coded) Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit) NID entries. ConL 6:0 R 01h N/A (Hard-coded) Number of NID entries in connection list. 6.32.4. Reg Set Get SPDIFIn (NID = 22h): ConLstEntry0 Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F0200h Field Name ConL3 Bits 31:24 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL2 23:16 R 00h N/A (Hard-coded) Unused list entry. 261 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ConL1 Bits 15:8 R/W R Default 00h Reset N/A (Hard-coded) Unused list entry. ConL0 7:0 R 24h N/A (Hard-coded) Dig2Pin pin widget (0x24) 6.32.5. Reg Set Get SPDIFIn (NID = 22h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - LR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 3h POR - DAFG - LR R 0h N/A (Hard-coded) Current power state setting for this widget. 262 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.32.6. Reg Set Get SPDIFIn (NID = 22h): CnvtrID Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 706h F0600h Byte 4 (Bits 31:24) Field Name Rsvd Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Strm 7:4 RW 0h POR - S&DAFG - LR - PS Stream ID: 0h = Converter "off", 1h-Fh = valid ID's. Ch 3:0 RW 0h POR - S&DAFG - LR - PS Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo converter). 6.32.7. Reg Set Get SPDIFIn (NID = 22h): DigCnvtr Byte 3 (Bits 23:16) 73Eh F0E00h / F0D00h Byte 4 (Bits 31:24) 73Fh Byte 2 (Bits 15:8) 70Eh Byte 1 (Bits 7:0) 70Dh Field Name Rsvd2 Bits 31:16 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) Rsvd1 15 Reserved. R 0h N/A (Hard-coded) CC 14:8 R 00h POR - DAFG - ULR CC: Category Code. L 7 R 0h POR - DAFG - ULR L: Generation Level. PRO 6 R 0h POR - DAFG - ULR PRO: Professional. 263 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name AUDIO Bits 5 R/W R Default 0h Reset POR - DAFG - ULR /AUDIO: Non-Audio. COPY 4 R 0h POR - DAFG - ULR COPY: Copyright. PRE 3 R 0h POR - DAFG - ULR PRE: Preemphasis. VCFG 2 R 0h POR - DAFG - ULR VCFG: Validity Config. V 1 V: Validity. DigEn 0 RW 0h POR - DAFG - ULR R 0h POR - DAFG - ULR Digital enable: 1 = converter enabled, 0 = converter disable. 6.32.8. Reg Set Get SPDIFIn (NID = 22h): InAmpCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Dh Field Name Mute Bits 31 R/W R Default 1h Reset N/A (Hard-coded) Mute support: 1 = yes, 0 = no. Rsvd3 30:23 Reserved. StepSize 22:16 R 00h N/A (Hard-coded) R 00h N/A (Hard-coded) Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps. Rsvd2 15 Reserved. NumSteps 14:8 R 00h N/A (Hard-coded) R 0h N/A (Hard-coded) Number of gains steps (number of possible settings - 1). 264 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd1 Bits 7 Reserved. R/W R Default 0h Reset N/A (Hard-coded) Offset 6:0 R 00h N/A (Hard-coded) Indicates which step is 0dB 6.32.9. Reg Set Get SPDIFIn (NID = 22h): InAmpLeft Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 360h B2000h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:0 Reserved. R 00h N/A (Hard-coded) 6.32.10. SPDIFIn (NID = 22h): InAmpRight Reg Set Get B0000h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 350h Field Name Rsvd2 Bits 31:2 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) Mute 7 RW 0h POR - DAFG - ULR Amp mute: 1 = muted, 0 = not muted. Rsvd1 6:0 Reserved. RW 0h N/A (Hard-coded) 265 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.32.11. SPDIFIn (NID = 22h): VS Reg Set Get FE000h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7E0h Field Name Rsvd Bits 31:2 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) RoundDis 1 RW 0h POR - DAFG - ULR SPDIF Input rounding disable: 0 = rounding is enabled, 1 = rounding is disabled. LoLvSel 0 RW 0h POR - DAFG - ULR SPDIF Input level select: 0 = standard level, 1 = low level (input buffer enabled. 6.32.12. SPDIFIn (NID = 22h): Status Reg Set Get FE800h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 7E8h Field Name RcvSmplRate Bits 31:29 R/W R Default 7h Reset POR - DAFG - ULR Received Sample Rate: 000b = 44.1kHz 001b = 48kHz 010b = 88.2kHz 011b = 96kHz 100b = 176.4kHz 101b = 192kHz 11Xb = Invalid Rate Rsvd2 28.26 Reserved. R 0h N/A (Hard-coded) 266 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name OrigFS Bits 25:22 R/W R Default 0h Reset POR - DAFG - ULR Original Sample Rate (per IEC60958-3 spec): 0000b = Original sampling frequency not indicated 0001b = 192kHz 0010b = 12kHz 0011b = 176.4kHz 0100b = Reserved 0101b = 96kHz 0110b = 8kHz 0111b = 88.2kHz 1000b = 16kHz 1001b = 24kHz 1010b = 11.025kHz 1011b = 22.05kHz 1100b = 32kHz 1101b = 48khz 1110b = Reserved 1111b = 44.1kHz CA 21:20 R 0h POR - DAFG - ULR Clock Accuracy (per IEC60958-3 spec): 00b = Level II 01b = Level I 10b = Level III 11b = Reserved FS 19:16 R 0h POR - DAFG - ULR Sample Rate (per IEC60958-3 spec): 0000b = 44.1kHz 0001b = Original sampling frequency not indicated 0010b = 48kHz 0011b = 32kHz 0100b = 22.05kHz 0101b = Reserved 0110b = 24kHz 0111b = Reserved 1000b = 88.2kHz 1001b = Reserved 1010b = 96kHz 1011b = Reserved 1100b = 176.4kHz 1101b = Reserved 1110b = 192kHz 1111b = Reserved CN 15:12 R 0h POR - DAFG - ULR Channel Number (per IEC60958-3 spec): 0000b = Do not take into account 0001b = Channel 1 (Left channel for stereo channel format) 0010b = Channel 2 (Right channel for stereo channel format) 0011b-1111b = Channel 3-15 267 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name SmplWrdL Bits 11:9 R/W R Default 0h Reset POR - DAFG - ULR Sample Word Length (per IEC60958-3 spec): 000b = Word length not indicated 001b = Max length - 4 010b = Max length - 2 011b = Reserved 100b = Max length - 1 101b = Max length - 0 110b = Max length - 3 111b = Reserved MaxWrdL 8 R 0h POR - DAFG - ULR Max Word Length (per IEC60958-3 spec): 0 = 20 bits, 1 = 24 bits. NoBlkChk 7 RW 0h POR - DAFG - ULR Disable Sample Block Checking. Rsvd 6:5 Reserved. ParityLimit 4:3 RW 0h POR - DAFG - ULR R 0h N/A (Hard-coded) SPDIFIn Parity Limit (DPLL loses lock when the set number of parity errors per block is detected): 00b = 4 Parity errors 01b = 3 Parity errors 10b = 2 Parity errors 11b = 1 Parity error SPRun 2 R 0h POR - DAFG - ULR SPDIFIn Running 0 = no signal on SPDIFIn Pin, 1 = Signal on SPDIFIn pin. SiPerr 1 RW 0h POR - DAFG - ULR SPDIFIn Parity Error: 0 = No error detected, 1 = Error detected (write 0 to clear). Not affected by ParityLimit. CopyInv 0 RW 0h POR - DAFG - ULR Copyright Invert: 0 = Do not invert COPY bit, 1 = Invert COPY bit. 268 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.33. NID = 23h Reserved 269 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 6.34. Dig2Pin (NID = 24h): WCap Reg Set Get F0009h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Field Name Rsvd2 Bits 31:24 Reserved. R/W R Default 00h Reset N/A (Hard-coded) Type 23:20 R 0h N/A (Hard-coded) Widget type: 0h = Out Converter 1h = In Converter 2h = Summing (Mixer) 3h = Selector (Mux) 4h = Pin Complex 5h = Power 6h = Volume Knob 7h = Beep Generator 8h-Eh = Reserved Fh = Vendor Defined Delay 19:16 R 0h N/A (Hard-coded) Number of sample delays through widget. Rsvd1 15:12 Reserved. SwapCap 11 R 1h N/A (Hard-coded) R 0h N/A (Hard-coded) Left/right swap support: 1 = yes, 0 = no. PwrCntrl 10 R 1h N/A (Hard-coded) Power state support: 1 = yes, 0 = no. Dig 9 R 1h N/A (Hard-coded) Digital stream support: 1 = yes (digital), 0 = no (analog). ConnList 8 R 0h N/A (Hard-coded) Connection list present: 1 = yes, 0 = no. UnSolCap 7 R 1h N/A (Hard-coded) Unsolicited response support: 1 = yes, 0 = no. 270 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name ProcWidget Bits 6 R/W R Default 0h Reset N/A (Hard-coded) Processing state support: 1 = yes, 0 = no. Stripe 5 R 0h N/A (Hard-coded) Striping support: 1 = yes, 0 = no. FormatOvrd 4 R 0h N/A (Hard-coded) Stream format override: 1 = yes, 0 = no. AmpParOvrd 3 R 0h N/A (Hard-coded) Amplifier capabilities override: 1 = yes, no. OutAmpPrsnt 2 R 0h N/A (Hard-coded) Output amp present: 1 = yes, 0 = no. InAmpPrsnt 1 R 0h N/A (Hard-coded) Input amp present: 1 = yes, 0 = no. Stereo 0 R 1h N/A (Hard-coded) Stereo stream support: 1 = yes (stereo), 0 = no (mono). 6.34.1. Reg Set Get Dig2Pin (NID = 24h): PinCap Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) Byte 4 (Bits 31:24) F000Ch Field Name Rsvd2 Bits 31:17 Reserved. R/W R Default 0000h Reset N/A (Hard-coded) EapdCap 16 R 00h N/A (Hard-coded) EAPD support: 1 = yes, 0 = no. 271 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name VrefCntrl Bits 15:8 R/W RW Default 0h Reset N/A (Hard-coded) Vref support: bit 7 = Reserved bit 6 = Reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = Reserved bit 2 = GND support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = Hi-Z support (1 = yes, 0 = no) Rsvd1 7 Reserved. BalancedIO 6 R 0h N/A (Hard-coded) R 0h N/A (Hard-coded) Balanced I/O support: 1 = yes, 0 = no InCap 5 R 1h N/A (Hard-coded) Input support: 1 = yes, 0 = no OutCap 4 R 0h N/A (Hard-coded) Output support: 1 = yes, 0 = no. HdphDrvCap 3 R 0h N/A (Hard-coded) Headphone amp present: 1 = yes, 0 = no PresDtctCap 2 R 1h N/A (Hard-coded) Presence detection support: 1 = yes, 0 = no. TrigRqd 1 R 0h N/A (Hard-coded) Trigger required for impedance sense: 1 = yes, 0 = no ImpSenseCap 0 R 0h N/A (Hard-coded) Impedance sense support: 1 = yes, 0 = no 6.34.2. Reg Set Get Dig2Pin (NID = 24h): PwrState Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 705h F0500h Byte 4 (Bits 31:24) 272 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Rsvd4 Bits 31:11 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) SettingsReset 10 R 1h POR - DAFG - ULR Indicates if any persistent settings in this Widget have been reset. Cleared by PwrState 'Get', or a 'Set' to any Verb in this Widget. Rsvd3 9 Reserved. Error 8 R 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. Rsvd2 7:6 Reserved. Act 5:4 R 3h POR - DAFG - ULR R 0h N/A (Hard-coded) Actual power state of this widget. Rsvd1 3:2 Reserved. Set 1:0 RW 0h POR - DAFG - ULR R 0h N/A (Hard-coded) Current power state setting for this widget. Dig2Pin (NID = 24h): PinWCntrl Reg Set Get F0700h Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 707h Field Name Rsvd2 Bits 31:7 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) OutEn 6 R 0h POR - DAFG - ULR Output enable: 1 = enabled, 0 = disabled. 273 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name InEn Bits 5 R/W RW Default 0h Reset POR - DAFG - ULR Input enable: 1 = enabled, 0 = disabled Rsvd1 4:0 Reserved. R 0h N/A (Hard-coded) 6.34.3. Reg Set Get Dig2Pin (NID = 24h): UnsolResp Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 708h F0800h Byte 4 (Bits 31:24) Field Name Rsvd2 Bits 31:8 Reserved. R/W R Default 000000h Reset N/A (Hard-coded) En 7 RW 0h POR - DAFG - ULR Unsolicited response enable (also enables Wake events for this Widget): 1 = enabled, 0 = disabled. Rsvd1 6 Reserved. Tag 5:0 RW 00h POR - DAFG - ULR R 0h N/A (Hard-coded) Software programmable field returned in top six bits (31:26) of every Unsolicited Response generated by this node. 6.34.4. Reg Set Get Dig2Pin (NID = 24h): ChSense Byte 3 (Bits 23:16) Byte 2 (Bits 15:8) Byte 1 (Bits 7:0) 709h F0900h Byte 4 (Bits 31:24) 274 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name PresDtct Bits 31 R/W R Default 0h Reset POR Presence detection indicator: 1 = presence detected; 0 = presence not detected. Rsvd 30:0 Reserved. R 00000000h N/A (Hard-coded) 6.34.5. Reg Set Get Dig2Pin (NID = 24h): ConfigDefault Byte 3 (Bits 23:16) 71Eh Byte 4 (Bits 31:24) 71Fh Byte 2 (Bits 15:8) 71Dh Byte 1 (Bits 7:0) 71Ch F1F00h / F1E00h / F1D00h / F1C00h Field Name PortConnectivity Bits 31:30 R/W RW Default 0h Reset POR Port connectivity: 0h = Port complex is connected to a jack 1h = No physical connection for port 2h = Fixed function device is attached 3h = Both jack and internal device attached (info in all other fields refers to integrated device, any presence detection refers to jack) Location 29:24 Location Bits [5..4]: 0h = External on primary chassis 1h = Internal 2h = Separate chassis 3h = Other Bits [3..0]: 0h = N/A 1h = Rear 2h = Front 3h = Left 4h = Right 5h = Top 6h = Bottom 7h-9h = Special Ah-Fh = Reserved RW 01h POR 275 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Device Bits 23:20 R/W RW Default Ch Reset POR Default device: 0h = Line out 1h = Speaker 2h = HP out 3h = CD 4h = SPDIF Out 5h = Digital other out 6h = Modem line side 7h = Modem handset side 8h = Line in 9h = Aux Ah = Mic in Bh = Telephony Ch = SPDIF In Dh = Digital other in Eh = Reserved Fh = Other ConnectionType 19:16 RW 5h POR Connection type: 0h = Unknown 1h = 1/8"" stereo/mono 2h = 1/4"" stereo/mono 3h = ATAPI internal 4h = RCA 5h = Optical 6h = Other digital 7h = Other analog 8h = Multichannel analog (DIN) 9h = XLR/Professional Ah = RJ-11 (modem) Bh = Combination Ch-Eh = Reserved Fh = Other 276 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Field Name Color Bits 15:12 R/W RW Default 2h Reset POR Color: 0h = Unknown 1h = Black 2h = Grey 3h = Blue 4h = Green 5h = Red 6h = Orange 7h = Yellow 8h = Purple 9h = Pink Ah-Dh = Reserved Eh = White Fh = Other Misc 11:8 RW 0h POR Miscellaneous: Bits [3..1] = Reserved Bit 0 = Jack detect override Association 7:4 RW 7h POR Default assocation. Sequence 7:4 Sequence. RW 0h POR 277 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 7. PINOUTS AND PACKAGE INFORMATION 7.1. 48-Pin Pinout SPDF0/DMIC1/GPIO3 EAPD SPDF1/DMIC1/GPIO0 SPDIF_IN GPIO4 PORTB_R(IN) PORTB_L(IN) AVSS2 PORTA_R(IN) PORTA_L(IN) AVDD2 CPVreg 48 47 46 45 44 43 42 41 40 39 38 37 DVDD_LV DMIC_CLK/GPIO1 DVDD_IO DMIC0/GPIO2 SDATA_OUT BITCLK DVSS SDATA_IN DVDD SYNC RESET# PCBeep 1 2 3 4 5 6 7 8 9 10 11 12 48-QFN 36 35 34 33 32 31 30 29 28 27 26 25 CAP+ CAPVAVSS2 PORTB_R(HP) PORTB_L(HP) PORTA_R(HP) PORTA_L(HP) AVreg AVDD1 AVSS1 Mono_Out SENSE_A SENSE_B PORTE_L PORTE_R PORTF_L PORTF_R PORTC_L PORTC_R VrefFilt CAP2 VrefOut-E VrefOut-C 13 14 15 16 17 18 19 20 21 22 23 24 Figure 14. 48-Pin Pinout 278 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 7.2. 40-Pin Pinout SPDF0/DMIC1/GPIO3 EAPD SPDF1/DMIC1/GPIO0 SPDIF_IN PORTB_R(IN) PORTB_L(IN) AVSS2 PORTA_R(IN) PORTA_L(IN) AVDD2 DVDD_LV DMIC_CLK/GPIO1 DMIC0/GPIO2 SDATA_OUT BITCLK SDATA_IN DVDD SYNC RESET# PCBeep 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 40-QFN CPVreg CAP+ CAPVAVSS2 PORTB_R(HP) PORTB_L(HP) PORTA_R(HP) PORTA_L(HP) AVreg SENSE_A PORTF_L PORTF_R PORTC_L PORTC_R VrefFilt CAP2 VREFOUT-C AVSS1 AVDD1 Figure 15. 40-Pin Pinout 279 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 11 12 13 14 15 16 17 18 19 20 V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 7.3. Pin Table for 48-Pin Pin Name Pin Function 1.5V Digital Core Regulator Filter Cap Digital Mic Clock Output/GPIO1 Reference Voltage (1.5V or 3.3V) Digital Mic 01 Input/GPIO2 HD Audio Serial Data output from controller HD Audio Bit Clock Digital Ground Digital Vdd= 3.3V HD Audio Frame Sync HD Audio Reset PC Beep Input Jack insertion detection Jack insertion detection Port E Left Port E Right Port F Left Port F Right Port C Left Port C Right Analog Virtual Ground ADC reference bypass capacitor Reference Voltage out (for mic bias) Reference Voltage out (for mic bias) Mono output port Analog Ground Analog Vdd=5.0V Analog Core LDO decoupling cap Port A Output Left Port A Output Right Port B Output Left Port B Output Right Analog Ground Charge-pump negative output Charge-pump flying cap Charge-pump flying cap + Table 31. 48-PinTable 280 V 1.0 2/12 92HD66B I/O O(Power) I/O(Digital) I(Power) I/O(Digital) I(Digital) I(Digital) I(Digital) I(Power) I(Digital) I(Digital) I(Analog) I(Analog) I(Analog) I/O(Analog) I/O(Analog) I/O(Analog) I/O(Analog) I/O(Analog) I/O(Analog) O(Analog) O(Analog) O(Analog) O(Analog) O(Analog) I(Analog) I(Analog) O(Analog) O(Analog) O(Analog) O(Analog) O(Analog) I(Analog) O(Analog) I(Analog) O(Analog) Internal Pull-up Pull-down None 1 QFN location DVDD_LV DMIC_CLK/GPIO1 DVDD_IO DMIC0/GPIO2 SDATA_OUT BITCLK DVSS SDATA_IN DVDD SYNC RESET# PCBeep SENSE_A SENSE_B PORTE_L PORTE_R PORTF_L PORTF_R PORTC_L PORTC_R VREFFILT CAP 2 VREFOUT-E VREFOUT-C Mono_Out AVSS1 AVDD1 AVreg PORTA_L (HP) PORTA_R (HP) PORTB_L (HP) PORTB_R (HP) AVSS2 VCAPCAP+ 60K Pull-down 2 None 3 60K Pull-down 4 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 HD Audio Serial Data Input to controller I/O(Digital) ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Pin Name CPVreg AVDD2 PORTA_L (IN) PORTA_R (IN) AVSS2 PORTB_L(IN) PORTB_R(IN) GPIO 4 SPDIFIN SPDF1/GPIO0/ DMIC1 EAPD SPDF0/GPIO3/ DMIC1 Pin Function Charge-pump LDO decoupling cap Analog Supply for VREG Port A Left Input Port A Right Input Analog Ground Port B Left Input Port B Right Input General purpose I/O SPDIF Input SPDIF 0utput, GPIO0, Digital microphone input External Amplifier Power Down (active low) SPDIF 0utput, GPIO3, Digital microphone input Table 31. 48-PinTable I/O O(Analog) I(Power) I(Analog) I(Analog) I(Power) I(Analog) I(Analog) I/O (Digital) I(Digital) I/O(Digital) I/O(Digital) I/O(Digital) Internal Pull-up Pull-down QFN location 37 38 39 40 41 42 43 44 45 46 47 48 None None None None None None None 60K Pull-Down 60K Pull-Down 60K Pull-Down 60K Pull-Up 60K Pull-Down 7.4. Pin Table for 40-Pin Pin Name Pin Function 1.5V Digital Core Regulator Filter Cap I/O O(Power) Internal Pull-up Pull-down None 60K Pull-Down 60K Pull-Down None None None None None None None None None None None None None None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 QFN location DVDD_LV DMIC_CLK/GPIO1 DMIC0/GPIO2 SDATA_OUT BITCLK SDATA_IN DVDD SYNC RESET# PCBeep SENSE_A PORTF_L PORTF_R PORTC_L PORTC_R VREFFILT CAP 2 Digital Microphone clock output or GPIO I/O(Digital) 1 Digital Microphone data input or GPIO 2 I/O(Digital) HD Audio Serial Data output from controller HD Audio Bit Clock Digital Vdd= 3.3V HD Audio Frame Sync HD Audio Reset PC Beep input Jack insertion detection Port F Left Port F Right Port C Left Port C Right Analog Virtual Ground ADC reference bypass capacitor Table 32. 40-Pin Table I(Digital) I(Digital) I(Power) I(Digital) I(Digital) I(Analog) I(Analog) I/O(Analog) I/O(Analog) I/O(Analog) I/O(Analog) O(Analog) O(Analog) HD Audio Serial Data Input to controller I/O(Digital) 281 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS Pin Name VREFOUT-C AVSS1 AVDD1 AVreg PORTA_L (HP) PORTA_R (HP) PORTB_L (HP) PORTB_R (HP) AVSS2 VCAPCAP+ CPVreg AVDD2 PORTA_L(IN) PORTA_R(IN) AVSS2 PORTB_L(IN) PORTB_R(IN) SPDIFIN SPDF1/GPIO0/ DMIC1 EAPD SPDF0/GPIO3/ DMIC1 Pin Function Reference Voltage out drive (intended for mic bias) Analog Ground Analog Vdd=5.0V or 3.3V Analog Core LDO decoupling cap Port A Output Left Port A Output Right Port B Output Left Port B Output Right Analog Ground Charge-pump negative output Charge-pump flying cap Charge-pump flying cap + Charge-pump LDO decoupling cap Analog Supply for VREG Port A Left Input Port ARight Input Analog Ground Port B Left Input Port B Right Input SPDIF Input SPDIF output, GPIO0, or digital microphone input External Amplifier Power-Down (active low) SPDIF output, GPIO3, or digital microphone input Table 32. 40-Pin Table I/O O(Analog) I(Power) I(Analog) O(Analog) O(Analog) O(Analog) O(Analog) O(Analog) I(Power) O(Analog) I(Analog) O(Analog) I(Analog) I(Power) I(Analog) I(Analog) I(Power) I(Analog) I(Analog) I (Digital) I/O(Digital) I/O(Digital) I/O(Digital) Internal Pull-up Pull-down None None None None None None None None QFN location 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 None None None None None None None None None None None 60K Pull-Down 60K Pull-Down 60K Pull-Up 60K Pull-Down 282 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 7.5. 48QFN Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No. 95 QFN Dimensions in mm Key A A1 A3 D D1 E E1 L e R b D2 E2 ZD ZE 0.18 5.50 5.50 0.35 Min 0.80 0.00 Nom 0.90 0.02 0.20 REF 7.00 BSC 5.50 BSC 7.00 BSC 5.50 BSC 0.40 0.50 BSC 0.20-0.25 0.25 5.65 5.65 0.75 BSC 0.75 BSC 0.30 5.80 5.80 0.45 Max 1.0 0.05 Additional Approved Option Figure 16. 48QFN Package Diagram 283 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V 1.0 2/12 92HD66B 92HD66B FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS 7.6. 40QFN Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No. 95 Figure 17. 40QFN Package Diagram 7.7. Pb Free Process- Package Classification Reflow Temperatures Package Thickness or = 2.5mm Volume mm3 2000 260 + 0 oC* 245 + 0 oC* 245 + 0 oC* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 oC. For example 260 oC+0 oC) at the rated MSL level. Table 33. Reflow Note: IDT’s package thicknesses are