954226AKLFT

DATASHEET Programmable Timing Control HubTM for Mobile P4TM Systems Recommended Application: CK410M Compatible Main Clock Output Features: • 2 - 0.7V current-mode differential CPU pairs • 4 - 0.7V current-mode differential PCI Express* pairs • 1 - 0.7V current-mode differential CPU/PCI Express selectable pair • 1 - 0.7V current-mode differential SATA pair • 1 - 0.7V current-mode differential LCDCLK/PCI Express selectable pair • 4 - PCI (33MHz) • 2 - PCICLK_F, (33MHz) free-running • 1 - USB, 48MHz • 1 - DOT, 96MHz, 0.7V current differential pair • 2 - REF, 14.318MHz 9 54226 Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • PCI Express outputs cycle-cycle jitter < 125ps • SATA outputs cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 500ps • +/- 300ppm frequency accuracy on CPU, PCI Express and SATA clocks • +/- 100ppm frequency accuracy on USB clocks Features/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA and PCI Express • Supports programmable spread percentage and frequency • • • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, PCI Express pair in PD for power management. PEREQ# pins to support PCI Express and SATA power management. MLF Pin Configuration REF1/FSLC/TEST_SEL PCICLK2/REQ_SEL** PCI/SRC_STOP# TSSOP Pin Configuration VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 **SELPCIEX_LCDCLK#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE LCDCLK_SS/PCIEX0T LCDCLK_SS/PCIEX0C PCIEXT1 PCIEXC1 VDDPCIEX PCIEXT2 PCIEXC2 PCIEXT3 PCIEXC3 SATACLKT SATACLKC VDDPCIEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2/REQ_SEL** PCI/SRC_STOP# CPU_STOP# REF1/FSLC/TEST_SEL REF0 GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/PCIEXT6 CPUCLKC2_ITP/PCIEXC6 VDDPCIEX PEREQ1#*/PCIEXT5 PEREQ2#*/PCIEXC5 PCIEXT4 PCIEXC4 GND CPU_STOP# PCICLK5 PCICLK4 PCICLK3 VDDPCI REF0 GND GND GND X1 56 55 VDDPCI 1 ITP_EN/PCICLK_F0 2 **SELPCIEX_LCDCLK#/PCICLK_F1 3 Vtt_PwrGd#/PD 4 VDD48 5 FSLA/USB_48MHz 6 GND 7 DOTT_96MHz 8 DOTC_96MHz 9 FSLB/TEST_MODE 10 LCDCLK_SS/PCIEXT0 11 LCDCLK_SS/PCIEXC0 12 PCIEXT1 13 PCIEXC1 14 15 16 PCIEXT2 VDDPCIEX 54 53 52 51 50 49 48 47 46 45 44 43 42 VDDREF 41 SDATA 40 SCLK 39 GND 38 CPUCLKT0 37 CPUCLKC0 X2 ICS 954226AKLF 36 VDDCPU 35 CPUCLKT1 34 CPUCLKC1 33 IREF 32 GNDA 31 VDDA 30 CPUCLKT2_ITP/PCIEXT6 29 CPUCLKC2_ITP/PCIEXC6 17 18 19 20 21 22 23 24 25 26 27 28 SATACLKC PCIEXC2 PCIEXT3 PCIEXC3 GND PCIEXC4 PCIEXT4 PEREQ2#*/PCIEXC5 PEREQ1#*/PCIEXT5 SATACLKT VDDPCIEX VDDPCIEX 56-MLF * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 56-TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor Table 1: Frequency Selection Table FSLC B6b2 FS LB B6b1 FS LA B6b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 PCIEX MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 Spread % 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down 0.5% Down IDT® Programmable Timing Control HubTM for Mobile P4TM Systems ICS954226 0930A—04/13/10 1 954226 Programmable Timing Control HubTM for Mobile P4TM Systems TSSOP Pin Description PIN # 1 2 3 4 5 6 7 8 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PIN NAME TYPE PWR PWR OUT OUT OUT PWR PWR I/O DESCRIPTION Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# through I2C . ITP_EN: latched input to select pin functionality 1 = CPU_2_ITP pair 0 = PCIEX_6 pair Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / Free running 3.3V PCI clock output. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK_SS output / True clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# Complementary clock of LCDCLK_SS output / Complementary clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential SATA pair. Complement clock of differential SATA pair. Power supply for PCI Express clocks, nominal 3.3V 9 **SELPCIEX_LCDCLK#/PCICLK_F1 I/O 10 11 12 13 14 15 16 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE IN PWR I/O PWR OUT OUT IN 17 18 19 20 21 22 23 24 25 26 27 28 LCDCLK_SS/PCIEX0T LCDCLK_SS/PCIEX0C PCIEXT1 PCIEXC1 VDDPCIEX PCIEXT2 PCIEXC2 PCIEXT3 PCIEXC3 SATACLKT SATACLKC VDDPCIEX OUT OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 2 954226 Programmable Timing Control HubTM for Mobile P4TM Systems TSSOP Pin Description (cont.) PIN # 29 30 31 32 GND PCIEXC4 PCIEXT4 PEREQ2#*/PCIEXC5 PIN NAME TYPE PWR OUT OUT I/O DESCRIPTION Ground pin. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of differential PCI Express output. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / True clock of differential PCI Express output. Power supply for PCI Express clocks, nominal 3.3V Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. / True clock of differential PCIEX pair 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Stops all CPUCLK, except those set to be free running clocks Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0 level, when input low 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ# 33 34 35 PEREQ1#*/PCIEXT5 VDDPCIEX CPUCLKC2_ITP/PCIEXC6 I/O PWR OUT 36 37 38 39 CPUCLKT2_ITP/PCIEXT6 VDDA GNDA IREF OUT PWR PWR OUT 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 GND SCLK SDATA VDDREF X2 X1 GND REF0 REF1/FSLC/TEST_SEL CPU_STOP# PCI/SRC_STOP# PCICLK2/REQ_SEL** OUT OUT PWR OUT OUT PWR IN I/O PWR OUT IN PWR OUT I/O IN IN I/O IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 3 954226 Programmable Timing Control HubTM for Mobile P4TM Systems MLF Pin Description PIN # 1 2 VDDPCI ITP_EN/PCICLK_F0 PIN NAME TYPE PWR I/O DESCRIPTION Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / Free running 3.3V PCI clock output. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. Free running PCI clock not affected by PCI_STOP# through I2C . ITP_EN: latched input to select pin functionality 1 = CPU_2_ITP pair 0 = PCIEX_6 pair Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK_SS output / True clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# Complementary clock of LCDCLK_SS output / Complementary clock of PCI Express differential pair. Selected by SELPCIEX_LCDCLK# True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential SATA pair. Complement clock of differential SATA pair. Power supply for PCI Express clocks, nominal 3.3V Ground pin. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of differential PCI Express output. Real-time input pin that controls SATACLK and PCIEXCLK outputs that are selected through the I2c. 1 = disabled, 0 = enabled. / True clock of differential PCI Express output. Power supply for PCI Express clocks, nominal 3.3V 3 **SELPCIEX_LCDCLK#/PCICLK_F1 I/O 4 5 6 7 8 9 10 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE IN PWR I/O PWR OUT OUT IN 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 LCDCLK_SS/PCIEXT0 LCDCLK_SS/PCIEXC0 PCIEXT1 PCIEXC1 VDDPCIEX PCIEXT2 PCIEXC2 PCIEXT3 PCIEXC3 SATACLKT SATACLKC VDDPCIEX GND PCIEXC4 PCIEXT4 PEREQ2#*/PCIEXC5 OUT OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR PWR OUT OUT I/O 27 28 PEREQ1#*/PCIEXT5 VDDPCIEX I/O PWR IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 4 954226 Programmable Timing Control HubTM for Mobile P4TM Systems MLF Pin Description (Continued) PIN # 29 PIN NAME CPUCLKC2_ITP/PCIEXC6 TYPE OUT DESCRIPTION Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. / True clock of differential PCIEX pair 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Stops all CPUCLK, except those set to be free running clocks Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0 level, when input low 3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ# Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. 30 31 32 33 CPUCLKT2_ITP/PCIEXT6 VDDA GNDA IREF OUT PWR PWR OUT 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 GND SCLK SDATA VDDREF X2 X1 GND REF0 REF1/FSLC/TEST_SEL CPU_STOP# PCI/SRC_STOP# PCICLK2/REQ_SEL** VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND OUT OUT PWR OUT OUT PWR IN I/O PWR OUT IN PWR OUT I/O IN IN I/O PWR PWR OUT OUT OUT PWR IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 5 954226 Programmable Timing Control HubTM for Mobile P4TM Systems General Description The ICS954226 is a CK410M compatible clock synthesizer. It provides a single-chip solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. The device is driven with a 14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI Express. Block Diagram REF(1:0) USB_48MHz X1 X2 XTAL OSC. FIXED PLL DIVIDER DOT_96MHz PCICLK(5:2) PCICLK_F(1:0) PROG. SPREAD MAIN PLL PCIEX(5:1) PROG. DIVIDERS CPUCLK2/PCIEX6 PCI/SRC_STOP# CPU_STOP# FSL(C:A) ITP_EN TEST_MODE TEST_SEL VTT_PWRGD#/PD PEREQ#(2:1) SDATA SCLK SELPCIEX_LCDCLK# REQ_SEL CPUCLK(1:0) LCDCLK_SS/PCIEX0 CONTROL LOGIC SATACLK IREF IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 6 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Table2: LCDCLK Spread and Frequency Selection Table Byte 6b7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Byte 6b6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Byte 6b5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Byte 6b4 Byte 6b3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin 17/18 MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 Spread % 0.8 Down 1 Down 1.25 Down 1.5 Down 1.75 Down 2 Down 2.5 Down 3 Down +/-0.3 Center +/-0.4 Center +/-0.5 Center +/-0.6 Center +/-0.8 Center +/-1.0 Center +/-1.25 Center +/-1.5 Center 0.8 Down 1 Down 1.25 Down 1.5 Down 1.75 Down 2 Down 2.5 Down 3 Down +/-0.3 Center +/-0.4 Center +/-0.5 Center +/-0.6 Center +/-0.8 Center +/-1.0 Center +/-1.25 Center +/-1.5 Center IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 7 954226 Programmable Timing Control HubTM for Mobile P4TM Systems General SMBus serial interface information for the 954226 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK * By default, SMBADR = 0, therefore, SMBus WRITE/READ address is D0/D1. Please see SMBus Address Selection table on page 1. Byte N + X - 1 N P Not acknowledge stoP bit IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 8 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: Output Control Register Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name CPUCLK2_ITP/PCIEX6 Enable PCIEX5 Enable PCIEX4 Enable SATACLK Enable PCIEX3 Enable PCIEX2 Enable PCIEX1 Enable LCDCLK/PCIEX0 Enable Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 SMBus Table: Spread and Output Control Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Test Clock Mode Entry DOT_96MHz Enable USB_48MHz Enable REF_0 Enable LCDCLK/PCIEX0 Spectrum Mode CPUCLK1 CPUCLK0 Spread Spectrum Mode Control Function Test Mode Output Enable Output Enable Output Enable Spread Control Output Enable Output Enable Spread Control for PLL1 Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable OFF Disable Disable OFF 1 Enable Enable Enable Enable ON Enable Enable ON PWD 0 1 1 1 1 1 1 0 SMBus Table: Output Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCICLK5 PCICLK4 PCICLK3 PCICLK2 Test Mode Selection PCI_STOP PCI_F0 Enable PCI_F1 Enable Control Function Output Enable Output Enable Output Enable Output Enable Test Mode Selection Stop all PCI, PCIEX and SATA clocks Output Enable Output Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Hi-Z Enable Disable Disable 1 Enable Enable Enable Enable REF/N Disable Enable Enable PWD 1 1 1 1 0 1 1 1 SMBus Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCIEX6 PCIEX5 PCIEX4 SATACLK PCIEX3 PCIEX2 PCIEX1 PCIEX0 Allow assertion of PCI_STOP# or setting of PCI_STOP control bit in SMBus register to stop PCIEX clocks Control Function Type RW RW RW RW RW RW RW RW 0 Free Running Free Running Free Running Free Running Free Running Free Running Free Running Free Running 1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable PWD 0 0 0 0 0 0 0 0 IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 9 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: Output Control Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name REF_1 Enable 96MHz REF_0 STRENGTH PCI_F1 PCI_F0 CPUCLK2_ITP CPUCLK1 CPUCLK0 Control Function Output Enable Driven in PD Strength Programming Allow assertion of PCI_STOP# or setting of Allow assertion of CPU_STOP# to stop CPUCLK outputs Type RW RW RW RW RW RW RW RW 0 Disable Driven 1X Free Running Free Running Free Running Free Running Free Running 1 Enable Hi-Z 2X Stoppable Stoppable Stoppable Stoppable Stoppable PWD 1 1 1 0 0 1 1 1 SMBus Table: Output Control Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCI_STOP Drive Mode CPUCLK2_ITP_STOP Drive Mode CPUCLK1_STOP Drive Mode CPUCLK0_STOP Drive Mode PCIEX (6:0) Drive Mode CPUCLK2_ITP_PD Drive Mode CPUCLK[1:0] PD Drive Mode ITP_EN Driven in Powerdown (PD) Control Function Driven in PCI_STOP# Type RW RW Driven in CPU_STOP# RW RW RW RW RW PCIEX/CPU_ITP select RW 0 Driven Driven Driven Driven Driven Driven Driven PCIEX 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z CPU_ITP PWD 0 0 0 0 0 0 0 latch SMBus Table: Output Control Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SS4 SS3 SS2 SS1 SS0 FSLC FSLB FSLA Control Function LCDCLK Spread Prog Bit 4 LCDCLK Spread Prog Bit 3 LCDCLK Spread Prog Bit 2 LCDCLK Spread Prog Bit 1 LCDCLK Spread Prog Bit 0 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW See Table 2: LCDCLK Freq Sel 0 96Mhz 1 100Mhz PWD 0 1 0 0 0 Latched Latched Latched See Table 1: PLL1 Frequency Selection Table SMBus Table: Vendor & Revision ID Register Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD x x x x 0 0 0 1 VENDOR ID IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 10 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: Byte Count Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 1 1 1 Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. SMBus Table: Watchdog Timer Register Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name WDH_EN WDS_EN WD Hard Status WD Soft Status WDTCtrl WD2 WD1 WD0 Control Function Watchdog Hard Alarm Enable Watchdog Soft Alarm Enable WD Hard Alarm Status WD Soft Alarm Status Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type RW RW R R RW RW RW RW 0 Disable Disable Normal Normal 290ms Base 1 Enable Enable Alarm Alarm 1160ms Base PWD 0 0 X X 0 1 1 1 These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s. SMBus Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name M/N_EN LCDCLK/PCIEX0 SEL REQ_SEL LCDCLK/PCIEX0 WD Safe Freq Source WD SFC WD SFB WD SFA Control Function PLLM/N Programming Enable SELPCIEX0/LCDCLK# REQ_SEL Driven in PD WD Safe Freq Source Watch Dog Safe Freq Programming bits Type RW RW RW RW RW RW RW RW 0 Disable LCDCLK PCIEX5 Driven Latch Inputs/Byte6[2:0] 1 Enable PCIEX0 PEREQ Hi-Z B10b(2:0) PWD 0 latch latch 0 0 0 0 0 Writing to these bit will configure the safe frequency as Byte0 bit (4:0). SMBus Table: VCO Frequency Control Register Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 N Div 9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 M Divider Programming bits Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 11 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X N Divider Programming b(8:0) The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] SMBus Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X Spread Spectrum Programming b(7:0) These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. SMBus Table: Spread Spectrum Control Register Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Spread Spectrum Programming b(14:8) Control Function Reserved Type R RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 PWD 0 X X X X X X X SMBus Table: Output Divider Control Register Byte 15 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name PCIEX Div3 PCIEX Div2 PCIEX Div1 PCIEX Div0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function PCIEX Divider Ratio Programming Bits Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/15 0000:/2 0001:/3 0010:/5 0011:/15 0 0100:/4 0101:/6 0110:/10 0111:/30 0100:/4 0101:/6 0110:/10 0111:/30 1000:/8 1001:/12 1010:/20 1011:/60 1000:/8 1001:/12 1010:/20 1011:/60 1 1100:/16 1101:/24 1110:/40 1111:/120 1100:/16 1101:/24 1110:/40 1111:/120 PWD X X X X X X X X CPUDivider Ratio Programming Bits IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 12 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: PEREQ# Control Register Control Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved PEREQ2# controls selected outputs. Outputs controlled by this pin will be Hi-Z when PEREQ2# is high. Reserved PEREQ1# controls selected outputs. Outputs controlled by this pin will be Hi-Z when PEREQ1# is high. Function Reserved PCIEX4 is controlled PCIEX3 is controlled PCIEX1 is controlled Reserved SATACLK is controlled PCIEX2 is controlled PCIEX0 is controlled Type RW RW RW RW RW RW RW RW 0 Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled 1 Controlled Controlled Controlled Controlled Controlled Controlled PWD 0 0 0 0 0 0 0 0 SMBus Table: PLL 2 VCO Frequency Control Register Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 M Divider Programming bits Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X SMBus Table: PLL 2 VCO Frequency Control Register Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X N Divider Programming b(8:0) The decimal representation of M and N Divier in Byte 17 and 18 will configure the VCO frequency. Default at power up = Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] SMBus Table: PLL 2 Spread Spectrum Control Register Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function Type RW RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. 0 1 PWD X X X X X X X X Spread Spectrum Programming b(7:0) IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 13 954226 Programmable Timing Control HubTM for Mobile P4TM Systems SMBus Table: PLL2 Spread Spectrum Control Register Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Spread Spectrum Programming b(14:8) Control Function Reserved Type R RW RW RW RW RW RW RW 0 1 PWD 0 X X X X X X X These Spread Spectrum bits in Byte 19 and 20 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 14 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Absolute Maximum Rating PARAMETER 3.3V Core Supply Voltage SYMBOL VDDA CONDITIONS -65 0 2000 MIN TYP MAX 4.6 4.6 150 70 125 UNITS V V ° Notes 1 1 1 1 1 1 3.3V Logic Input Supply VDD Voltage Storage Temperature Ts Ambient Operating Temp Tambient Junction Temperature Tj Input ESD protection HBM ESD prot 1 C °C °C V Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Input High Voltage Input Low Voltage Input High Current I nput Low Current Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance SYMBOL V IH V IL I IH I IL1 I IL2 VIH_FSL VIL_FSL IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of @ IPULLUP 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 1000 300 MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 1.7 0.35 400 70 12 14.31818 7 5 6 5 1.8 30 33 300 5 5 5.5 0.4 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns Notes 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Clk Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time 1 2 VDD VOL IPULLUP TRI2C TFI2C 2.7 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 15 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom MIN 3000 660 -150 -300 250 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 850 150 1150 550 140 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 TYP MAX UNITS Ω mV mV mV mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % % ps ps ps ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 1 1 Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation Rise/Fall Matching Duty Cycle Skew Skew Jitter, Cycle to cycle Jitter, Cycle to cycle 1 2 3 tr tf d-tr d-tf trfm dt3 tsk3 700 700 125 125 20 55 100 150 125 85 45 CPU(1:0), VT = 50% CPU(1:0) to CPU2_ITP, tsk4 VT = 50% Measurement from differential wavefrom tjcyc-cyc (CPU2_ITP) Measurement from differential tjcyc-cyc wavefrom, (CPU(1:0)) *T A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 16 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Electrical Characteristics - SATA/PCIEX/LCDCLK_SS@100M 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Rise/Fall Matching Duty Cycle Skew Jitter, Cycle to cycle 1 2 3 SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm Tperiod Tabsmin tr tf d-tr d-tf trfm dt3 tsk3 CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom VT = 50% MIN 3000 660 -150 -300 250 -300 9.9970 9.9970 9.8720 175 175 TYP MAX UNITS Ω Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1 1 1 1 1 1 1 1 850 150 1150 550 140 300 10.0030 10.0533 700 700 125 125 20 55 250 125 mV mV mV mV mV mV ppm ns ns ns ps ps ps ps % % ps ps 45 tjcyc-cyc Measurement from differential wavefrom *TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9ΩΒ REF = 475Ω I Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ Z O=50Ω. Electrical Characteristics - DOT_96MHz/LCDCLK_SS@96M 0.7V Current Mode Differential Pair PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Rise/Fall Matching Duty Cycle Jitter, Cycle to cycle 1 2 3 SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf trfm dt3 CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 96.00MHz nominal 96.00MHz nominal VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom MIN 3000 660 -150 -300 250 -100 10.4135 10.1635 175 175 TYP MAX UNITS Ω Notes 1 1,3 1,3 1 1 1 1 1,2 2 1,2 1 1 1 1 1 1 1 850 150 1150 550 140 100 10.4198 700 700 125 125 20 55 250 mV mV mV mV mV mV ppm ns ns ps ps ps ps % % ps 45 tjcyc-cyc Measurement from differential wavefrom *T A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω, RP =49.9ΩΤIREF = 475Ω Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475Ω ( 1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ Z O=50Ω. IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 17 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Duty Cycle Group Skew Jitter, Cycle to cycle 1 SYMBOL RDSP VOH VOL I OH IOL tslewr/f dt1 tskew tjc y c-c y c CONDITIONS* VO = VDD*(0.5) I OH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN 12 2.4 -33 TYP MAX 55 0.55 -33 UNITS Ω V V mA mA mA mA V/ns % ps ps 30 38 1 45 4 55 500 250 Notes 1 1 1 1 1 1 1 1 1 1 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - 48MHz PARAMETER Long Accuracy Clock period Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Duty Cycle Jitter, Cycle to cycle 1 SYMBOL ppm Tperiod RDSP VOH VOL I OH IOL t slewr/f_48 dt1 tjc y c-c y c CONDITIONS* see Tperiod min-max values 48.00MHz output nominal VO = VDD*(0.5) I OH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V 48M Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VT = 1.5 V VT = 1.5 V MIN -100 20.8313 12 2.4 -33 TYP MAX 100 20.8354 55 0.55 -33 UNITS ppm ns Ω V V mA mA mA mA V/ns % ps Notes 1 1 1 1 1 1 1 1 1 1 1 30 38 1 45 2 55 500 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Duty Cycle Jitter 1 2 SYMBOL ppm Tperiod VOH VOL IOH IOL tslewr/f dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VT = 1.5 V VT = 1.5 V MIN -300 69.8270 2.4 -29 29 1 45 TYP MAX 300 69.8550 0.4 -23 27 4 55 1000 UNITS ppm ns V V mA mA V/ns % ps Notes 1,2 2 1 1 1 1 1 1 1 *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 39Ω Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 18 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Test Clarification Table Comments HW FSLC/TES FSLB/TES T_SEL T_MODE SW TEST ENTRY BIT W1b7 0 X X X REF/N or HI-Z W2b3 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N · FS_C/TES T_SEL is a 3-level latched input. o Power-up w/ V >= 2.0V to select TEST o Power-up w/ V < 2.0V to have pin function as FS_C. · When pin is FS_C, VIH_FS and VIL_FS levels apply. · FS_B/TEST_MODE is a low-threshold input o VIH_FS and VIL_FS levels apply. o TEST_MODE is a real time input · TEST_SEL can be invoked after power up through SMBus B1b7. o If TEST is selected by B1b7, only B2b3 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. · Power must be cycled to exit TEST. HW PIN 0 1 1 1 HW PIN X 0 0 1 1 1 X 1 REF/N 0 X 1 0 HI-Z 0 X 1 1 REF/N W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) W2b3: 1= REF/N, Default = 0 (HI-Z) IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 19 954226 Programmable Timing Control HubTM for Mobile P4TM Systems N c L INDEX AREA E1 E 12 D a A2 A1 A 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil ) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N 56 10-0039 -Ce b SEATING PLANE aaa C D mm. MIN MAX 13.90 14.10 D (inch) MIN .547 MAX .555 Reference Doc.: JEDEC Publicat ion 95, M O-153 IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 20 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Seating Plane Index Area N Anvil Singulation A1 A3 L (Ref.) (N D -1)x e (Ref.) ND & N Even N 1 (T yp.) e 2 If N & N D are Even (N -1)x e 2 E2 E2 2 (Ref.) OR Top V iew Sawn Singulation b A (Re f.) e D2 2 D2 D ND & N Odd C Thermal Base Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC ICS 56L SYMBOL VLLD-2 / -5 TOLERANCE N 56 56 ND 14 14 NE 14 14 D x E BASIC 8.00 x 8.00 8.00 x 8.00 D2 MIN. / MAX. 2.75 / 6.80 4.35 / 4.65 E2 MIN. / MAX. 2.75 / 6.80 5.05 / 5.35 L MIN. / MAX. 0.30 / 0.50 0.30 / 0.50 Ordering Information Part / Order Number 954226AGLF 954226AGLFT 954226AKLF 954226AKLFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 56-pin TSSOP 56-pin TSSOP 56-pin MLF 56-pin MLF Temperature 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C “LF” to the suffix are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). IDT® Programmable Timing Control HubTM for Mobile P4TM Systems 0930A—04/13/10 21 954226 Programmable Timing Control HubTM for Mobile P4TM Systems Revision History Rev. 0.1 0.2 Issue Date 3/29/2005 7/14/2006 Who JC DC Description Updated Ordering Information from "Lead Free" to "Annealed Lead Free" Added MLF Pinout, Pin Description and Ordering Information. 1. Clean up Electrical Tables 2. Corrected Test Clarification Table 3. Move to final Page # 18 1, 4, 5, 21 A 4/12/2010 RDW Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 22