9DB102BFILF

DATASHEET Two Output Differential Buffer for PCIe Gen1 & Gen2 Description The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. ICS9DB102 Features/Benefits • • • • • • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Industrial temperature range available Output Features • 2 - 0.7V current mode differential output pairs (HCSL) Key Specifications • • Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps Functional Block Diagram CLKREQ0# CLKREQ1# PCIEX0 CLK_INT SPREAD COMPATIBLE PLL PCIEX1 C LK_IN C PLL_BW SMBDAT SMBCLK CONTROL LOGIC IREF IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 1 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Pin Configuration PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA GNDA IREF **CLKREQ1# VDD GND PCIEXT1 PCIEXC1 VDD SMBCLK Power Groups Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PIN NAME PLL_BW CLK_INT CLK_INC **CLKREQ0# VDD GND PCIEXT0 PCIEXC0 VDD SMBDAT SMBCLK VDD PCIEXC1 PCIEXT1 GND VDD **CLKREQ1# PIN TYPE INPUT INPUT INPUT INPUT POWER POWER OUTPUT OUTPUT POWER I/O INPUT POWER OUTPUT OUTPUT POWER POWER INPUT DESCRIPTION 3.3V input for selecting PLL Band Width 0 = low, 1= high "True" reference clock input. "Complementary" reference clock input. Output enable for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant Power supply, nominal 3.3V Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Ground pin. Power supply, nominal 3.3V Output enable for SRC/PCI Express output pair '1' 0 = enabled, 1 = tri-stated This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 18 19 20 IREF GNDA VDDA ICS9DB102 Pin Number VDD GND 5,9,12,16 6,15 9 6 20 19 20 19 Description PCI Express Outputs SMBUS IREF Analog VDD & GND for PLL core OUTPUT POWER POWER Note: Pins preceeded by '**' have internal 120K ohm pull down resistors IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 2 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Absolute Max Symbol VDDA VDD Ts Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Output Supply Voltage Storage Temperature Case Temperature Input ESD protection human body model Min GND - 0.5 -65 Max V DD + 0.5V V DD + 0.5V 150 115 Units V V C ° C V ° 2000 Electrical Characteristics - Input/Supply/Common Output Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Tambient Input High Voltage Input Low Voltage Input High Current SYMBOL Tambcom Tambind V IH V IL IIH IIL1 Input Low Current IIL2 Operating Supply Current Input Frequency 3 Pin Inductance1 Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Spread Spectrum Modulation Frequency PLL Bandwidth SMBus Voltage Low-level Output Voltage Current sinking at V OL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time 1 CONDITIONS Commercial range Industrial range 3.3 V +/-5% 3.3 V +/-5% V IN = V DD V IN = 0 V; Inputs with no pullup resistors V IN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; all differential pairs tri-stated V DD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock Triangular Modulation Lexmark Modulation PLL Bandwidth when PLL_BW=0 PLL Bandwidth when PLL_BW=1 MIN 0 -40 2 VSS - 0.3 -5 -5 -200 TYP MAX 70 85 V DD + 0.3 0.8 5 UNITS NOTES ° C ° C V V uA uA uA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I DD3.3OP Fi Lpin CIN COUT TSTAB 80 75 27 100 100 50 105 7 5 4.5 1.8 mA mA MHz nH pF pF ms kHz KHz KHz MHz 30 25 400 1.2 2.7 33 45 fMOD BW VDD V OLSMBUS IPULLUP TRI2C TFI2C @ IPULLUP SMBus SDATA pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 5.5 0.4 4 1000 300 V V mA ns ns Guaranteed by design and characterization, not 100% tested in production. IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 3 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair TA = Tambient; VDD = 3.3 V +/-5%; CL P ARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage Vuds Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Input to Output Delay Duty Cycle Output-to-Output Skew Jitter, Cycle to cycle 1 = 2pF, RS=33.2 , RP=49.9 , IREF = 475 CONDITIONS MIN VO = Vx Statistical measurement on single ended signal using Measurement on single ended signal using absolute value. 3000 660 -150 -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V V OL = 0.175V TYP MAX UNITS NOTES 1 850 150 1150 350 12 550 140 0 10.0030 10.0533 700 700 125 125 150 4.2 55 25 35 30 mV mV mV mV ppm ns ns ns ps ps ps ps ps ns % ps ps ps 1,3 1,3 1,3 1,3 1,3 1,3 1,2 2 2 1,2 1 1 1 1 1 1 1 1 1 1 d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf tpd tpdbyp dt3 tsk3 tjcyc-cyc tjcyc-cycbyp 9.9970 9.9970 9.8720 175 175 30 30 PLL Mode. Bypass mode Measurement from differential wavefrom V T = 50% PLL mode. Measurement from differential wavefrom Additve Jitter in Bypass Mode 0 3.7 45 . Guaranteed by design, not 100% tested in production. 2 The 9DB102 does not add a ppm error to the input clock 3 IREF = V DD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 . IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 4 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Electrical Characteristics - PLL Parameters TA = Tambient; Supply Voltage VDD = 3.3 V +/-5% Group PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Parameter jpeak-hibw jpeak-lobw pllHIBW pllLOBW Description (PLL_BW = 1) (PLL_BW = 0) (PLL_BW = 1) (PLL_BW = 0) PCIe Gen 1 phase jitter (1.5 - 22 MHz) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band