9DB1200CGLFT

DATASHEET Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Description DB1200 Rev 2.0 Intel Yellow Cover Device 9 DB1200C Features/Benefits • • • 3 selectable SMBus addresses for easy system expansion Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread Supports undriven differential outputs in Power Down Mode for power management. General Description The ICS9DB1200 is an Intel DB1200 Differential Buffer Specification device. This buffer provides 12 differential clocks at frequencies ranging from 100MHz to 400 MHz. The ICS9DB1200 is driven by a differential output from a CK410B+ or CK509B main clock generator. Key Specifications • • • • • • Output cycle-cycle jitter < 50ps. Output to output skew: 50ps Phase jitter: PCIe Gen2 < 3.1ps rms Phase jitter: QPI < 0.5ps rms 64-pin TSSOP Package Available in RoHS compliant packaging Output Features • • • • • 12 - 0.7V current-mode differential output pairs. Supports zero delay buffer mode and fanout mode. Bandwidth programming available. 100-400 MHz operation in PLL mode 33-400 MHz operation in Bypass mode Functional Block Diagram 12 OE_(11:0)# SRC_IN SRC_IN# SPREAD COMPATIBLE PLL M U X 12 DIF(11:0)) FS(2:0) HIGH_BW# BYPASS#/PLL VTTPWRGD#/PD ADR_SEL SMBDAT SMBCLK CONTROL LOGIC IREF IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 1414F—06/30/10 1 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Pin Configuration VDD DIF_IN DIF_IN# GND OE0# DIF_0 DIF_0# VDD GND OE1# DIF_1 DIF_1# OE2# DIF_2 DIF_2# GND VDD OE3# DIF_3 DIF_3# OE4# DIF_4 DIF_4# VDD GND OE5# DIF_5 DIF_5# **ADR_SEL HIGH_BW# FS2 SMBCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDA AGND IREF FS0 OE11# DIF_11 DIF_11# VDD GND OE10# DIF_10 DIF_10# OE9# DIF_9 DIF_9# GND VDD OE8# DIF_8 DIF_8# OE7# DIF_7 DIF_7# VDD GND OE6# DIF_6 DIF_6# VTTPWRGD#/PD BYPASS#/PLL FS1 SMBDAT 64-TSSOP ** Indicates 120K ohm Pulldown 9DB1200C Frequency Select Table FSL2 FSL1 FSL0 B0b2 B0b1 B0b0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Input MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 Hi-Z DIF_x; MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 Hi-Z SMBus Address Selection (Pin 29) ADR_SEL Voltage SMBus Adr (Wr/Rd) Low