9DB1233AGLF

DATASHEET Twelve Output Differential Buffer for PCIe Gen3 Recommended Application 12 output PCIe Gen3 zero-delay/fanout buffer 9 DB1233 Features/Benefits • • • • • • • 3 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment 12 OE# pins/Hardware control of each output PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Supports undriven differential outputs in Power Down mode for power management General Description The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features • 12 - 0.7V current mode differential HCSL output pairs • • • • Key Specifications Output cycle-cycle jitter < 50ps. Output-to-output skew < 50 ps PCIe Gen3 phase jitter < 1.0ps RMS Pin compatible with DB1200 Yellow Cover Device Functional Block Diagram 12 OE_(11:0)# DIF_IN DIF_IN# SPREAD COMPATIBLE PLL M U X 12 DIF(11:0)) HIGH_BW# BYPASS#/PLL VTTPWRGD#/PD ADR_SEL SMBDAT SMBCLK IREF CONTROL LOGIC IDT® Twelve Output Differential Buffer for PCIe Gen3 1675B—11/08/10 1 9DB1233 Twelve Output Differential Buffer for PCIe Gen3 Pin Configuration VDD DIF_IN DIF_IN# GND OE0# DIF_0 DIF_0# VDD GND OE1# DIF_1 DIF_1# OE2# DIF_2 DIF_2# GND VDD OE3# DIF_3 DIF_3# OE4# DIF_4 DIF_4# VDD GND OE5# DIF_5 DIF_5# **ADR_SEL HIGH_BW# VDD SMBCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDA AGND IREF VDD OE11# DIF_11 DIF_11# VDD GND OE10# DIF_10 DIF_10# OE9# DIF_9 DIF_9# GND VDD OE8# DIF_8 DIF_8# OE7# DIF_7 DIF_7# VDD GND OE6# DIF_6 DIF_6# VTTPWRGD#/PD BYPASS#/PLL GND SMBDAT 64-TSSOP ** Indicates 120K ohm Pulldown 9DB1233 SMBus Address Selection (Pin 29) ADR_SEL Voltage SMBus Adr (Wr/Rd) Low