9DBL411BGILF

DATASHEET Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI Recommended Application: PCI-Express Gen2 or QPI fanout buffer 9 DBL411B Features/Benefits: • • • • Low power differential outputs for PCIExpress and QPI clocks Power down mode when all OE# are high Available in I-temp 20-pin MLF or TSSOP packaging Output Features: • • 4 - low power differential output pairs Individual OE# control of each output pair General Description: Key Specifications: • • Output cycle-cycle jitter < 15ps additive Output to output skew: < 50ps The 9DBL411B is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 150 MHz. Power Groups Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Description VDD_IO for DIF(3:0) 3.3V Analog VDD & GND Functional Block Diagram 4 OE#(3:0) DIF_INT DIF_INC STOP LOGIC 4 DIF_LPR(3:0) IDT® Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI 1645C—10/18/10 1 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information Pin Configurations DIF0C_LPR DIF0T_LPR DIF_INC DIF_INT OE0# 20 19 18 17 16 VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 1 2 3 4 5 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR 9DBL411B 6 VDD_IO 7 GND 8 DIF2C_LPR 9 10 DIF2T_LPR OE2# OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR 20-pin MLF 20-pin TSSOP Terminations 9DBL411B Zo Zo 9DBL411 Rs Rs Zo – 17 = Rs (ohms), where Zo is the single-ended intrinsic impedance of the board transmission line. Single-ended intrinsic impedance is ½ that of the differential impedance. Single Ended Rs Impedance 5% Rs (Zo) tolerance 2% tolerance Notes 50 33 33.2 In general, 5% resistors 45 27 27.4 may be used. All values are 42.5 24 or 27 24.9 in ohms. IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 1645C—10/18/10 2 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information TSSOP Pin Description PIN # (TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR OE2# DIF1C_LPR DIF1T_LPR OE1# GND VDD_IO DIF0C_LPR DIF0T_LPR PIN TYPE IN IN IN PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT DESCRIPTION Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 1645C—10/18/10 3 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information MLF Pin Description PIN # (MLF) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND DIF2C_LPR DIF2T_LPR OE2# DIF1C_LPR DIF1T_LPR OE1# GND VDD_IO DIF0C_LPR DIF0T_LPR OE0# DIF_INC DIF_INT PIN TYPE PWR GND IN OUT OUT PWR GND OUT OUT IN OUT OUT IN GND PWR OUT OUT IN IN IN DESCRIPTION 3.3V Power for the Analog Core Ground for the Analog Core Output Enable for DIF3 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Power supply for low power differential outputs, nominal 1.05V to 3.3V Ground pin Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF2 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF1 output. Control is as follows: 0 = enabled, 1 = Low-Low Ground pin Power supply for low power differential outputs, nominal 1.05V to 3.3V Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed) Output Enable for DIF0 output. Control is as follows: 0 = enabled, 1 = Low-Low Complement side of differential input clock True side of differential input clock IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 1645C—10/18/10 4 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information Absolute Maximum Ratings PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Ambient Operating Temp Storage Temperature Input ESD protection SYMBOL VDDA VDD_IO VIH VIL TambCOM TambIND Ts ESD prot CONDITIONS Core Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Commercial Range Industrial Range Human Body Model Vss - 0.5 0 -40 -65 2000 70 85 150 0.99 MIN MAX 4.6 3.8 4.6 UNITS V V V V °C °C ° Notes 1,7 1,7 1,7,8 1,7 1 1 1,7 1,7 C V Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Differential Input High Voltage Differential Input Low Voltage Input Slew Rate - DIF_IN Input Leakage Current Operating Supply Current SYMBOL VDDxxx VDDxxx_IO VIHSE VILSE VIHDIF VILDIF dv/dt IIN IDD_3.3V IDD_IO_133M IDD_SB_3.3V IDD_SBIO Fi Lpin CIN COUT TOE#LAT Logic Inputs Output pin capacitance Number of clocks to enable or disable output from assertion/deassertion of OE# Delay from assertion of first OE# to first clock out (assumes input clock running) Output enable after OE# de-assertion Fall/rise time of OE# inputs 1.5 CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Measured differentially VIN = VDD , VIN = G ND VDDA supply current VDD_IO supply @ fOP = 133MHz VDDA supply current, Input stopped, OE# pins all high VDD_IO supply, Input stopped, OE# pins all high VDD = 3.3 V MIN 3.000 0.99 2 VSS - 0.3 600 VSS - 0.3 0.4 -5 MAX 3.600 3.600 VDD + 0.3 0.8 1.15 300 8 5 20 20 750 150 15 150 7 5 6 1 3 UNITS V V V V V V V/ns uA mA mA uA uA MHz nH pF pF periods Notes 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 Power Down Current (All OE# pins High) Input Frequency Pin Inductance Input Capacitance OE# latency (at least one OE# is low) Clock stabilization time (from all OE# high to first OE# low). Tdrive_OE# Tfall_OE# Trise_OE# TSTAB TDROE# TFALL TRISE 150 10 5 5 ns ns ns ns 1 1 1 1 IDT® Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI 1645C—10/18/10 5 9DBL411B Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI Advance Information AC Electrical Characteristics - DIF Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle Distortion Additive Cycle to Cycle Jitter DIF[3:0] Skew Propagation Delay Additive Phase Jitter - PCIe Gen1 Additive Phase Jitter - PCIe Gen2 High Band Additive Phase Jitter PCIe Gen2 Low Band Additive Phase Jitter QPI133 (6.4GBs, 12 UI) 1 2 3 4 5 SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYCDIS0 DIFJ C2CADD DIFSKEW tPD tphase_addPCIG1 tphase_addPCIG2HI tphase_addPCIG2LO tphase_addQPI6G4 CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement, fIN