9EMS9633BFILF

Datasheet ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) for Embedded Applications ICS9EMS9633 Features/Benefits: • • • • • • • • Industrial temperature range compliant Supports ULV CPUs with 67 to 167 MHz CPU outputs Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins CPU STOP# input for power manangment Fully integrated Vreg Integrated series resistors on differential outputs 1.5V VDD IO operation, 3.3V VDD core and REF supply pin for REF -40 to +85C operating range Output Features: • • • • • 3 - CPU low power differential push-pull pairs 3 - SRC low power differential push-pull pairs 1 - LCD100 SSCD low power differential push-pull pair 1 - DOT96 low power differential push-pull pair 1 - REF, 14.31818MHz, 3.3V SE output SSOP Pin Configuration REF GNDREF VDDCORE_3.3 FSC_L TEST_MODE TEST_SEL SCLK SDATA VDDCORE_3.3 VDDIO_1.5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.5 VDDCORE_3.3 *CR#0 GNDSRC SRCC0_LPR SRCT0_LPR *CR#1 VDDCORE_3.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF_3.3 X1 X2 CLKPWRGD#/PD_3.3 CPU_STOP# CPUT0_LPR CPUC0_LPR VDDIO_1.5 GNDCPU CPUT1_LPR CPUC1_LPR VDDCORE_3.3 VDDIO_1.5 GNDCPU CPUT2_LPR CPUC2_LPR FSB_L *CR#2 SRCT2_LPR SRCC2_LPR GNDSRC SRCT1_LPR SRCC1_LPR VDDIO_1.5 48 SSOP Package * indicates inputs with internal pull up of ~10Kohm to 3.3V IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 9EMS9633 1 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet SSOP Pin Description PIN # PIN NAME 1 REF 2 GNDREF 3 VDDCORE_3.3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FSC_L TEST_MODE TEST_SEL SCLK SDATA VDDCORE_3.3 VDDIO_1.5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.5 VDDCORE_3.3 *CR#0 GNDSRC SRCC0_LPR SRCT0_LPR *CR#1 VDDCORE_3.3 TYPE DESCRIPTION OUT 14.318 MHz reference clock. PWR Ground pin for the REF outputs. PWR 3.3V power for the PLL core Low threshold input for CPU frequency selection. Refer to input electrical IN characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode IN while in test mode. Refer to Test Clarification Table. TEST_SEL: latched input to select TEST MODE IN 1 = All outputs are tri-stated for test 0 = All outputs behave normally . IN Clock pin of SMBus circuitry, 5V tolerant. I/O Data pin for SMBus circuitry, 3.3V tolerant. PWR 3.3V power for the PLL core PWR Power supply f or low power differential outputs, nominal 1.5V. Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm OUT resistor to GND needed. No Rs needed. True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor OUT to GND needed. No Rs needed. PWR Ground pin for DOT clock output PWR Ground pin for LCD clock output Complement clock of low power differential pair for LCD100 SS clock. No 50ohm OUT resistor to GND needed. No Rs needed. True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to OUT GND needed. No Rs needed. PWR Power supply for low power differential outputs, nominal 1.5V. PWR 3.3V power for the PLL core IN Clock request for SRC0, 0 = enable, 1 = disable PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC1, 0 = enable, 1 = disable PWR 3.3V power for the PLL core IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 2 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet SSOP Pin Description (continued) PIN # PIN NAME 25 VDDIO_1.5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SRCC1_LPR SRCT1_LPR GNDSRC SRCC2_LPR SRCT2_LPR *CR#2 FSB_L CPUC2_LPR CPUT2_LPR GNDCPU VDDIO_1.5 VDDCORE_3.3 CPUC1_LPR CPUT1_LPR GNDCPU VDDIO_1.5 CPUC0_LPR CPUT0_LPR CPU_STOP# CLKPWRGD#/PD_3.3 X2 X1 VDDREF_3.3 TYPE DESCRIPTION PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC2, 0 = enable, 1 = disable Low threshold input for CPU frequency selection. Refer to input electrical IN characteristics for Vil_FS and Vih_FS values. Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs PWR Power supply for low power differential outputs, nominal 1.5V. PWR 3.3V power for the PLL core Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs PWR Power supply f or low power differential outputs, nominal 1.5V. Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. IN Stops all CPU clocks, except those set to be free running clocks IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. / Asynchronous active high input pin used to place the device into a power down state. OUT Crystal output, Nominally 14.318MHz IN Crystal input, Nominally 14.318MHz. PWR Power pin for the XTAL and REF clocks, nominal 3.3V IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 3 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet MLF Pin Configuration VDDCORE_3.3 CPUC0_LPR CPUC1_LPR CPUC2_LPR CPUT0_LPR CPUT1_LPR CPUT2_LPR VDDIO_1.5 VDDIO_1.5 GNDCPU GNDCPU 48 47 46 45 44 43 42 41 40 39 38 37 CPU_STOP# CLKPWRGD#/PD_3.3 X2 X1 VDDREF_3.3 REF GNDREF VDDCORE_3.3 FSC_L TEST_MODE TEST_SEL SCLK_3.3 1 2 3 4 5 6 7 8 9 10 11 12 SDATA_3.3 VDDCORE_3.3 36 35 34 33 32 31 30 29 28 27 26 25 *CR#0 *CR#2 SRCT2_LPR SRCC2_LPR GNDSRC SRCT1_LPR SRCC1_LPR VDDIO_1.5 VDDCORE_3.3 *CR#1 SRCT0_LPR SRCC0_LPR GNDSRC ICS9EMS9633 13 14 15 16 17 18 19 20 21 22 23 24 DOT96C_LPR DOT96T_LPR LCD100T_LPR VDDIO_1.5 LCD100C_LPR VDDIO_1.5 GNDDOT GNDLCD VDDCORE_3.3 48-pin MLF, 6x6 mm, 0.4mm pitch * indicates inputs with internal pull up of ~10Kohm to 3.3V IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications FSB_L 1617—08/19/09 4 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet MLF Pin Description PIN # PIN NAME 1 CPU_STOP# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CLKPWRGD#/PD_3.3 X2 X1 VDDREF_3.3 REF GNDREF VDDCORE_3.3 FSC_L TEST_MODE TEST_SEL SCLK_3.3 SDATA_3.3 VDDCORE_3.3 VDDIO_1.5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.5 VDDCORE_3.3 *CR#0 TYPE DESCRIPTION IN Stops all CPU clocks, except those set to be free running clocks IN OUT IN PWR OUT PWR PWR IN IN IN IN I/O PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. / Asynchronous active high input pin used to place the device into a power down state. Cry stal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Power pin for the XTAL and REF clocks, nominal 3.3V 14.318 MHz reference clock. Ground pin for the REF outputs. 3.3V power for the PLL core Low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. TEST_SEL: latched input to select TEST MODE 1 = All outputs are tri-stated for test 0 = All outputs behave normally. Clock pin of SMBus circuitry , 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. 3.3V power for the PLL core Power supply f or low power differential outputs, nominal 1.5V. Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor to GND needed. No Rs needed. Ground pin for DOT clock output Ground pin for LCD clock output Complement clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to GND needed. No Rs needed. True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to GND needed. No Rs needed. Power supply for low power differential outputs, nominal 1.5V. 3.3V power for the PLL core Clock request for SRC0, 0 = enable, 1 = disable IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 5 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet MLF Pin Description (continued) PIN # PIN NAME 25 GNDSRC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SRCC0_LPR SRCT0_LPR *CR#1 VDDCORE_3.3 VDDIO_1.5 SRCC1_LPR SRCT1_LPR GNDSRC SRCC2_LPR SRCT2_LPR *CR#2 FSB_L CPUC2_LPR CPUT2_LPR GNDCPU VDDIO_1.5 VDDCORE_3.3 CPUC1_LPR CPUT1_LPR GNDCPU VDDIO_1.5 CPUC0_LPR CPUT0_LPR TYPE DESCRIPTION PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC1, 0 = enable, 1 = disable PWR 3.3V power for the PLL core PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm OUT series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC2, 0 = enable, 1 = disable Low threshold input for CPU frequency selection. Refer to input electrical IN characteristics for Vil_FS and Vih_FS values. Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs PWR Power supply for low power differential outputs, nominal 1.5V. PWR 3.3V power for the PLL core Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs PWR Power supply for low power differential outputs, nominal 1.5V. Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated OUT 33ohm series resistor. No 50 ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm OUT series resistor. No 50 ohm resistor to GND needed. IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 6 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Funtional Block Diagram X1 X2 REF OSC SRC(2:0) CPU, SRC SS-PLL CPU(2:0) LCD SS-PLL LCD100_SSC 96M Non-SS PLL DOT96MHz FSLC FSLB CKPWRGD/PD# CPU_STOP# CR#(2:0) TESTSEL TESTMODE SMBDAT SMBCLK Control Logic Power Groups Pin Number Description VDD GND 41, 46 Low power outputs 40, 45 CPUCLK 42 VDDCORE_3.3V 30 Low power outputs 25, 33 SRCCLK 29 VDDCORE_3.3V 22 Low power outputs LCDCLK 19 23 VDDCORE_3.3V 15 Low power outputs 18 DOT 96Mhz 14 VDDCORE_3.3V Xtal, REF 5 7 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 7 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Absolute Maximum Ratings PARAMETER 3.3V Supply Voltage 1.5V Supply Voltage 3.3_Input High Voltage Minimum Input Voltage Storage Temperature Input ESD protection SYMBOL VDDxxx_3.3 VDDxxx_1.5 VIH3.3 VIL Ts ESD prot CONDITIONS Supply Voltage Supply Voltage 3.3V Inputs Any Input Human Body Model Man Machine Model GND - 0.5 -65 2000 200 150 MIN MAX 3.9 3.9 VDD_3.3+ 0.3V UNITS V V V V ° Notes 1,2 1,2 1,2,3 1 1,2 1,2 1,2 C V V Notes: 1 2 3 Guaranteed by design and characterization, not 100% tested in production. O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Ambient Operating Temp 3.3V Supply Voltage 1.5V Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage Low Threshold InputLow Voltage SYMBOL TambientITEMP VDDxxx_3.3 VDDxxx_1.5 VIHSE3.3 VILSE3.3 IIN IINRES VOHSE VOLSE VIH_FS VIL_FS IDD_DEFAULT Operating Supply Current IDD_LCDEN IDD_IO IDD_PD3.3 Power Down Current Input Frequency Pin Inductance Input Capacitance Spread Spectrum Modulation Frequency IDD_PDIO Fi Lpin CIN COUT CINX fSSMOD Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation 30 1.5 CONDITIONS No Airflow 3.3V +/- 5% 1.5V - 5% to 3.3V + 5% Single-ended inputs Single-ended inputs VIN = VDD , VIN = G ND Inputs with pull or pull down resistors. (CR# pins) VIN = VDD , VIN = G ND Single-ended outputs, IOH = - 1mA Single-ended outputs, IOL = 1 mA 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, LCDPLL off 3.3V supply, LCDPLL enabled 1.5V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 1.5V IO supply, Power Down Mode VDD = 3.3 V 0.7 VSS - 0.3 MIN -40 3.135 1.425 2 VSS - 0.3 -5 -200 2.4 0.4 1.5 0.35 65 70 55 2 0.5 15 7 5 6 5 33 MAX 85 3.465 3.465 VDD + 0.3 0.8 5 200 UNITS °C V V V V uA uA V V V V mA mA mA mA mA MHz nH pF pF pF kHz Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 8 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet AC Electrical Characteristics - Input/Common Parameters PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL T STAB T DRSRC T DRPD T DRSRC T FALL T RISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after CR# assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS ms ns us ns ns ns Notes 1 1 1 1 1 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Rise/Fall Time Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[2:0] Skew SRC[2:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 250 MIN 0.5 0.5 MAX 6 6 125 1150 UNITS V/ns V/ns ps mV mV mV mV mV % ps ps ps ps ps NOTES 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS ppm ns ns V V mA mA V/ns V/ns % ps Notes 1,2 2 2 1 1 1 1 1 1 1 1 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 9 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Electrical Characteristics - SMBus Interface PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 3.3 0.4 UNITS V V mA ns ns kHz Notes 1 1 1 1 1 1 Notes on Electrical Characteristics: 1 2 3 4 5 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# O nly applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz O peration under these conditions is neither implied, nor guaranteed. 6 7 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Symbol 1 Clock LgAbsolute Period Definition Minimum Absolute Period 9.87400 9.91400 7.41425 5.91440 1us -SSC 0.1s -ppm error 0.1s 0ppm Period 0.1s + ppm error Long-Term Average 1us +SSC Short-term Average 1 Clock Lg+ Period Short-term Long-Term Average Average Minimum Absolute Period 9.99900 9.99900 7.49925 5.99940 Minimum Absolute Period 9.99900 9.99900 7.49925 5.99940 Nominal 10.00000 10.00000 7.50000 6.00000 Maximum 10.00100 10.00100 7.50075 6.00060 Maximum 10.05130 10.05130 7.53845 6.03076 Maximum 10.17630 10.13630 7.62345 6.11576 Units ns ns ns ns Notes 1,2 1,2 1,2 1,2 SRC 100 Signal Name CPU 100 CPU 133 CPU 166 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Symbol 1 Clock LgAbsolute Period Definition Minimum Absolute Period 9.87400 9.91400 7.41425 5.91440 1us -SSC 0.1s -ppm error 0.1s 0ppm Period 0.1s + ppm error Long-Term Average 1us +SSC Short-term Average 1 Clock Lg+ Period Short-term Long-Term Average Average Minimum Absolute Period Minimum Absolute Period 9.99900 9.99900 7.49925 5.99940 Nominal 10.00000 10.00000 7.50000 6.00000 Maximum 10.00100 10.00100 7.50075 6.00060 10.41770 Maximum Maximum 10.17630 10.13630 7.62345 6.11576 10.66770 Units ns ns ns ns ns Notes 1,2 1,2 1,2 1,2 1,2 Signal Name SRC 100 CPU 100 CPU 133 CPU 166 10.16560 10.41560 10.41670 DOT 96 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 10 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Table 1: CPU Frequency Select Table CPU SRC DOT 1 1 FSLC FSLB MHz MHz MHz 0 0 133.33 0 1 166.67 100.00 96.00 1 0 100.00 1 1 66.67 LCD MHz REF MHz 100.00 14.318 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Table 2: LCD Spread Select Table (Pin 20/21) B1b5 0 0 0 0 1 1 1 1 B1b4 0 0 1 1 0 0 1 1 B1b3 0 1 0 1 0 1 0 1 Spread Comment % -0.5% LCD100 -1% LCD100 -2% LCD100 -2.5% LCD100 +/- 0.25 % LCD100 +/-0.5% LCD100 +/-1% LCD100 +/-1.25% LCD100 Table 3: CPU N-step P rogramming CPU (MHz) 133.33 166.67 100.00 200.00 P 3 3 4 2 Default N (hex ) 64 7D 64 64 Fcpu = 4MHz x N/P = 4MHz x N/P = 4MHz x N/P = 4MHz x N/P CPU Power Management Table SMBus Register PD CPU_STOP# CPU CPU# OE 0 Enable Running Running 1 X Enable Low/20K Low 1 0 Enable High Low 0 0 X Low/20K Low Disable SRC, LCD, DOT Power Management Table PD 0 1 0 0 CR_x# 0 X 1 X SMBus Register OE Enable X Enable Disable SRC SRC# DOT/LCD DOT#/LCD# Running Low/20K Running Low/20K Running Low Running Low Running Running Low/20K Low Low/20K Low Low/20K Low REF Power Management Table PD 0 1 0 SMBus Register OE Enable X Disable REF Running Low Low 1617—08/19/09 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 11 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet General SMBus serial interface information for the ICS9EMS9633 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(h) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit S lave Address D2(h) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 12 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Byte Bit(s) 7 6 5 4 3 2 1 0 0 PLL & Divider Enable Register Pin # Name Description This bit controls whether the PLL driving the CPU PLL1 Enable and SRC clocks is enabled or not. This bit controls whether the PLL driving the DOT PLL2 Enable and clock is enabled or not. This bit controls whether the PLL driving the LCD PLL3 Enable clock is enabled or not. Reserved This bit controls whether the CPU output divider is enabled or not. CPU Divider Enable NOTE: This bit should be automatically set to ‘0’ if bit 7 is set to ‘0’. This bit controls whether the SRC output divider is SRC Output Divider enabled or not. Enable NOTE: This bit should be automatically set to ‘0’ if bit 7 is set to ‘0’. This bit controls whether the LCD output divider is LCD Output Divider enabled or not. Enable NOTE: This bit should be automatically set to ‘0’ if bit 5 is set to ‘0’. This bit controls whether the DOT output divider is DOT Output Divider enabled or not. Enable NOTE: This bit should be automatically set to ‘0’ if bit 6 is set to ‘0’. 1 PLL SS Enable/Control Register Pin # Name Description This bit controls whether PLL1 has spread enabled or not. Spread spectrum for PLL1 is set at -0.5% PLL1 SS Enable down-spread. Note that PLL1 drives the CPU and SRC clocks. PLL3 SS Enable This bit controls whether PLL3 has spread enabled or not. Note that PLL3 drives the SSC clock, and that the spread spectrum amount is set in bits 3-5. These 3 bits select the frequency of PLL3 and the SSC clock when Byte 1 Bit 6 (PLL3 Spread Spectrum Enable) is set. Reserved Reserved Reserved Type RW RW RW 0 0 = Disabled 0 = Disabled 0 = Disabled 1 1 = Enabled 1 = Enabled 1 = Enabled Default 1 1 1 0 RW 0 = Disabled 1 = Enabled 1 RW 0 = Disabled 1 = Enabled 1 RW 0 = Disabled 1 = Enabled 1 RW 0 = Disabled 1 = Enabled 1 Byte Bit(s) 7 Type RW 0 0 = Disabled 1 1 = Enabled Default 1 6 5 4 3 2 1 0 RW 0 = Disabled 1 = Enabled 1 0 0 0 0 0 0 PLL3 FS Select RW See Table 2: LCD Spread Select Table IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 13 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) 7 6 5 4 2 Output Enable Register Pin # Name Description This bit controls whether the CPU[0] output buffer CPU0 Enable is enabled or not. This bit controls whether the CPU[1] output buffer CPU1 Enable is enabled or not. This bit controls whether the CPU[2] output buffer CPU2 Enable is enabled or not. This bit controls whether the SRC[0] output buffer SRC0 Enable is enabled or not. This bit controls whether the SRC[1] output buffer SRC1 Enable is enabled or not. This bit controls whether the SRC[2] output buffer SRC2 Enable is enabled or not. This bit controls whether the DOT output buffer is DOT Enable enabled or not. This bit controls whether the LCD output buffer is LCD100 Enable enabled or not. 3 Output Control Register Pin # Name Type RW RW RW RW RW RW RW RW 0 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 0 = Disabled 1 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Default 1 1 1 1 1 1 1 1 Description Reserved Reserved Type 0 1 Default 0 0 1 REF Enable This bit controls whether the REF output buffer is enabled or not. RW 0 = Disabled 1 = Enabled REF Slew 3 These bits control the edge rate of the REF clock. RW 00 = Slow Edge Rate 01 = Medium Edge Rate 10 = Fast Edge Rate 11 = Reserved 10 2 1 0 This bit controls whether the CPU[0] output buffer is free-running or stoppable. If it is set to stoppable CPU0 Stop Enable the CPU[0] output buffer will be disabled with the assertion of CPU_STP#. This bit controls whether the CPU[1] output buffer is free-running or stoppable. If it is set to stoppable CPU1 Stop Enable the CPU[1] output buffer will be disabled with the assertion of CPU_STP#. This bit controls whether the CPU[2] output buffer is free-running or stoppable. If it is set to stoppable CPU2 Stop Enable the CPU[2] output buffer will be disabled with the assertion of CPU_STP#. RW Free Running Stoppable 0 RW Free Running Stoppable 0 RW Free Running Stoppable 0 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 14 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 CPU PLL N Register Pin # Name CPU N Div8 CPU PLL/N Register 5 Pin # Name CPU N Div7 CPU N Div6 CPU N Div5 CPU N Div4 CPU N Div3 CPU N Div2 CPU N Div1 CPU N Div0 6 Pin # Reserved Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved N Divider Prog bit 8 Type 0 1 RW Default 1 1 1 1 1 1 1 0 Control Function See Table 3: CPU N-step Programming Type RW RW RW RW RW RW RW RW 0 1 Default depends on latched input frequency. Default for CPU = 166 is 7Dh. Default for all other frequencies is 64h. Default X X X X X X X X Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 1 1 1 1 0 0 1 1 7 Pin # Reserved Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 15 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) 7 6 5 4 3 2 1 0 Byte Bit(s) 7 6 5 4 3 2 1 0 8 Pin # Reserved Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 9 LCD100 PLL N Register Pin # Name Control Function LCD100 N Div7 LCD100 N Div6 LCD100 N Div5 N Divider Programming Byte9 bit(7:0) and Byte8 LCD100 N Div4 bit7 LCD100 N Div3 LCD100 N Div2 LCD100 N Div1 LCD100 N Div0 10 Status Readback Register Pin # Name 37 FSB 9 FSC 24 CR0# Readbk 28 CR1# Readbk 36 CR2# Readbk Type R R R R R R R R 0 1 See N-step programming formula Default X X X X X X X X Description Frequency Select B Frequency Select C Real time CR0# State Indicator Real time CR1# State Indicator Real time CR2# State Indicator Reserved Reserved Reserved Type R R R R R 0 1 See Table 1: CPU Frequency Select Table CR0# is Low CR0# is High CR1# is Low CR1# is High CR2# is Low CR2# is High Default Latch Latch X X X 0 0 0 11 Revision ID/Vendor ID Register Pin # Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 12 Device ID Register Pin # Name DEV_ID3 DEV_ID2 DEV_ID1 DEV_ID0 Description Revision ID (0 for A rev) Vendor ID Type R R R R R R R R 0 1 Vendor specific Default X X X X 0 0 0 1 Description Device ID MSB Device ID 2 Device ID 1 Device ID LSB Reserved Reserved Reserved Reserved Type R R R R 0 1 Default 0 0 1 1 0 0 0 0 1617—08/19/09 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 16 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 13 Pin # Reserved Register Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 14 Pin # Reserved Register Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 15 Byte Count Register Pin # Name BC5 BC4 BC3 BC2 BC1 BC0 Control Function Reserved Reserved Byte Count 5 Byte Count 4 Byte Count 3 Byte Count 2 Byte Count 1 Byte Count LSB Type 0 1 RW RW RW RW RW RW Specifies Number of bytes to be read back during an SMBus read. Default is 0xF. Default 0 0 0 0 1 1 1 1 Bytes 16:40 are reserved Byte Bit(s) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 41 N Program Enable Register Pin # Name CPU N Enable LCD N Enable Control Function Reserved Reserved Reserved Reserved Reserved Reserved Enables CPU N programming Enables LCD N programming Type 0 1 RW RW Disabled Disabled Enabled Enabled Default 0 0 0 0 0 0 0 0 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 17 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Test Clarification Table Comments HW TEST_SEL HW PIN TEST_MODE OUTPUT HW PIN low Vth input TEST_MODE is a real time input >0.7V >0.7V X 0.7V NORMAL HI-Z REF/N IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 18 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet MLF Top Mark Information (9EMS9633KILF) 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS EMS9633IL YYWW CofO ###### 36 35 34 33 32 31 30 29 28 27 26 25 Line 1. Company name Line 2. Part Number Line 3. YYWW = Date Code Line 3. Country of Origin Line 4. ####### = Lot Number IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 19 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet SYMBOL A A1 b c D E E1 e h L N a VARIATIONS N 48 300 mil SSOP In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D mm. MIN 15.75 MAX 16.00 MIN .620 D (inch) MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 20 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Seating Plane Index Area N Anvil Singulation A1 A3 L (Ref.) (N D -1)x e (Ref.) ND & N Even N 1 (Typ.) e 2 If N & N D are Even (N -1)x e 2 E2 E2 2 (Ref.) OR Top View Sawn Singulation b A (Re f.) e D2 2 D2 D ND & N Odd C Thermal Base Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.40 BASIC DIMENSIONS SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 48L TOLERANCE 48 12 12 6.00 x 6.00 3.95 / 4.25 3.95 / 4.25 0.30 / 0.50 Ordering Information Part/Order Number 9EMS9633BKILF 9EMS9633BKILFT 9EMS9633BFILF 9EMS9633BFILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 48-pin MLF 48-pin MLF 48-pin SSOP 48-pin SSOP Temperature -40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C Parts that are ordered w ith a “LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant. Due to package size constraints, actual top-side m arking m ay differ from the full orderable part num ber. IDTTM/ICSTM Ultra Mobile PC Clock for Embedded Applications 1617—08/19/09 21 ICS9EMS9633 ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS Datasheet Revision History Rev. 0.1 A Issue Date Description 07/31/09 Initial Release 08/19/09 Released to final Page # - Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 22