9FG104DFILFT

DATASHEET Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Description The ICS9FG104D is a Frequency Timing Generator that provides 4 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-tooutput skew of less than 35 ps. The ICS9FG104D also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control. ICS9FG104D Features/Benefits • • • • • • Generates common frequencies from 14.318 MHz or 25 MHz Crystal or reference input 4 - 0.7V current-mode differential output pairs Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread Unused inputs may be disabled in either driven or Hi-Z state for power management. Key Specifications • • • • Output cycle-to-cycle jitter < 50 ps Output to output skew < 35 ps +/-300 ppm frequency accuracy on output clocks +/-50 ppm at any frequency w/spread off Functional Block Diagram XIN/CLKIN OSC X2 2 R EF OU T PROGRAMMABLE SPREAD PLL STOP LOGIC 4 DIF(3:0) SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC IREF IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 1 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Pin Configuration XIN/CLKIN X2 VDD GND REFOUT vFS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDA GNDA IREF vFS0 vFS1 DIF_0 DIF_0# VDD GND DIF_1 DIF_1# ^SEL14M_25M# vSPREAD DIF_STOP# Functionality Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.00 0 1 1 0 333.00 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.00 1 1 1 0 333.00 1 1 1 1 400.00 ^ Pin has internal 120K pull up v Pin has internal 120K pull down 28-pin SSOP/TSSOP Power Groups Pin Number VDD GND 3 4 9,21 10,20 28 27 Description REFOUT, Digital Inputs DIF Outputs IREF, Analog VDD, GND for PLL Core IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG104D 1541C —12/16/10 2 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN NAME XIN/CLKIN X2 VDD GND REFOUT vFS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK DIF_STOP# vSPREAD ^SEL14M_25M# DIF_1# DIF_1 GND VDD DIF_0# DIF_0 vFS1 vFS0 PIN TYPE IN OUT PWR PWR OUT IN OUT OUT PWR PWR OUT OUT I/O IN IN IN IN OUT OUT PWR PWR OUT OUT IN IN DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Active low input to stop differential output clocks. Asynchronous, active high input to enable spread spectrum functionality. This pin has a 120Kohm pull down resistor. Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm pull up resistor. 1 = 14.31818 MHz, 0 = 25 MHz 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Ground pin for the PLL core. 3.3V power for the PLL core. 26 27 28 IREF GNDA VDDA OUT PWR PWR IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 3 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Absolute Max Symbol Parameter VDDxx 3.3V Supply Voltage Ts Storage Temperature Tambient Ambient Operating Temp•(Commerical Grade) Tambient Ambient Operating Temp•(Industrial Grade) Tcase Case Temperature ESD prot Input ESD protection•human body model Min -65 0 -40 2000 Max 4.6 150 +70 +85 115 Units V ° C °C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = TA M B IENT ; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL I IH IIL1 Input Low Current IIL2 CONDITIONS MIN TYP MAX VDD + 0.3 UNITS NOTES V V uA uA uA 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1,2 1,2 1,3,4 1,3,4 1 1 3.3 V +/-5% 2 VSS - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-5 up resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz All outputs stopped driven All outputs stopped Hi-Z SEL14M_25M# = 0 SEL14M_25M# = 1 Logic Inputs Output pin capacitance From VDD Power-Up to 1st clock (Commercial) From VDD Power-Up to 1st clock (Industrial) SEL14M_25M# = 0 SEL14M_25M# = 1 DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD -200 125 110 106 48 22.5 25.00 12.886 14.31818 1.5 0.8 5 150 125 120 60 27.5 15.75 7 5 6 1.8 1.8 mA mA mA mA MHz MHz nH pF pF ms ms kHz kHz I DD3.3OP Operating Supply Current I DD3.3STOP Input Frequency 3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 TSTABind Modulation Frequency Modulation Frequency DIF output enable Input Rise and Fall times 1 2 Fi Lpin CIN COUT TSTABcom f MOD f MOD t DIFOE tR/t F 32.541 32.467 15 5 ns ns Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 I nput frequency should be measured at the REF pin and tuned to 0 PPM to meet ppm frequency accuracy on PLL outputs. These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz. IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 4 4 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = TA M B IENT ; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, I REF = 475Ω PARAMETER Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo 1 CONDITIONS V O = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Crossing variation over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, V OH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 TYP MAX UNITS Ω NOTES 1 1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm 850 mV 150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, output to output Jitter, Cycle to cycle 1 2 tr tf d-t r d-t f dt3 tsk3 t jcyc-cyc Measured Differentially V T = 50% Measured Differentially -300 300 2.49988 2.5000 2.5001 2.4993 2.5133 2.99985 3.0000 3.0002 2.9991 3.016 3.74981 3.7500 3.7502 3.7489 3.77 4.9998 5.0000 5.0003 4.9985 5.0266 5.9997 6.0000 6.0003 5.9982 6.0320 7.4996 7.5000 7.5004 7.4978 5.4000 9.9995 10.0000 10.0005 9.9970 10.0533 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 700 175 700 125 125 45 55 35 50 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accurac y and Clock Period s pecifications are guaranteed assuming that REFOUT is tuned to 0 3 Figures are for down spread. 4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 +/- 50 ppm at any frequenc y with s pread off IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 5 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Electrical Characteristics - REF-14.318/25 MHz TA = TA M B IENT ; V DD = 3.3 V +/-5%;RS=33Ω CL = 5 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Jitter 1 2 SYMBOL ppm Tperiod VOH VOL I OH I OL tr1 tf1 dt1 tjc y c-c y cCOM tjcyc-cycIND CONDITIONS see Tperiod min-max values 14.318MHz output nominal 25.000MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V (commerical) VT = 1.5 V (commerical) MIN TYP 0 69.8413 40.0000 MAX UNITS Notes ppm ns ns V V mA mA ns ns % ps ps 1,2 1,2 1,2 1 1 1 1 1 1,2 1,2 1 1 2.4 0.4 -29 29 1 1 45 1.6 1.6 52.5 150 400 -23 27 2.5 2.5 55 200 600 Guaranteed by design and characterization, not 100% tested in production. Trim capacitors must be used to tune the REF to the exact Crystal Frequenc y . Electrical Characteristics - Differential Phase Jitter Parameters PARAMETER Symbol Conditions Min Typ Max Units Notes tjphasePLL tjphaseLo tjphaseHigh Jitter, Phase tjphQPI tjphFBD3.2G tjphFBD4.8G 1 2 PCIe Gen 1 PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) QPI 133MHz 4.8G/6.4Gb,12UI FBD specs (11 to 33MHz) FBD specs (11 to 33MHz) 40 1.2 2.2 0.25/0.2 2.2 1.8 86 3 3.1 0.5 3 2.5 ps (p-p) ps (RMS) ps (RMS) ps (RMS) ps (RMS) ps (RMS) 1,2 1,2 1,2 1,3 1 1 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for compelte s pecs 3 First number is 4.8G link s peed, second number is 6.4G link s peed. From Intel Clock Jit tool 1.5.1 IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 6 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA General SMBus serial interface information for the ICS9FG104D How to Write: Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address DC(h) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address DC(h) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address DD(h) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK Byte N + X - 1 N P IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Not acknowledge stoP bit 1541C —12/16/10 7 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin # 17 6 24 25 16 Name FS31 FS21 FS11 FS01 Spread Enable1 Control Function Type RW RW RW RW RW 0 1 Default Pin 17 Pin 6 Pin 24 Pin 25 Pin 16 See Frequency Selection Table, Page 1 Off On Bit 2 - Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) RW Hardware Select Software Select 0 Bit 1 Bit 0 DIF_STOP# drive mode SPREAD TYPE RW RW Driven Down Hi-Z Center 0 0 Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 EN DIF_0 EN DIF_3 EN DIF_2 EN Name Control Function Reserved Output Enable Output Enable Reserved Reserved Output Enable Output Enable Reserved RW RW Disable Disable Enable Enable RW RW Disable Disable Enable Enable Type 0 1 Default 1 1 1 1 1 1 1 1 SMBus Table: Output Stop Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # DIF_1 STOP EN DIF_0 STOP EN DIF_3 STOP EN DIF_2 STOP EN Name Control Function Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved Reserved Free Run/ Stop Enable Free Run/ Stop Enable Reserved RW RW Free-run Free-run Stop-able Stop-able RW RW Free-run Free-run Stop-able Stop-able Type 0 1 Default 0 0 0 0 0 0 0 0 IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 8 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Frequency Select Readback Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 27 6 44 45 16 Name SEL14M_25M# (FS3) FS21 FS11 FS01 SPREAD1 1 Control Function State of pin 17 State of pin 6 State of pin 24 State of pin 25 State of pin 26 Reserved Reserved Reserved Type R R R R R 0 1 Default Pin 17 See Frequency Selection Table, Page 1 Pin 6 Pin 24 Pin 25 Off On Pin 16 0 0 0 Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 VENDOR ID REVISION ID Control Function Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 SMBus Table: DEVICE ID Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 Device ID = 08 hex Control Function Type R R R R R R R R 0 1 Default 0 0 0 0 1 0 0 0 SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Control Function Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 1 1 1 1541C —12/16/10 IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 9 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Reserved Register Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 SMBus Table: Reserved Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 SMBus Table: M/N Programming Enable Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 5 REFOUT_En Name M/N_Enable Control Function M/N Prog. Enable Reserved REFOUT Enable Reserved Reserved Reserved Reserved Reserved RW Disable Enable Type RW 0 Disable 1 Enable Default 0 1 1 0 0 0 0 0 SMBus Table: PLL Frequency Control Register Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div8 PLL N Div9 PLL M Div5 PLL M Div4 PLL M Div3 PLL M Div2 PLL M Div1 PLL M Div0 M Divider Programming bit (5:0) Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 Default X X X X X X X X IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 10 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: PLL Frequency Control Register Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL N Div7 PLL N Div6 PLL N Div5 PLL N Div4 PLL N Div3 PLL N Div2 PLL N Div1 PLL N Div0 N Divider Programming Byte11 bit(7:0) and Byte10 bit(7:6) Control Function Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 Default X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PLL SSP7 PLL SSP6 PLL SSP5 PLL SSP4 PLL SSP3 PLL SSP2 PLL SSP1 PLL SSP0 Spread Spectrum Programming bit(7:0) Control Function Type RW RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL 0 1 Default X X X X X X X X SMBus Table: PLL Spread Spectrum Control Register Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PLL SSP14 PLL SSP13 PLL SSP12 PLL SSP11 PLL SSP10 PLL SSP9 PLL SSP8 Spread Spectrum Programming bit(14:8) Name Control Function Reserved RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL Type 0 1 Default 0 X X X X X X X IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 11 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA DIF_STOP# - Assertion (transition from '1' to '0') Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated. DIF_STOP# DIF DIF# DIF_STOP# - De-assertion (transition from '0' to '1') With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV. DIF_Stop# DIF DIF# DIF Internal Tdrive_DIF_Stop, 15nS >200mV IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 12 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 1 1 inch inch 2 2 Figure 1: Down Device Routing L1 Rs L2 L4 L4' L2' Rs Rt Rt PCI Express Down Device REF_CLK Input L1' HCSL Output Buffer L3' L3 Figure 2: PCI Express Connector Routing L1 Rs L2 L4 L4' L2' Rs Rt Rt PCI Express Add-in Board REF_CLK Input L1' HCSL Output Buffer L3' L3 IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 13 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 R1a L2 R3 L4 L4' R4 L1' HCSL Output Buffer R1b L2' R2a R2b Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a Cc L4 L4' Cc R6a R5b R6b PCIe Device REF_CLK Input IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 14 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 28-Pin SSOP Package Drawing and Dimensions c N 209 mil SSOP SYMBOL L E1 INDEX AREA E 12 h x 45° D α A A1 A2 b c D E E1 e L N α VARIATIONS N In Millimeters COMMON DIMENSIONS MIN MAX -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX -.079 .002 -.065 .073 .009 .015 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0° 8° D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 A A1 28 Reference Doc.: JEDEC Publication 95, MO-150 -Ce b SEATING PLANE .10 (.004) C 10-0033 IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 15 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 28-Pin TSSOP Package Drawing and Dimensions 4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) SYMBOL L N c (25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 E1 INDEX AREA E 12 α D A A1 A2 b c D E E1 e L N α aaa VARIATIONS In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 A2 A1 A N 28 D mm. MIN 9.60 MAX 9.80 MIN .378 D (inch) MAX .386 - Ce b SEA TING PLANE Reference Doc.: JEDEC Publication 95, MO-153 10-0035 aaa C Ordering Information Part/Order Number 9FG104DFLF 9FG104DFLFT 9FG104DFILF 9FG104DFILFT 9FG104DGLF 9FG104DGLFT 9FG104DGILF 9FG104DGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C Parts that are ordered with a “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1541C —12/16/10 16 ICS9FG104D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Revision History Rev. 0.1 Issue Date Description 1. Created Rev D data sheet from original non revision specific version. 12/18/2008 2. Updated phase noise characterisitcs for Rev D. 3. Corrected footnote reference to ppm on CPU Electrical Characteristics 1. Updated PPM footnotes 4/1/2009 2. Modified input frequency ranges for each setting of the SEL14M_25M# input. 1. Corrected/Added Tstab for Industrial Temperature Range 2. Corrected/Added REF cyc-cyc jitter for Industrial Temperature Range 5/14/2009 3. Move to final 1. Corrected PIN TYPE on pin 24. Changed pull up pull down designators to 11/8/2010 ^ and v respectively 12/16/2010 Updated VDD Supply Voltage specs Page # 0.2 Various A B C 4, 6 2, 3 4 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 17