9FG108DFLF

DATASHEET Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Description ICS9FG108D is a Frequency Timing Generator that provides 8 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output frequencies from either a 14.31818 MHz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 65 ps. ICS9FG108D also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control. ICS9FG108D Features/Benefits • • • • • • Generates common frequencies from 14.318 MHz or 25 MHz Crystal or reference input 8 - 0.7V current-mode differential output pairs Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 down spread and +/-0.25% center spread Unused inputs may be disabled in either driven or Hi-Z state for power management. Key Specifications • • • • Output cycle-to-cycle jitter < 50 ps Output to output skew < 65 ps +/-300 ppm frequency accuracy on output clocks +/-50 ppm at any frequency with spread off Functional Block Diagram XIN/CLKIN OSC X2 OE(7:0) R EFO U T PROGRAMMABLE SPREAD PLL STOP LOGIC 8 DIF(7:0) SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC IREF IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 1 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Pin Configuration XIN/CLKIN X2 VDD GND REFOUT vFS2 vOE_7 DIF_7 DIF_7# VDD DIF_6 DIF_6# ^OE_6 VDD GND ^OE_5 DIF_5 DIF_5# VDD DIF_4 DIF_4# vOE_4 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF vFS0 vFS1 vOE_0 DIF_0 DIF_0# VDD DIF_1 DIF_1# ^OE_1 VDD GND ^OE_2 DIF_2 DIF_2# VDD DIF_3 DIF_3# vOE_3 ^SEL14M_25M# vSPREAD DIF_STOP# Functionality Table Frequency Select Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.66 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.66 1 1 1 0 333.33 1 1 1 1 400.00 ^ indicates internal 120K pull up v indicates internal 120K pull down 48-pin SSOP & TSSOP Power Groups Pin Num ber VDD GND 3 4 10,14,19,31,36,40 15,35 N/A 47 48 47 Descri p tion REFOUT, Digital Inputs, SMBus DIF Outputs IREF Analog VDD & GND for PLL Core IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG108D 1542E 12/16/10 2 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Pin Description PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN N A ME XIN /C LKIN X2 VD D GN D R EFOU T vFS2 vOE_7 D IF_ 7 D IF_ 7# VD D D IF_ 6 D IF_ 6# ^OE_6 VD D GN D ^OE_5 D IF_ 5 D IF_ 5# VD D D IF_ 4 D IF_ 4# vOE_4 SD ATA SC LK PIN TYPE IN OU T PWR PWR OU T IN IN OU T OU T PWR OU T OU T IN PWR PWR IN OU T OU T PWR OU T OU T IN I/O IN D ESC R IPTION C rystal inpu t or R e feren ce C lock in put C rystal outp ut, N om inally 14 .318 MH z Pow e r supp ly, nom inal 3.3 V Groun d pin. R e fere nce C lock o utput Freq uency se lect pin . This pin has a n internal 1 20k pu ll dow n resistor Active hig h inp ut for enab ling o utpu t 7. This p in ha s a 120 kohm pull do w n. 0 = tri-sta te ou tputs, 1 = ena ble o utpu ts 0 .7V differe ntial true clock o utpu t 0 .7V differe ntial C o mplem enta ry clock ou tput Pow e r supp ly, nom inal 3.3 V 0 .7V differe ntial true clock o utpu t 0 .7V differe ntial C o mplem enta ry clock ou tput Active hig h inp ut for enab ling o utpu t 6. This p in ha s a n inte rna l 120ko hm p ull up . 0 = tri-sta te ou tputs, 1 = ena ble o utpu ts Pow e r supp ly, nom inal 3.3 V Groun d pin. Active hig h inp ut for enab ling o utpu t 5. This p in ha s a n inte rna l 120ko hm p ull up . 0 = tri-sta te ou tputs, 1 = ena ble o utpu ts 0 .7V differe ntial true clock o utpu t 0 .7V differe ntial C o mplem enta ry clock ou tput Pow e r supp ly, nom inal 3.3 V 0 .7V differe ntial true clock o utpu t 0 .7V differe ntial C o mplem enta ry clock ou tput Active hig h inp ut for enab ling o utpu t 4. This p in as an internal 1 20koh m pu ll dow n. 0 = tri-sta te ou tputs, 1 = ena ble o utpu ts D a ta pin fo r SMBus circuitry, 3.3V tolerant. C lo ck pin of SMBus circu itry, 5V tole rant. N ote: ^ i ndicates internal 120K pull up v indic ates internal 120K pull down IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 3 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Pin Description (continued) PIN # 25 26 27 PIN NAME DIF_STOP# vSPREAD ^SEL14M_25M# PIN TYPE IN IN IN DESCRIPTION Active low input to stop differential output clocks. Asynchronous, active high input to enable spread spectrum functionality. This pin has a 120Kohm pull down resistor. Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm pull up resistor. 1 = 14.31818 MHz, 0 = 25 MHz Active high input for enabling output 3. This pin has an internal 120kohm pull down resistor. 0 = tri-state outputs, 1= enable outputs 0.7V differential Complementary clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active high input for enabling output 2. This pin has in internal 120kohm pull up resistor. 0 = tri-state outputs, 1= enable outputs Ground pin. Power supply, nominal 3.3V Active high input for enabling output 1. This pin has an internal 120kohm pull up resistor. 0 = tri-state outputs, 1= enable outputs 0.7V differential Complementary clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active high input for enabling output 0. This pin has an internal 120kohm pull down resistor. 0 = tri-state outputs, 1= enable outputs 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. 3.3V Frequency select latched input pin with internal 120kohm pull down resistor. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Note: vOE_3 DIF_3# DIF_3 VDD DIF_2# DIF_2 ^OE_2 GND VDD ^OE_1 DIF_1# DIF_1 VDD DIF_0# DIF_0 vOE_0 vFS1 vFS0 IREF GNDA VDDA IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN IN IN OUT PWR PWR ^ indicates internal 120K pull up v indicates internal 120K pull down IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 4 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Absolute Max Symbol VDD_A VDD Ts Tambient Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp•(Commerical Grade) Ambient Operating Temp•(Industrial Grade) Case Temperature Input ESD protection•human body model Min Max 4.6 4.6 150 +70 +85 115 Units V V ° C °C °C °C V -65 0 -40 2000 Electrical Characteristics - REF-14.318/25 MHz TA = Tambient, Supply Voltage VDD = 3.3 V +/-5%; RS=33Ω, CL = 5pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Clock period Tperiod 14.318MHz output nominal 25.000MHz output nominal Clock period Tperiod IOH = -1 mA Output High Voltage VOH IOL = 1 mA Output Low Voltage VOL VOH @MIN = 1.0 V, Output High Current IOH VOH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current IOL VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V trf1COM Commercial Temp Rise/Fall Time VOL = 0.4 V, VOH = 2.4 V trf1IND Industrial Temp VT = 1.5 V Duty Cycle dt1 Jitter Jitter 1 2 MIN TYP 0 69.8413 40.0000 SPEC MAX 2.4 0.4 -29 29 0.5 0.5 45 150 250 0.8 0.8 -23 27 2 2 55 200 400 UNITS Notes ppm 1 ns 1,2 ns 1,2 V 1 V 1 mA mA ns ns % ps ps 1 1 1 1 1 1 1 tjcyc-cycCOM tjcyc-cycIND VT = 1.5 V (commerical) VT = 1.5 V (industrial) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818 or 25.00 MHz Electrical Characteristics - Differential Phase Jitter Parameters TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5% PARAMETER Symbol Conditions PCIe Gen 1 tjphasePLL PCIe Gen 2 t jphaseLo 10kHz < f < 1.5MHz PCIe Gen 2 t jphaseHigh 1.5MHz < f < Nyquist (50MHz) Jitter, Phase tjphQPI QPI 133MHz 4.8G/6.4Gb,12UI tjphFBD3.2G tjphFBD4.8G 1 2 Min Typ 30 1.2 2.2 0.26/ 0.18 1.8 1.4 SPEC Max 86 3 3.1 0.5 3 2.5 FBD specs (11 to 33MHz) FBD specs (11 to 33MHz) Units Notes ps (p-p) 1,2 ps 1,2 (RMS) ps 1,2 (RMS) ps 1,3 (RMS) ps 1 (RMS) ps 1 (RMS) Guaranteed by design and characterization, not 100% tested in production. See htt p://www.pcisig.com for compelte s pecs 3 First number is 4.8G link s peed, s econd number is 6.4G link s peed. From Intel Clock Jit tool 1.5.1 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 5 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Electrical Characteristics - Input/Supply/Common Output Parameters TA = Tambient, Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL I IH IIL1 Input Low Current IIL2 IDDVDD IDDVDDA IDDVDD IDDVDDA IDDVDDPD IDDVDDAPD IDDVDDPD IDDVDDAPD IDDVDD IDDVDD IDDVDDA IDDVDDA IDDVDDPD IDDVDDAPD Fi Lpin CIN COUT TSTABcom Clk Stabilization 1,2 SPEC MIN 2 VSS - 0.3 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% V IN = VDD V IN = 0 V ; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors CL=Full load; fout = 400 MHz CL=Full load; fout = 100 MHz All DIF pairs stopped in driven mode All DIF pairs stopped in Hi-Z mode CL=Full load; fout = 400 MHz CL=Full load; fout = 100 MHz All DIF pairs stopped in driven mode All DIF pairs stopped in Hi-Z mode SEL14M_25M# = 0 SEL14M_25M# = 1 Logic Inputs Output pin capacitance From V DD P ower-Up to 1st clock From V DD P ower-Up to 1st clock SEL14M_25M# = 0 SEL14M_25M# = 1 Down Spread Selected Center Spread Selected DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD TYP MAX VDD + 0.3 UNITS NOTES V V uA uA uA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1,2 1,2 1,3,4 1,3,4 1,3,4 1,3,4 1 1 -5 -5 -200 186 22 156 22 148 22 30 22 205 24 172 24 163 24 33 24 22.50 25.00 12.89 14.31818 1.5 0.8 5 Operating Supply Current (TA = Commercial) DIF_STOP# Current (TA = Commercial) 215 25 179 25 170 25 35 25 236 28 198 28 187 28 38 28 28.00 15.75 7 5 6 1.8 3 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz nH pF pF ms ms kHz kHz % % ns ns Operating Supply Current (TA = I ndustrial) DIF_STOP# Current (TA = I ndustrial) Input Frequency 3 Pin Inductance Input/Output Capacitance1 1 TSTABind Spread Modulation Frequency Spread Modulation % Spread Modulation % DIF output enable Input Rise and Fall times 1 2 f MOD f MOD%DWN f MOD%CTR tDIFOE t R/t F 32.541 32.467 -0.5 +/-0.25 15 5 Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 I nput frequency should be measured at the REF pin and tuned to 0 PPM to meet ppm frequency accuracy on PLL outputs. 4 These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale. For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 = 108MHz. IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 6 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = Tambient, Supply Voltage VDD = 3.3 V +/-5%, CL =2pF, RS=33.2Ω , RP=49.9Ω, I REF = 475Ω PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Crossing variation over all edges 14.3M input, SS OFF 14.3M input, SS ON 25M input SS OFF 25M input, SS ON 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V -300 -300 -50 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 MIN 3000 660 -150 -300 250 850 mV 150 1150 550 140 300 300 50 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ppm ppm ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps ps 1 1 1 1 1 1,2,5 1,2,5 1,2,5 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 TYP SPEC MAX UNITS Ω NOTES 1 1 Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, output to output Jitter, Cycle to cycle 1 2 tr tf d-t r d-t f dt3 t sk3COM t sk3IND t jcyc-cyc Measured Differentially TA = Commercial, VT=50% TA = Industrial, VT=50% Measurement from differential wavefrom 45 700 700 125 125 55 50 65 50 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz Figures are for down spread. This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 + /- 50 ppm at any frequenc y with s pread off 1542E 12/16/10 3 4 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 7 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA General SMBus serial interface information for the ICS9FG108D How to Write: Controller (host) sends a start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T S lave Address DC(h) WRite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address DC(h) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address DD(h) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit Byte N + X - 1 N P IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Not acknowledge stoP bit 1542E 12/16/10 8 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Pin # Name Control Function Type RW 27 Bit 7 FS31 RW 5 Bit 6 FS21 44 RW Bit 5 FS11 1 7 RW Bit 4 FS0 1 26 RW Bit 3 Spread Enable Bit 2 Bit 1 Bit 0 Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) DIF_STOP# drive mode Spread Type RW RW RW 0 1 See Frequency Selection Table, Page 1 Off On Default Pin 27 Pin 5 Pin 44 Pin 7 Pin 26 0 0 0 Hardware Software Select Select Driven Down Hi-Z Center Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Byte 1 Pin # Name Control Function Type DIF_7 EN Output Enable RW Bit 7 DIF_6 EN Output Enable RW Bit 6 DIF_5 EN Output Enable RW Bit 5 DIF_4 EN Output Enable RW Bit 4 DIF_3 EN Output Enable RW Bit 3 DIF_2 EN Output Enable RW Bit 2 DIF_1 EN Output Enable RW Bit 1 DIF_0 EN Output Enable RW Bit 0 Note: Byte 1 sets outputs active or inactive, not the conditons set by the OE SMBus Table: Output Stop Mode Register Pin # Name Control Function Byte 2 DIF_7 STOP EN Free Run/ Stop Enable Bit 7 DIF_6 STOP EN Free Run/ Stop Enable Bit 6 DIF_5 STOP EN Free Run/ Stop Enable Bit 5 DIF_4 STOP EN Free Run/ Stop Enable Bit 4 DIF_3 STOP EN Free Run/ Stop Enable Bit 3 DIF_2 STOP EN Free Run/ Stop Enable Bit 2 DIF_1 STOP EN Free Run/ Stop Enable Bit 1 DIF_0 STOP EN Free Run/ Stop Enable Bit 0 0 Disable Disable Disable Disable Disable Disable Disable Disable inputs. 1 Enable Enable Enable Enable Enable Enable Enable Enable Default 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW 0 Free-run Free-run Free-run Free-run Free-run Free-run Free-run Free-run 1 Default Stop-able 0 Stop-able 0 Stop-able 0 Stop-able 0 Stop-able 0 Stop-able 0 Stop-able 0 Stop-able 0 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 9 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Frequency Select Readback Register Byte 3 Pin # Name Control Function SEL14M_25M#1 27 State of pin 27 Bit 7 (FS3) 6 State of pin 6 Bit 6 FS21 1 44 State of pin 44 Bit 5 FS1 45 State of pin 45 Bit 4 FS01 1 26 State of pin 26 Bit 3 SPREAD Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Type R R R R R R R R 0 1 Default Pin 27 Pin 6 Pin 44 Pin 45 Pin 26 X X X See Frequency Selection Table, Page 1 Off On Reserved Reserved Reserved Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name Control Function RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 5 Pin # Name DEVID7 Bit 7 DEVID6 Bit 6 DEVID5 Bit 5 DEVID4 Bit 4 DEVID3 Bit 3 DEVID2 Bit 2 DEVID1 Bit 1 DEVID0 Bit 0 Type R R R R R R R R 0 - 1 - Default X X X X 0 0 0 1 Control Function Device ID = 08 hex Type R R R R R R R R 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 1 0 0 0 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 10 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: Byte Count Register Byte 6 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBus Table: Reserved Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Type RW RW RW RW RW RW RW RW 0 - 1 - Default 0 0 0 0 0 1 1 1 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default X X X X X X X X Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default X X X X X X X X SMBus Table: M/N Programming Enable Byte 9 Pin # Name Control Function PLL M/N Programming M/N_EN Bit 7 Enable Select Polarity of OE OE_Polarity Bit 6 inputs Enables/Disables REF 5 REFOUT_En Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Type RW RW RW 0 Disable OE# Disable 1 Enable OE Enable Default 0 1 1 0 0 0 0 0 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 11 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA SMBus Table: PLL Frequency Control Register Pin # Name Control Function Byte 10 PLL N Div8 N Divider Prog bit 8 Bit 7 PLL N Div9 N Divider Prog bit 9 Bit 6 PLL M Div5 Bit 5 PLL M Div4 Bit 4 M Divider Programming PLL M Div3 Bit 3 bit (5:0) PLL M Div2 Bit 2 PLL M Div1 Bit 1 PLL M Div0 Bit 0 SMBus Table: PLL Frequency Control Register Byte 11 Pin # Name Control Function PLL N Div7 Bit 7 PLL N Div6 Bit 6 PLL N Div5 Bit 5 N Divider Programming PLL N Div4 Bit 4 Byte11 bit(7:0) and PLL N Div3 Bit 3 Byte10 bit(7:6) PLL N Div2 Bit 2 PLL N Div1 Bit 1 PLL N Div0 Bit 0 SMBus Table: PLL Spread Spectrum Control Register Byte 12 Pin # Name Control Function PLL SSP7 Bit 7 PLL SSP6 Bit 6 PLL SSP5 Bit 5 Spread Spectrum PLL SSP4 Bit 4 Programming bit(7:0) PLL SSP3 Bit 3 PLL SSP2 Bit 2 PLL SSP1 Bit 1 PLL SSP0 Bit 0 SMBus Table: PLL Spread Spectrum Control Register Byte 13 Pin # Name Control Function Reserved Bit 7 PLL SSP14 Bit 6 PLL SSP13 Bit 5 PLL SSP12 Bit 4 Spread Spectrum PLL SSP11 Bit 3 Programming bit(14:8) PLL SSP10 Bit 2 PLL SSP9 Bit 1 PLL SSP8 Bit 0 Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv ( 5:0) +2] Default X X X X X X X X Type RW RW RW RW RW RW RW RW 0 1 The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = fXTAL x [NDiv(9:0)+8] / [MDiv ( 5:0) +2] Default X X X X X X X X Type RW RW RW RW RW RW RW RW Default X X These Spread X Spectrum bits in X Byte 13 and 14 will X program the spread X pecentage of PLL X X 0 1 Type RW RW RW RW RW RW RW Default 0 X These Spread X Spectrum bits in X Byte 13 and 14 will X program the spread X pecentage of PLL X X 0 1 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 12 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA DIF_STOP# - Assertion (transition from '1' to '0') Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIF outputs will be tri-stated. DIF_STOP# DIF DIF# DIF_STOP# - De-assertion (transition from '0' to '1') With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV. DIF_Stop# DIF DIF# DIF Internal Tdrive_DIF_Stop, 15nS >200mV IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 13 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 1 1 inch inch 2 2 Figure 1: Down Device Routing L1 Rs L2 L4 L4' L2' Rs Rt Rt PCI Express Down Device REF_CLK Input L1' HCSL Output Buffer L3' L3 Figure 2: PCI Express Connector Routing L1 Rs L2 L4 L4' L2' Rs Rt Rt PCI Express Add-in Board REF_CLK Input L1' HCSL Output Buffer L3' L3 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 14 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L1 R1a L2 R3 L4 L4' R4 L1' HCSL Output Buffer R1b L2' R2a R2b Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a Cc L4 L4' Cc R6a R5b R6b PCIe Device REF_CLK Input IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 15 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 48-pin SSOP Package Outline and Dimensions 48-Lead 300 mil SSOP N c SYMBOL L E1 INDEX AREA E 12 h x 45° D α A A1 A A1 b c D E E1 e h L N α VARIATIONS In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° -Ce b SEATING PLANE .10 (.004) C N 48 D mm. MIN 15.75 MAX 16.00 MIN .620 D (inch) MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 16 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 48-pin TSSOP Package Outline and Dimensions N c 48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) L (20 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 SYMBOL A A1 A2 b c D E E1 e L N α aaa VARIATIONS N 48 INDEX AREA E1 E 12 D a A2 A1 A In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 -Ce b SEATING PLANE D mm. MIN 12.40 MAX 12.60 MIN .488 D (inch) MAX .496 aaa C Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information Part / Order Number 9FG108DFLF 9FG108DFLFT 9FG108DFILF 9FG108DFILFT 9FG108DGLF 9FG108DGLFT 9FG108DGILF 9FG108DGILFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 48-pin SSOP 48-pin SSOP 48-pin SSOP 48-pin SSOP 48-pin TSSOP 48-pin TSSOP 48-pin TSSOP 48-pin TSSOP Temperature 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C 0 to +70°C 0 to +70°C -40 to +85°C -40 to +85°C Parts that are ordered w ith a “LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant. IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA 1542E 12/16/10 17 ICS9FG108D Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA Revision History Rev. 0.1 Issue Date Description 12/18/2008 New datasheet. 1. Updated phase jitter tables. 2, Updated input frequency ranges. There are now separate ranges for 14.318M input and 25M input. 5/7/2009 3. Merged I-temp and Commercial Temp Data sheets. 1. Corrected/Added Tstab for Industrial Temperature Range 2. Corrected/Added REF cyc-cyc jitter for Industrial Temperature Range 5/14/2009 3. Move to final. 5/20/2009 Updated REF - 14.318/25 MHz table. 1. Updated Electical Tables to clearly differentiate commercial and industrial parameter deltas. 2. Changed REF load to Rs = 33ohms, CL = 5pf, from CL = 30pf. Slew rate 11/20/2009 limits adjusted accordingly . 1. Changed pull up and pull down indicators from * and ** to ^ for pull up and v for pull down. 12/1/2009 2. Corrected Pin type on Pin 44 from I/O to IN. 12/16/2010 Updated VDD Supply v oltage specs Page # 0.2 Various A B 5,7 7 C D E 2-4 5 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 TM © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 18