9FG1901HKLFT

DATASHEET Frequency Gearing Clock for CPU, PCIe Gen1 & FBD Description The 9FG1901H follows the Intel DB1900G Differential Buffer Specification. This buffer provides 19 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups, DIF_(16:0) and DIF_(18:17) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H can provide outputs up to 400MHz. 9 FG1901H Features/Benefits • • • • • • • • Power up default is all outputs in 1:1 mode DIF_(16:0) can be “gear-shifted” from the input CPU Host Clock DIF_(18:17) can be “gear-shifted” from the input CPU Host Clock Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode VDDA controlled power down mode Key Specifications • • DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew across all outputs in 1:1 mode < 150ps Functional Block Diagram OE_17_18# SPREAD COMPATIBLE PLL GEAR SHIFT LOGIC STOP LOGIC 2 DIF(18:17) OE(16:5)#, OE_01234# 13 CLK_IN CLK_IN# SPREAD COMPATIBLE PLL GEAR SHIFT LOGIC STOP LOGIC 17 DIF(16:0) HIGH_BW# FS_A_410 SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK CONTROL LOGIC IREF IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD 1386A - 02/02/10 1 9FG1901H Frequency Gearing Clock for CPU, PCIe Gen1 & FBD SMB_A2_PLLBYP# Pin Configuration OE17_18# CLK_IN# DIF_18# DIF_17# DIF_16# DIF_15# DIF_14# CLK_IN DIF_18 DIF_17 DIF_16 DIF_15 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 IREF GNDA VDDA/PD# HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# 1 2 3 4 5 6 7 8 9 54 OE14# 53 DIF_13# 52 DIF_13 51 OE13# 50 DIF_12# 49 DIF_12 48 OE12# 47 VDD 46 GND 45 DIF_11# 44 DIF_11 43 OE11# 42 DIF_10# 41 DIF_10 40 OE10# 39 DIF_9# 38 DIF_9 37 OE9# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# DIF_6 DIF_6# VDD GND OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 GND 10 VDD 11 DIF_2 12 DIF_2# 13 DIF_3 14 DIF_3# 15 DIF_4 16 DIF_4# 17 OE_01234# 18 9FG1901 72-pin MLF Functionality at Power Up (PLL Mode) FS_A_410 1 0 1 Power Groups Pin Number VDD GND 3 2 11,27,47,63 10,28,46,64 Description Main PLL, Analog DIF clocks CLK_IN (CPU FSB) MHz 100