9LPR502YGLFT

Datasheet 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Recommended Application: CK505 compliant clock with fully integrated voltage regulator, PCIe Gen 1 compliant ICS9LPR502 Key Specifications: • • • • CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on CPU & SRC clocks Output Features: • • • • • • • • 2 - CPU differential low power push-pull pairs 7 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable differential low power push-pull pair 1 - SRC/DOT selectable differential low power push-pull pair 5 - PCI, 33MHz 1 - PCI_F, 33MHz free running 1 - USB, 48MHz 1 - REF, 14.318MHz Features/Benefits: • • • • Does not require external pass transistor for voltage regulator Supports spread spectrum modulation, default is 0.5% down spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning One differential push-pull pair selectable between SRC and two single-ended outputs Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 Pin Configuration USB MHz DOT MHz FSLB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDDI/O96Mhz DOTT_96/SRCT0 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3I/O SRCT2/SATAT SRCC2/SATAC GNDSRC SRCT3/CR#_C SRCC3/CR#_D VDDSRCI/O SRCT4 SRCC4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1 CPUC1 VDDI/OCPU NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRCI/O SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 1124D—02/26/09 56-SSOP/TSSOP IDT /ICS TM TM 56-pin CK505 w/Fully Integrated Voltage Regulator 1 ICS 9LPR502 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION SSOP/TSSOP Pin Description PIN # PIN NAME TYPE 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on powerup as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 output. 1.05 to 3.3V +/-5%. True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3 OUT 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 10 11 12 13 GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 PWR PWR I/O PWR PWR OUT 14 15 16 DOTC_96/SRCC0 GND VDD OUT PWR PWR IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 2 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION SSOP/TSSOP Pin Description (continued) PIN # 17 18 19 20 21 22 23 PIN NAME SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC TYPE OUT OUT PWR PWR OUT OUT PWR True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. 1.05 to 3.3V +/-5%. True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair Power supply for SRC clocks. 1.05 to 3.3V +/-5%. True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 24 SRCT3/CR#_C I/O 25 SRCC3/CR#_D I/O 26 27 28 VDDSRC_IO SRCT4 SRCC4 PWR I/O I/O IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 3 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION SSOP/TSSOP Pin Description (Continued) PIN # PIN NAME TYPE Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC Pre-drivers, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. Power supply for SRC outputs. 1.05 to 3.3V +/-5%. Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect Supply for CPU outputs. 1.05 to 3.3V +/-5%. Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. 29 CPU_STOP#/SRCC5 I/O 30 PCI_STOP#/SRCT5 I/O 31 32 33 34 VDDSRC SRCC6 SRCT6 GNDSRC PWR OUT OUT PWR 35 SRCC7/CR#_E I/O 36 SRCT7/CR#_F I/O 37 VDDSRC_IO PWR 38 CPUC2_ITP/SRCC8 OUT 39 CPUT2_ITP/SRCT8 OUT 40 41 42 43 44 45 46 47 NC VDDCPU_IO CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU N/A PWR OUT OUT PWR OUT OUT PWR IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 4 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION SSOP/TSSOP Pin Description (Continued) PIN # 48 49 50 51 52 53 54 55 56 PIN NAME CK_PWRGD/PD# FSLB/TEST_MODE GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK TYPE IN IN PWR OUT IN PWR I/O I/O IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Fully Integrated Regulator Connection for Desktop/Mobile Applications ICS9LPR502 ICS9LPRS502 VDDCPU_IO, Pin 41 1.05V to 3.3V (+/-5%) CPU_IO Decoupling Network NC PIN 40 96_IO Decoupling Network PLL3_IO Decoupling Network SRC_IO Decoupling Network VDDSRC_IO Pin 37, 26 VDDPLL3_IO, Pin 20 VDD96_IO, Pin 12 IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 5 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information SSOP/TSSOP Pin Description (Continued) CPUC2_ITP/SRCC8 FSLB/TEST_MODE CPUT2_ITP/SRCT8 CK_PWRGD/PD# VDDI/OCPU 56 55 54 53 52 51 50 49 48 47 46 45 44 43 X2 X1 VDDREF REF0/FSLC/TEST_SEL 1 2 3 4 SDATA 5 6 7 8 9 10 11 12 13 14 VDDI/O96Mhz GND48 VDD48 USB_48MHz/FSLA 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SRCT2/SATAT SRCC2/SATAC VDDPLL3I/O SRCT7/CR#_F SRCC7/CR#_E GNDSRC VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 SRCT11 SRCC11 SRCC4 SRCT4 VDDSRCI/O SRCC3/CR#_D SRCT3/CR#_C GNDSRC SCLK PCI0/CR#_A VDDPCI PCI1/CR#_B PCI2/TME PCI3 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI ICS9LPR502 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DOTT_96/SRCT0 DOTC_96/SRCC0 SRCT1/SE1 GND SRCC1/SE2 GND VDD 56-pin MLF IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator VDDSRCI/O GNDCPU VDDCPU GNDREF CPUC0 CPUC1 CPUT0 CPUT1 NC 1124D—02/26/09 6 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION MLF Pin Description PIN # 1 2 3 4 5 6 X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK PIN NAME TYPE OUT IN PWR I/O I/O IN Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. 7 PCI0/CR#_A I/O 8 VDDPCI PWR 9 PCI1/CR#_B I/O 10 PCI2/TME I/O 11 PCI3 OUT 12 PCI4/SRC5_EN I/O 13 14 PCI_F5/ITP_EN GNDPCI I/O PWR IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 7 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION MLF Pin Description (Continued) PIN # 15 16 17 18 19 VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 PIN NAME TYPE PWR I/O PWR PWR OUT Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 output. 1.05 to 3.3V +/-5%. True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. 1.05 to 3.3V +/-5%. True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. 20 21 22 23 24 25 26 27 28 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC OUT PWR PWR OUT OUT PWR PWR OUT OUT IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 8 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION MLF Pin Description (Continued) PIN # 29 GNDSRC PIN NAME TYPE PWR 30 SRCT3/CR#_C I/O 31 SRCC3/CR#_D I/O 32 33 34 35 36 VDDSRC_IO SRCT4 SRCC4 SRCC11 SRCT11 PWR I/O I/O OUT OUT Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair Power supply for SRC outputs. 1.05 to 3.3V +/-5%. True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC Pre-drivers, 3.3V nominal Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. 37 CPU_STOP#/SRCC5 I/O 38 PCI_STOP#/SRCT5 I/O 39 40 VDDSRC GNDSRC PWR PWR 41 SRCC7/CR#_E I/O 42 SRCT7/CR#_F I/O IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 9 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information DESCRIPTION MLF Pin Description (Continued) PIN # 43 PIN NAME VDDSRC_IO TYPE PWR Power supply for SRC outputs. 1.05 to 3.3V +/-5%. Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP Not Connected Power supply for CPU outputs. 1.05 to 3.3V +/-5%. Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit 44 CPUC2_ITP/SRCC8 OUT 45 CPUT2_ITP/SRCT8 OUT 46 47 48 49 50 51 52 53 54 55 56 NC VDDCPU_IO CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE GNDREF NC PWR OUT OUT PWR OUT OUT PWR IN IN PWR IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 10 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information General Description ICS9LPR502 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation Intel processors and Intel chipsets. ICS9LPR502 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Funtional Block Diagram X1 R EF X2 REF CPU(1:0) OSC SRC8/ITP CPU CPU PLL1 SS SRC SR C _M A IN SRC(7:3) PCI33MHz SRC PCI(5:0) PLL3 SS PCI33MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:F) SRC5_EN ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC1/SE(2:1) Control Logic Differential Output SE Outputs 7 SATA SRC0/DOT96 PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD GND 41 44 47 44 26, 37 23,34 31 23,34 20 19 16 19 12 11 9 11 53 50 2 8 Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 11 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information MIN MAX 4.6 3.8 4.6 150 UNITS Notes V 7 V 7 V 4,5,7 V 4,7 ° 4,7 C V 6,7 Absolute Maximum Ratings - DC Parameters PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection 1 2 3 SYMBOL VDDxxx VDDxxx_IO V IH V IL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V Inputs Any Input Human Body Model GND - 0.5 -65 2000 Guaranteed by design and characterization, not 100% tested in production. O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed VDD PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Low Threshold Input- High Voltage Low Threshold Input- FSC = '1' Voltage SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE VIH_FS_TEST VIH_FS_FSC VIH_FS_FSAB VIL_FS VIL_CFGHI VIL_CFGMID VIL_CFGLO IIN IINRES VOHSE VOLSE IDDOP3.3 IDDOPIO IDDiAMT3.3 IDDiAMTIO IDDPD3.3 IDDPDIO Fi Lpin CIN COUT CINX TSTAB TDRCROFF TDRCRON TDRSRC TFALL TRISE VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS fSSMOD CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended 3.3V inputs Single-ended 3.3V inputs 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% Optional input, 2.75V typ. Optional input, 1.65V typ. Optional input, 0.55V typ. VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Full Active, CL = Full load; Idd 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V Rail M1 Mode, IO Rail Power down mode, 3.3V Rail Power down mode, IO Rail VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock Output stop after CR deasserted Output run after CR asserted CPU output enable after PCI_STOP# de-assertion Fall/rise time of all 3.3V control inputs from 20-80% 2.7 @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Triangular Modulation 4 1000 300 30 100 33 MIN 0 3.135 0.9975 2 VSS - 0.3 2 0.7 0.7 VSS - 0.3 2.4 1.3 VSS - 0.3 -5 -200 2.4 0.4 200 70 80 10 5 0.1 15 7 5 6 6 1.8 400 0 10 10 10 5.5 0.4 MAX UNITS Notes 70 °C 3.465 V 3.465 V 10 VDD + 0.3 V 3 0.8 V 3 VDD + 0.3 V 8 1.5 V 8 VDD+0.3 0.35 VDD+0.3 2 0.9 5 200 V V V V V uA uA V V mA mA mA mA mA mA MHz nH pF pF pF ms ns us ns ns ns V V mA ns ns kHz kHz 1 1 10 9 9 9 2 Electrical Characteristics - Input/Supply/Common Output DC Parameters Low Threshold Input- FSA,FSB = '1' Voltage Low Threshold Input-Low Voltage PCI3/CFG0 Input PCI3/CFG0 Input PCI3/CFG0 Input Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Operating Supply Current iAMT Mode Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Tdrive_CR_off Tdrive_CR_on Tdrive_CPU Tfall_SE Trise_SE SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency Spread Spectrum Modulation Frequency 10 1.5 Electrical Characteristics - Input/Supply/Common Output DC ParametersDC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 2 3 4 5 6 7 8 9 Signal is required to be monotonic in this region. input leakage current does not include inputs with pull-up or pull-down resistors 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. Intentionally blank Maximum VIH is not to exceed VDD Human Body Model Operation under these conditions is neither implied, nor guaranteed. Frequency Select pins which have tri-level input PCI3/CFG0 is optional If present. Not all parts have this feature. 10 IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 12 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information MIN 2.5 2.5 300 300 MAX 4 4 20 550 140 1150 55 100 100 150 3000 UNITS NOTES V/ns 2, 3 V/ns 2, 3 % 1, 10 mV 2 mV 1,4,5 mV 1,4,9 mV 1,7 mV 1,8 % 2 ps ps 1 ps 1 ps 1,6,11 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU Skew CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew 1 2 3 4 5 6 7 8 9 SYMBOL tSLR tFLR tSLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC CPUSKEW CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Averaging on Differential Measurement Differential Measurement Differential Measurement -300 45 NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) O nly applies to the differential rising edge (Clock rising, Clock# falling) T otal distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps. T he max voltage including overshoot. T he min voltage including undershoot. T he total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced Matching applies to C rising edge rate for Clock and falling C edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets F or PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew. 10 11 C Clock Jitter Specs - Low Power Differential Outputs PARAMETER CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle 1 SYMBOL CPUJC2C SRCJC2C DOTJC2C CONDITIONS Differential Measurement Differential Measurement Differential Measurement MIN MAX 85 125 250 UNITS NOTES ps 1 ps 1,2 ps 1 NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece 2 Phase jitter requirement: The deisgnated G e2 outputs will meet the reference clock jitter requiremernts from the PCI Express G en2 Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement methodology is as defined by the PCI SIG. IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 13 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information MIN -100 29.99700 30.08421 29.49700 29.56617 2.4 -33 30 1 1 100 45 MAX UNITS NOTES 100 ppm 1,2 30.00300 ns 2 30.23459 ns 2 30.50300 ns 2 30.58421 ns 2 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 4 V/ns 1 4 V/ns 1 250 ps 2 200 ps 2 55 % 2 500 ps 2 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs V OH V OL I OH I OL t SLR t FLR tskew tskew dt1 t jcy c-cy c CONDITIONS see Tperiod min-max values 33.33MHz output no spread 33.33MHz output spread 33.33MHz output no spread 33.33MHz output nominal/spread I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs THIGH TLOW V OH V OL I OH I OL t SLR t FLR dt1 t jcy c-cy c CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal MIN -100 20.83125 20.48125 8.216563 7.816563 2.4 -29 29 1 1 45 MAX UNITS NOTES 100 ppm 2,4 20.83542 ns 2,3 21.18542 ns 2 11.15198 V 10.95198 V V 0.55 V mA -23 mA mA 27 mA 2 V/ns 1 2 V/ns 1 55 % 2 350 ps 2 I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 14 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information MIN -100 69.82033 69.83400 29.97543 29.57543 2.4 -33 30 1 1 45 MAX UNITS Notes 100 ppm 2, 4 69.86224 ns 2, 3 70.84800 ns 2 38.46654 V 38.26654 V V 0.4 V -33 38 4 4 55 1000 mA mA V/ns V/ns % ps 1 1 2 2 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle 1 2 3 4 SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Edge rate in system is measured from 0.8V to 2.0V. Duty cycle, Peroid and Jitter are measured with respect to 1.5V The average period over any 1us period of time Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 15 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information USB MHz DOT MHz Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 FSLB B0b6 0 0 1 1 0 0 1 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: PLL3 Quick Configuration B1b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B1b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin 17 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A Pin 18 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A Spread Comment % PLL 3 disabled 0.5% Down Spread SRCCLK1 from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A N/A IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 16 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1 Table 4: Device ID table B8b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B8b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B8b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B8b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comment 56 pin TSSOP/QFN 64 pin TSSOP/QFN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 17 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Differential Clocks (Except CPU) Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low CK= Pull down, CK# = Low PCI_STOP# Power Management Single-ended Clocks SMBus OE Bit PCI_STOP# 1 Stop Drive Mode X 0 Enable 0 1 Disable X X Low Low Low Stoppable Running Free running Running CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 1 Disable CR# Power Management SMBus OE Bit Enable Disable PD# Power Management Single-ended Clocks Device State Latches Open Power Down Low M1 Virtual Power Cycle to Latches Open Hi-Z w/o Latched input w/Latched input CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CK= Pull down, CK# = Low CK= Pull down CK# = Low Running CK= Pull down, CK# = Low Differential Clocks (Except CPU1) CPU1 CR# 1 0 X Stop Drive Mode X Differential Clocks Stoppable Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low X X Stop Drive Mode X 0 Differential Clocks Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low Low IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 18 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information General SMBus serial interface information for the ICS9LPR502 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK Byte N + X - 1 N P Not acknowledge stoP bit IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 19 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Default Latch Latch Latch 0 0 0 0 Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 4 3 2 1 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL Description Type 0 1 CPU Freq. Sel. Bit (Most Significant) R See Table 1 : CPU Frequency Select Table CPU Freq. Sel. Bit R CPU Freq. Sel. Bit (Least Significant) R Set via SMBus or dynamically by CK505 if detects RW iAMT Enabled Legacy Mode dynamic M1 Reserved RW Select source for SRC Main RW SRC Main = PLL3 SRC Main = PLL1 Select source for SATA clock RW SATA = SRC_Main SATA = PLL2 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on Configuration Saved RW Configuration Not Saved and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. 0 - PD_Restore 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config B it 1 PLL3 Quick Config B it 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down s pread Down spread 1 DOT96 Center s pread Center spread Default 0 0 0 0 0 0 1 1 See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from PLL1 PCI from SRC_MAIN Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Description Output enable for REF, if disabled output is tri-stated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW Output Output Output Out put Out put Output Output Out put 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Out put enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW Output Output Out put Out put Output Output Out put Out put 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Out put enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's s pread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Out put Disabled Out put Disabled Output Disabled Output Disabled Out put Disabled S pread Disabled S pread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 20 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Byte 5 Clock Request Enable/Configuration Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Default 0 0 0 0 0 0 0 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved If set, SSCD (SRC1) stops with PCI_STOP# If set, SRCs (except SRC1) stop with PCI_STOP# Type RW RW RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_H 1 Enable CR#_E Enable CR#_F Enable CR#_G Enable CR#_H Default 0 0 0 0 0 0 0 0 Free Running Free Running Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Description Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Vendor specific Vendor ID ICS is 0001, binary Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Type R Table of Device identifier codes, used for R R differentiating between CK505 package options, etc. R RW Reserved RW Reserved Output enable for SE1 RW Output enable for SE2 RW Description 0 See Device ID Table Disabled Disabled Enabled Enabled 1 Default 0 0 0 0 0 0 0 0 Byte 9 Output Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback Reserved Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Reserved Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 0 Free running normal operation Outputs HI-Z Normal operation 1 Stops with PCI_STOP# assertion no overclocking Outputs = REF/N Test mode Default 0 0 1 0 0 1 0 1 See Table 3: V_IO Selection (Default is 0.8V) IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 21 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running 1 SRC5 Enabled TBD TBD TBD TBD TBD Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Byte 10 CK505 Rev 0.85 functions (ICS Rev H silicon and higher) Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved CPU2_iAMT_EN CPU1_iAMT_EN PCIe-Gen2 CPU2 Stop Enable Description Reserved Enables CPU2(ITP) output in iAMT state (M1) Enables CPU1 output in iAMT state (M1) PCIe-Gen2 status Enables control of CPU2(ITP) with CPU_STOP# Type RW RW RW RW RW RW R RW 0 TBD TBD TBD TBD Off in iAMT Off in iAMT non-Gen2 Free Running 1 TBD TBD TBD TBD Free running in iAMT Free running in iAMT PCIe Gen2 compliant Stoppable Default 0 0 0 0 0 1 0 1 Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Read Back byte count register, max bytes = 32 Byte 13 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Type RW RW RW RW The decimal representation of M and N Divider in Byte RW 13 and 14 will configure the VCO frequency. Default RW at power up = latch-in or Byte 0 Rom table. RW RW Description N Divider 8 N Divider 9 0 1 Default X X X X X X X X Byte 14 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Type RW RW RW The decimal representation of M and N Divider in Byte RW 13 and 14 will configure the VCO frequency. Default RW at power up = latch-in or Byte 0 Rom table. RW RW RW Description 0 1 Default X X X X X X X X IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 22 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Byte 15 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 16 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 x X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 17 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Type RW RW RW RW The decimal representation of M and N Divider in Byte RW 17 and 18 will configure the VCO frequency. Default RW at power up = latch-in or Byte 0 Rom table. RW RW Description N Divider 8 N Divider 9 0 1 Default X X X X X X X X Byte 18 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Type RW RW RW The decimal representation of M and N Divider in Byte RW 17 and 18 will configure the VCO frequency. Default RW at power up = latch-in or Byte 0 Rom table. RW RW RW Description 0 1 Default X X X X X X X X Byte 19 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 23 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Type RW RW RW RW RW RW RW RW 0 1 Default 0 X X X X X X X Byte 20 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 21 M/N Enables Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved M/N Enable CPU M/N Enable Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 0 0 Disable Disable Enable Enable Byte 22 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 8 N Div bit 9 M Div Bit 5 M Div Bit 4 M Div Bit 3 M Div Bit 2 M Div Bit 1 M Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Byte 23 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 7 N Div bit 6 N Div bit 5 N Div bit 4 N Div bit 3 N Div bit 2 N Div bit 1 N Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Bytes 24-62 Reserved Byte 63 Special Power Management Features (Rev P Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved SATA PLL XTAL PD Control Description RW RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 Note 1 Power Management Feature Controls XTAL on/off in legacy PD off off on on Note: Default is "off" for Rev P Silicon and higher. *Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions. IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 24 ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information HW SW REF/N or HI-Z B9b4 Test Clarification Table Comments FSLB/ TEST TEST_MOD FSLC/ ENTRY BIT E TEST_SEL B9b3 HW PIN HW PIN Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N