9LPRS501YGLFT

Datasheet 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Recommended Application: CK505 compliant clock with fully integrated voltage regulator and Internal series resistor on differential outputs, PCIe Gen 1 compliant ICS9LPRS501 Key Specifications: • • • • CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on CPU & SRC clocks Output Features: • • • • • • • • 2 - CPU differential low power push-pull pairs 10 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable differential low power push-pull pair 1 - SRC/DOT selectable differential low power push-pull pair 5 - PCI, 33MHz 1 - PCI_F, 33MHz free running 1 - USB, 48MHz 1 - REF, 14.318MHz • • • • • Features/Benefits: Does not require external pass transistor for voltage regulator Integrated series resistors on differential outputs, Zo=50Ω Supports spread spectrum modulation, default is 0.5% down spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning One differential push-pull pair selectable between SRC and two single-ended outputs Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 TSSOP Pin Configuration USB MHz DOT MHz FSLB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. PCI0/CR#_A 1 VDDPCI 2 PCI1/CR#_B 3 PCI2/TME 4 PCI3 5 PCI4/SRC5_EN 6 PCI_F5/ITP_EN 7 GNDPCI 8 VDD48 9 USB_48MHz/FSLA 10 GND48 11 VDD96_IO 12 DOTT_96/SRCT0 13 DOTC_96/SRCC0 14 GND 15 VDD 16 SRCT1/SE1 17 SRCC1/SE2 18 GND 19 VDDPLL3_IO 20 SRCT2/SATAT 21 SRCC2/SATAC 22 GNDSRC 23 SRCT3/CR#_C 24 SRCC3/CR#_D 25 VDDSRC_IO 26 SRCT4 27 SRCC4 28 GNDSRC 29 SRCT9 30 SRCC9 31 SRCC11/CR#_G 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 9LPRS501 1121F—02/23/09 1 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information TSSOP Pin Description PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 37 and 38). The latched value controls the pin function on pins 37 and 38 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3 OUT 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 10 11 12 13 GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 PWR PWR I/O PWR PWR OUT 14 DOTC_96/SRCC0 OUT 15 16 GND VDD PWR PWR IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 2 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information TSSOP Pin Description (continued) PIN # 17 18 19 20 21 22 23 PIN NAME SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC TYPE OUT OUT PWR PWR OUT OUT PWR DESCRIPTION True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 24 SRCT3/CR#_C I/O 25 SRCC3/CR#_D I/O 26 27 28 29 30 31 VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 PWR I/O I/O PWR OUT OUT 32 SRCC11/CR#_G I/O IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 3 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information TSSOP Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3 bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC internal circuits, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP No Connect 33 SRCT11/CR#_H I/O 34 35 36 SRCT10 SRCC10 VDDSRC_IO OUT OUT PWR 37 CPU_STOP#/SRCC5 I/O 38 PCI_STOP#/SRCT5 I/O 39 40 41 42 VDDSRC SRCC6 SRCT6 GNDSRC PWR OUT OUT PWR 43 SRCC7/CR#_E I/O 44 SRCT7/CR#_F I/O 45 VDDSRC_IO PWR 46 CPUC2_ITP/SRCC8 OUT 47 CPUT2_ITP/SRCT8 OUT 48 NC N/A IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 4 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information TSSOP Pin Description (Continued) PIN # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK PIN NAME VDDCPU_IO TYPE PWR OUT OUT PWR OUT OUT PWR IN IN PWR OUT IN PWR I/O I/O IN DESCRIPTION Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT. True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. Ground Pin for CPU Outputs Complement clock of low power differential CPU clock pair. True clock of low power differential CPU clock pair. Power Supply 3.3V nominal. Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Fully Integrated Regulator Connection for Desktop/Mobile Applications ICS9LPR501 ICS9LPRS501 VDDCPU_IO, Pin 49 1.05V to 3.3V (+/-5%) CPU_IO Decoupling Network NC PIN 48 96_IO Decoupling Network PLL3_IO Decoupling Network SRC_IO Decoupling Network VDDSRC_IO Pin 45,36,26 VDDPLL3_IO, Pin 20 VDD96_IO, Pin 12 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 5 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information MLF Pin Configuration CPUC2_ITP/SRCC8 CPUT2_ITP/SRCT8 FSLB/TEST_MODE CK_PWRGD/PD# SRCC7/CR#_E SRCT7/CR#_F VDDSRC_IO VDDCPU_IO CPUC1_F CPUT1_F 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK PCI0/CR#_A VDDPCI GNDSRC 48 47 46 45 44 43 42 GNDCPU VDDCPU CPUC0 CPUT0 NC 1 2 3 4 5 6 7 8 9 SRCT6 SRCC6 VDDSRC PCI_STOP#/SRCT5 CPU_STOP#/SRCC5 VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H SRCC11/CR#_G SRCC9 SRCT9 GNDSRC SRCC4 SRCT4 VDDSRC_IO ICS9LPRS501 41 40 39 38 37 36 35 34 33 PCI1/CR#_B 10 PCI2/TME 11 PCI3 12 PCI4/SRC5_EN 13 PCI_F5/ITP_EN 14 GNDPCI 15 VDD48 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DOTT_96/SRCT0 DOTC_96/SRCC0 VDDPLL3_IO VDD96_IO GND48 SRCT1/SE1 SRCC1/SE2 USB_48MHz/FSLA SRCT2/SATAT GND GND VDD SRCT3/CR#_C SRCC2/SATAC IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor SRCC3/CR#_D GNDSRC 1121F—02/23/09 6 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information MLF Pin Description PIN # 1 2 3 4 5 6 7 PIN NAME GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK TYPE PWR OUT IN PWR I/O I/O IN DESCRIPTION Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. 8 PCI0/CR#_A I/O 9 VDDPCI PWR 10 PCI1/CR#_B I/O 11 PCI2/TME I/O 12 PCI3 OUT 13 PCI4/SRC5_EN I/O 14 PCI_F5/ITP_EN I/O 15 16 GNDPCI VDD48 PWR PWR IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 7 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information MLF Pin Description (Continued) PIN # 17 18 19 20 PIN NAME USB_48MHz/FSLA GND48 VDD96_IO DOTT_96/SRCT0 TYPE I/O PWR PWR OUT DESCRIPTION Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. Power supply for DOT96 outputs, VDD96_IO is 1.05 to 3.3V with +/-5% tolerance True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. True clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin for SRC / SE1 and SE2 clocks, PLL3. Power supply for PLL3 output. VDDPLL3_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC/SATA clock pair. Complement clock of differential SRC/SATA clock pair. Ground pin for SRC clocks. True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default), 1= CR#_D controls SRC4 pair 21 22 23 24 25 26 27 28 29 30 DOTC_96/SRCC0 GND VDD SRCT1/SE1 SRCC1/SE2 GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR 31 SRCT3/CR#_C I/O 32 SRCC3/CR#_D I/O IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 8 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information MLF Pin Description (Continued) PIN # 33 34 35 36 37 38 PIN NAME VDDSRC_IO SRCT4 SRCC4 GNDSRC SRCT9 SRCC9 TYPE PWR I/O I/O PWR OUT OUT DESCRIPTION Power supply for SRC clocks. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance True clock of differential SRC clock pair 4 Complement clock of differential SRC clock pair 4 Ground pin for SRC clocks. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. SRC11 complement /Clock Request control for SRC9 pair The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 SRC11 true or Clock Request control H for SRC10 pair The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in byte 3, bit 6 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10. True clock of differential SRC clock pair. Cpmplement clock of differential SRC clock pair. Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Stops all CPU Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= CPU_STOP# 1 = SRC5 In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values Stops all PCI Clocks, except those set to be free running clocks / Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows: 0= PCI_STOP# 1 = SRC5# In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37. VDD pin for SRC internal circuits, 3.3V nominal Complement clock of low power differential SRC clock pair. True clock of low power differential SRC clock pair. 39 SRCC11/CR#_G I/O 40 SRCT11/CR#_H I/O 41 42 43 SRCT10 SRCC10 VDDSRC_IO OUT OUT PWR 44 CPU_STOP#/SRCC5 I/O 45 PCI_STOP#/SRCT5 I/O 46 47 48 VDDSRC SRCC6 SRCT6 PWR OUT OUT IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 9 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information MLF Pin Description (Continued) PIN # 49 PIN NAME GNDSRC TYPE PWR Ground for SRC clocks DESCRIPTION SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8. 50 SRCC7/CR#_E I/O 51 SRCT7/CR#_F I/O 52 VDDSRC_IO 53 CPUC2_ITP/SRCC8 PWR Power supply for SRC outputs. VDDSRC_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: OUT Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: OUT Pin 7 latched input Value 0 = SRC8 1 = ITP N/A No Connect PWR Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance Complement clock of low power differenatial CPU clock pair. This clock will be free-running during OUT iAMT. OUT True clock of low power differential CPU clock pair. This clock will be free-running during iAMT. PWR Ground Pin for CPU Outputs OUT Complement clock of low power differential CPU clock pair. OUT True clock of low power differential CPU clock pair. PWR Power Supply 3.3V nominal. IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and IN Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. 54 CPUT2_ITP/SRCT8 55 56 57 58 59 60 61 62 63 64 NC VDDCPU_IO CPUC1_F CPUT1_F GNDCPU CPUC0 CPUT0 VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 10 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information General Description ICS9LPRS501 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation Intel processors and Intel chipsets. ICS9LPRS501 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Funtional Block Diagram X1 R EF X2 REF CPU(1:0) OSC SRC8/ITP CPU CPU PLL1 SS SRC SR C _M A IN SRC(11-9,7:3) PCI33MHz SRC PCI PLL3 SS PCI33MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:H) SRC5_EN ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC1/SE(2:1) Control Logic Differential Output SE Outputs 7 SATA SRC0/DOT96 PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD GND 49 52 55 52 26, 36, 45 23, 29, 42 39 23, 29, 42 20 19 16 19 12 11 9 11 61 58 2 8 Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 11 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Absolute Maximum Ratings PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Case Temperature Input ESD protection SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts Tcase ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V LVCMOS Inputs Any Input Human Body Model 2000 GND - 0.5 -65 150 115 0.99 MIN MAX 4.6 3.8 4.6 UNITS Notes V V V V ° 1,7 1,7 1,7,8 1,7 1,7 1,7 1,7 C °C V Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE IIN IINRES VOHSE VOLSE VOHDIF VOLDIF VIH_FS_TEST VIH_FS VIL_FS IDD_DEFAULT IDD_PLL3DIF Operating Supply Current IDD_PLL3SE IDD_IO IDD_PD3.3 Power Down Current IDD_PDIO IDD_iAMT3.3 IDD_iAMT0.8 Fi Lpin CIN Input Capacitance COUT CINX Logic Inputs Output pin capacitance X1 & X2 pins 1.5 CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Differential Outputs Differential Outputs 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, PLL3 off 3.3V supply, PLL3 Differential Out 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode 3.3V supply, iAMT Mode 0.8V IO supply, iAMTMode VDD = 3.3 V 2 0.7 VSS - 0.3 0.7 MIN 0 3.135 0.99 2 VSS - 0.3 -5 -200 2.4 0.4 0.9 0.4 VDD + 0.3 1.5 0.35 200 250 250 70 10 0.1 26 10 15 7 5 6 6 MAX 70 3.465 3.465 VDD + 0.3 0.8 5 200 UNITS Notes °C V V V V uA uA V V V V V V V mA mA mA mA mA mA mA mA MHz nH pF pF pF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1121F—02/23/09 iAMT Mode Current Input Frequency Pin Inductance IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 12 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information AC Electrical Characteristics - Input/Common Parameters PARAMETER Clk Stabilization Tdrive_SRC Tdrive_PD# Tdrive_CPU Tfall_PD# Trise_PD# SYMBOL TSTAB T DRSRC TDRPD T DRSRC T FALL T RISE CONDITIONS From VDD Power-Up or deassertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 15 300 10 5 5 UNITS Notes ms ns us ns ns ns 1 1 1 1 1 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS VXABSVAR DCYC CPUJ C2C SRCJ C2C DOTJ C2C CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement 45 -300 300 300 550 140 55 85 125 250 100 150 3000 MIN 2.5 2.5 MAX 8 8 20 1150 UNITS NOTES V/ns V/ns % mV mV mV mV mV % ps ps ps ps ps ps 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 1 1 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Skew Intentional PCI-PCI delay Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tskew tdelay tj c y c-c y c CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal/spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 1 45 30 38 4 4 55 250 200 nominal 500 -33 -33 MIN -300 29.99100 29.49100 2.4 0.4 MAX 300 30.00900 30.15980 30.65980 UNITS NOTES 1,6 ppm ns ns ns V V mA mA mA mA V/ns V/ns % ps ps ps 6 6 6 1 1 1 1 1 1 1 1 1 1 1,9 1 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 13 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tj c y c-c y c CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V 1 1 45 29 27 2 2 55 350 -29 -23 MIN -100 20.83125 20.48130 2.4 0.4 MAX 100 20.83542 21.18540 UNITS NOTES ppm 1,2 ns ns V V mA mA mA mA V/ns V/ns % ps 2 2 1 1 1 1 1 1 1 1 1 1 Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = - 1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V -33 30 1 1 45 MIN -300 69.8203 69.8203 2.4 0.4 -33 38 4 4 55 1000 MAX 300 69.8622 70.86224 UNITS Notes ppm ns ns V V mA mA V/ns V/ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 14 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Electrical Characteristics - SE1/2=25MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle Jitter, Long Term SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tj c y c-c y c tLTJ CONDITIONS see Tperiod min-max values 25.00MHz output nominal 25.00MHz output nominal IOH = - 1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V @ 10us delay 1 1 45 29 27 4 4 55 500 3000 -29 -23 MIN -100 39.99600 39.32360 2.4 0.4 MAX 100 40.00400 40.67640 UNITS NOTES ppm 1,2 ns ns V V mA mA mA mA V/ns V/ns % ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 Electrical Characteristics - SMBus Interface PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP T RI2C T FI2C F SMBUS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 CONDITIONS MIN 2.7 MAX 5.5 0.4 UNITS Notes V V mA ns ns kHz 1 1 1 1 1 1 Notes on Electrical Characteristics: 1Guaranteed 2 3 4 5 by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# O nly applies to the differential rising edge (CLK rising and CLK# falling) D efined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 7 8 9 O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 15 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Table 1: CPU Frequency S elect Table FS LC B0b7 0 0 0 0 1 1 1 1 2 1 1 FS LB B0b6 0 0 1 1 0 0 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: PLL3 Quick Configuration B1b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B1b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin 17 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A Pin 18 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A Spread Comment % PLL 3 disabled 0.5% Down Spread SRCCLK1 from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A N/A IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 16 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1 Table 4: Device ID table B8b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B8b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B8b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B8b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comment 56 pin TSSOP/QFN 64 pin TSSOP/QFN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 17 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information PCI_STOP# Power Management Single-ended Clocks SMBus OE Bit PCI_STOP# 1 Stop Drive Mode X 0 Enable 0 1 Disable X X Low Low Low Stoppable Running Free running Running Differential Clocks (Except CPU) Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low CK= Pull down, CK# = Low CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 1 Disable CR# Power Management SMBus OE Bit Enable Disable PD# Power Management Single-ended Clocks Device State Latches Open Power Down Low M1 Virtual Power Cycle to Latches Open Hi-Z w/o Latched input w/Latched input CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CK= Pull down, CK# = Low CK= Pull down CK# = Low Running CK= Pull down, CK# = Low Differential Clocks (Except CPU1) CPU1 CR# 1 0 X Stop Drive Mode X Differential Clocks Stoppable Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low X X Stop Drive Mode X 0 Differential Clocks Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down Running CK# = Low Low IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 18 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information General SMBus serial interface information for the ICS9LPRS501 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK Byte N + X - 1 N P Not acknowledge stoP bit IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 19 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 4 3 2 1 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL Description CPU Freq. Sel. Bit (Most Significant) CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main Select source for SATA clock 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. Type R R R RW RW RW RW Legacy Mode SRC Main = PLL1 SATA = SRC_Main iAMT Enabled SRC Main = PLL3 SATA = PLL2 0 See Table 1 : CPU Frequency Select Table 1 Default Latch Latch Latch 0 0 0 0 0 - PD_Restore RW Configuration Not Saved Configuration Saved 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down spread Down spread 1 DOT96 Center spread Center spread Default 0 0 0 0 0 0 1 1 See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from PLL1 PCI from SRC_MAIN Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Description Output enable for REF, if disabled output is tri-stated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Output Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 20 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Byte 5 Clock Request Enable/Configuration Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Default 0 0 0 0 0 0 0 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Enable CR#_G (clk req) -> SRC9 Enable CR#_H (clk req) -> SRC10 Reserved Reserved If set, SSCD (SRC1) stops with PCI_STOP# If set, SRCs (except SRC1) stop with PCI_STOP# Type RW RW RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_H 1 Enable CR#_E Enable CR#_F Enable CR#_G Enable CR#_H Default 0 0 0 0 0 0 0 0 Free Running Free Running Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Vendor specific Vendor ID ICS is 0001, binary Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Output enable for SE2 Type R R R R RW RW RW RW 0 See Device ID Table Disabled Disabled Enabled Enabled 1 Default 0 0 0 1 0 0 0 0 Byte 9 Output Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback Reserved Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME ) strap s tatus Reserved Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 0 Free running normal operation Outputs HI-Z Normal operation 1 Stops with PCI_STOP# assertion no overclocking Outputs = REF/N Test mode Default 0 0 1 0 0 1 0 1 See Table 3: V_IO Selection (Default is 0.8V) IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 21 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Byte 10 CK505 Rev 0.85 Functions (ICS Rev H Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running 1 SRC5 Enabled TBD TBD TBD TBD TBD Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved CPU2_iAMT_EN CPU1_iAMT_EN PCIe-Gen2 CPU2 Stop Enable Description Reserved Enables CPU2(ITP) output in iAMT state (M1) Enables CPU1 output in iAMT state (M1) PCIe-Gen2 status Enables control of CPU2(ITP) with CPU_STOP# Type RW RW RW RW RW RW R RW 0 TBD TBD TBD TBD Off in iAMT Off in iAMT non-Gen2 Free Running 1 TBD TBD TBD TBD Free running in iAMT Free running in iAMT PCIe Gen2 compliant Stoppable Default 0 0 0 0 0 1 0 1 Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Read Back byte count register Byte 13 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW Description N Divider 8 N Divider 9 0 1 Default X X X X X X X X Byte 14 CK505 PLL1 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Description 0 1 Default X X X X X X X X Byte 15 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 22 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Byte 16 CK505 PLL1 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 x X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 17 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Type RW RW RW RW The decimal representation of M Div (5:0) is equal RW to reference divider value. Default at power up = RW latch-in or Byte 0 Rom table. RW RW Description N Divider 8 N Divider 9 0 1 Default X X X X X X X X Byte 18 CK505 PLL3 M/N Programming Register Bit 7 6 5 4 3 2 1 0 Pin Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Type RW RW RW The decimal representation of N Div (9:0) is equal RW to VCO divider value. Default at power up = latchRW in or Byte 0 Rom table. RW RW RW Description 0 1 Default X X X X X X X X Byte 19 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Description Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 20 CK505 PLL3 Spread Spectrum Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Description Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 X X X X X X X These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values. Byte 21 M/N Enables Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved M/N Enable CPU M/N Enable SRC/PCI Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 0 0 Disable Disable Enable Enable IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 23 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Byte 22 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 8 N Div bit 9 M Div Bit 5 M Div Bit 4 M Div Bit 3 M Div Bit 2 M Div Bit 1 M Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Byte 23 CPU M/N Programming Bit 7 6 5 4 3 2 1 0 Pin Name N Div bit 7 N Div bit 6 N Div bit 5 N Div bit 4 N Div bit 3 N Div bit 2 N Div bit 1 N Div Bit 0 Description PLL 1 M/N Programming (Intel PLL1 CPU) Type RW RW RW RW RW RW RW RW 0 1 Default X X X X X X X X Bytes 24-62 Reserved Byte 63 Special Power Management Features (Rev P Silicon and Higher) Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved SATA PLL XTAL PD Control Description RW RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 Note 1 Power Management Feature Controls XTAL on/off in legacy PD off off on on Note: Default is "off" for Rev P Silicon and higher. *Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121F—02/23/09 24 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR Advance Information Test Clarification Table Comments FSLC/ TEST_SEL HW PIN HW FSLB/ TEST_MODE HW PIN SW TEST ENTRY BIT B9b3 REF/N or HI-Z B9b4 Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N