9LPRS525AFLFT

DATASHEET 56-pin CK505 for Intel Systems Recommended Application: 56-pin CK505 compatible clock, w/fully integrated Vreg and series resistors on differential outputs Output Features: • 2 - CPU differential low power push-pull pairs • 7 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential low power push-pull pair • 1 - SRC/DOT selectable differential low power push-pull pair • 1 - SRC/SE selectable differential push-pull pair/Single-ended outputs • 5 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequency accuracy on all outputs • SRC outputs meet PCIe Gen2 when sourced from PLL3 Pin Configuration PCI0/CR#_A 1 VDDPCI PCI1/CR#_B PCI2/TME PCI3/CFG0 PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96IO DOTT_96_LRS/SRCT0_LRS DOTC_96_LRS/SRCC0_LRS GND VDD SRCT1_LRS/SE1 SRCC1_LRS/SE2 GND VDDPLL3IO SRCT2_LRS/SATAT_LRS SRCC2_LRS/SATAC_LRS GNDSRC SRCT3_LRS/CR#_C SRCC3_LRS/CR#_D VDDSRCIO SRCT4_LRS SRCC4_LRS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 SCLK 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0_LRS CPUC0_LRS GNDCPU CPUT1_F_LRS CPUC1_F_LRS VDDCPUIO NC CPUT2_ITP_LRS/SRCT8_LRS CPUC2_ITP_LRS/SRCC8_LRS VDDSRCIO SRCT7_LRS/CR#_F SRCC7_LRS/CR#_E GNDSRC SRCT6_LRS SRCC6_LRS VDDSRC PCI_STOP#/SRCT5_LRS CPU_STOP#/SRCC5_LRS ICS9LPRS525 Features/Benefits: • Supports spread spectrum modulation, 0 to -0.5% down spread • Supports CPU clks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 FS LB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB DOT MHz MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. 56-SSOP & TSSOP IDTTM PC MAIN CLOCK 9LPRS525 1484B—01/21/10 1 ICS9LPRS525 PC MAIN CLOCK Pin Description PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRA#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CRA# controls SRC0 pair (default), 1= CRA# controls SRC2 pair Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRB#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CRB# controls SRC1 pair (default) 1= CRB# controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows 0=Overclocking of CPU and SRC allowed 1=Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information 3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground pin for the PCI outputs Power pin for the 48MHz output and PLL.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin for the 48MHz outputs Power supply for DOT96 outputs, 1.05V to 3.3V. True clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0. After powerup, this pin function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows: 0= SRC0 1=DOT96 Complement clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0#. After powerup, this pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows 0= SRC0# 1=DOT96# Ground pin. Power supply, nominal 3.3V True clock of low power differential SRC1 clock pair with integrated 33 ohm Rs. / 3.3V single-ended output. The powerup default is 100 MHz SRC, 0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Complement clock of low powerl differential SRC1 clock pair with integrated 33 ohm Rs / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1] Ground pin. Power supply for PLL3 outputs. 1.05V to 3.3V. True clock of low power differentiall SRC/SATA clock pair with integrated Rs. Complement clock of low power differential push-pull SRC/SATA clock pair with integrated 33 ohm Rs. Ground pin for the SRC outputs True clock of low power differential SRC clock pair with integrated 33 ohm Rs./ Clock Request control C for either SRC0 or SRC2 pair. The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRC#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 3 0 = SRCCLK3 enabled (default) 1= CRC# enabled. Byte 5, bit 2 controls whether CRC# controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CRC# controls SRC0 pair (default), 1= CRC# controls SRC2 pair 1 PCI0/CR#_A I/O 2 VDDPCI PWR 3 PCI1/CR#_B I/O 4 PCI2/TME I/O 5 PCI3/CFG0 I/O 6 PCI4/SRC5_EN I/O 7 PCI_F5/ITP_EN I/O 8 9 10 11 12 13 GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96IO DOTT_96_LRS/SRCT0_LRS PWR PWR I/O PWR PWR OUT 14 15 16 17 18 19 20 21 22 23 DOTC_96_LRS/SRCC0_LRS GND VDD SRCT1_LRS/SE1 SRCC1_LRS/SE2 GND VDDPLL3IO SRCT2_LRS/SATAT_LRS SRCC2_LRS/SATAC_LRS GNDSRC OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR 24 SRCT3_LRS/CR#_C I/O IDTTM PC MAIN CLOCK 1484B—01/21/10 2 ICS9LPRS525 PC MAIN CLOCK Pin Description (continued) PIN # PIN NAME TYPE DESCRIPTION Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair. The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 1 0 = SRC3 enabled (default) 1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CRD# controls SRC1 pair (default), 1= CRD# controls SRC4 pair Power supply for SRC outputs. 1.05V to 3.3V. True clock of low power differential SRC clock pair with integrated 33 ohm Rs. Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs. Stops all CPUCLK, except those set to be free running clocks / Complement clock of low power differential SRC pair with 33 ohm integrated Rs. Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair with integrated 33 ohm Rs. Supply for SRC PLL, 3.3V nominal Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs. True clock of low power differential SRC clock pair with integrated 33 ohm Rs. Ground pin for the SRC outputs Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CRE# enabled. True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SR Power supply for SRC outputs. 1.05V to 3.3V. Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: Pin 7 latched input Value 0 = SRC8 1 = ITP 25 SRCC3_LRS/CR#_D I/O 26 27 28 29 30 31 32 33 34 VDDSRCIO SRCT4_LRS SRCC4_LRS CPU_STOP#/SRCC5_LRS PCI_STOP#/SRCT5_LRS VDDSRC SRCC6_LRS SRCT6_LRS GNDSRC PWR OUT OUT I/O I/O PWR OUT OUT PWR 35 SRCC7_LRS/CR#_E I/O 36 37 SRCT7_LRS/CR#_F VDDSRCIO I/O PWR 38 CPUC2_ITP_LRS/SRCC8_LRS OUT 39 CPUT2_ITP_LRS/SRCT8_LRS OUT 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 NC VDDCPUIO CPUC1_F_LRS CPUT1_F_LRS GNDCPU CPUC0_LRS CPUT0_LRS VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK N/A PWR OUT OUT PWR OUT OUT PWR IN IN PWR OUT IN PWR I/O I/O IN No Connect Power supply for CPU outputs, 1.05V to 3.3V. Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT. True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT. Ground pin for the CPU outputs Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs. True clock of low power differential CPU clock pair with integrated 33 ohm Rs. Supply for CPU PLL, 3.3V nominal Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Ground pin for the REF outputs. Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. IDTTM PC MAIN CLOCK 1484B—01/21/10 3 ICS9LPRS525 PC MAIN CLOCK General Description ICS9LPRS525 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LPRS525 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram X1 X2 REF REF CPU(1:0) OSC SRC8/ITP CPU CPU PLL1 SS SRC SRC_MAIN SRC(7:3) PCI33MHz SRC PCI(5:0) PCI33MHz PLL3 SS SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:F) SRC5_EN ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC1/SE(2:1) Control Logic Differential Output SE Outputs 7 SATA SRC0/DOT96 PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD GND 41, 47 44 16 15 26, 31, 37 20 12 9 53 2 IDTTM PC MAIN CLOCK Description CPUCLK Master Clock, Analog SRCCLK PLL3/SE DOT 96Mhz USB 48 Xtal, REF PCICLK 1484B—01/21/10 23, 34 19 11 11 50 8 4 ICS9LPRS525 PC MAIN CLOCK Absolute Maximum Ratings - DC Parameters PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection 1 2 3 SYMBOL VDDxxx VDDxxx_IO V IH V IL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V Inputs Any Input Human Body Model MIN MAX 4.6 3.8 4.6 150 GND - 0.5 -65 2000 UNITS V V V V ° C V Notes 7 7 4,5,7 4,7 4,7 6,7 Guaranteed by design and characterization, not 100% tested in production. O peration under these conditions is neither implied, nor guaranteed. M aximum input voltage is not to exceed VDD Electrical C haracteristics - Input/S upply/C ommon Output D C Parameters P ARAME TE R A m bient Operating Tem p S upply V oltage S upply V oltage Input High V oltage Input Low V oltage Low Threshold Input- High V oltage Low Thres hold Input- FS C = '1' V olta g e Low Threshold Input- FS A ,FSB = '1' V olta g e Low Threshold Input-Low V oltage P CI3/CFG0 Input P CI3/CFG0 Input P CI3/CFG0 Input Input Leakage Current Input Leakage Current Output High V oltage Output Low V oltage Operating S upply Current iA M T M ode Current P owerdown Current Input Frequency P in Inductanc e Input Capac itanc e S Y MBOL Tam bient V DDxx x V DDxx x_IO V IHSE V I LSE V I H_FS_TEST V I H_FS_FSC V I H_FS_FSAB V I L_FS V IL_CFGHI V I L_CFGMI D V I L_CFGLO I IN I INRES V OHSE V OLSE I DDOP3.3 I DDOPI O I DDiAMT3.3 I DDiAMTIO I DDPD3.3 I DDPDI O Fi L p in CI N C OUT C I NX T STAB T DRCROFF T DRCRON T DRSRC T FALL T RI SE V DD V OLSMB I PULLUP T RI 2C T FI 2C F SMBUS f SSMOD Triangular Modulation 30 CONDITIONS S upply V oltage Low-V oltage Differential I/O S upply S ingle-ended 3.3V inputs S ingle-ended 3.3V inputs 3.3 V + /-5% 3.3 V + /-5% 3.3 V + /-5% 3.3 V + /-5% Optional input, 2.75V typ. Optional input, 1.65V typ. Optional input, 0.55V typ. V I N = V DD , V I N = G ND Inputs with pull up or pull down res is tors V I N = V DD , V I N = G ND S ingle-ended outputs, I OH = -1m A S ingle-ended outputs, I OL = 1 m A Full A c tiv e, C L = F ull load; Idd 3.3V Full A ctive, C L = F ull load; IDD IO M 1 mode, 3.3V Rail M1 Mode, IO Rail P ower down mode, 3.3V Rail P ower down m ode, IO Rail V DD = 3 .3 V Logic Inputs Output pin c apac itanc e X 1 & X2 pins From VDD P ower-Up or de-ass ertion of PD to 1st c loc k Output stop after CR deass erted Output run after CR as serted CP U output enable after P CI_S TOP # de-as sertion Fall/rise time of all 3.3V c ontrol inputs from 20-80% 2.7 @ I PULLUP S M B Data P in (Max V IL - 0.15) to (M in V IH + 0.15) (Min V IH + 0.15) to (Max V IL - 0.15) 4 1000 300 100 33 MIN 0 3.135 0.9975 2 V SS - 0 .3 2 0.7 0.7 V SS - 0 .3 2.4 1.3 V SS - 0 .3 -5 -200 2.4 0.4 115 55 36 10 5 0.1 15 7 5 6 6 1.8 400 0 10 10 10 5.5 0.4 MAX UNITS 70 °C 3.465 V 3.465 V V DD + 0 .3 V 0.8 V V DD + 0.3 V 1.5 V DD+0.3 0.35 V DD+0.3 2 0.9 5 200 V V V V V V uA uA V V mA mA mA mA mA mA MHz nH pF pF pF ms ns us ns ns ns V V mA ns ns k Hz k Hz 1 1 10 Notes 10 3 3 8 8 9, 10 9, 10 9, 10 2 10 1.5 Clk S tabiliz ation Tdrive_CR_off Tdrive_CR_on Tdriv e_CPU Tfall_S E Tris e_S E S M B us Voltage Low-lev el Output V oltage Current sinking at V OLSMB = 0 .4 V S CLK /S DA TA Cloc k/Data Ris e Time S CLK /S DA TA Clock /Data Fall Time M ax im um S M B us Operating Frequenc y S pread Spec trum M odulation Frequenc y IDTTM PC MAIN CLOCK 1484B—01/21/10 5 ICS9LPRS525 PC MAIN CLOCK NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 2 3 4 5 6 7 8 9 Signal is required to be monotonic in this region. input leakage current does not include inputs with pull-up or pull-down resistors 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. Intentionally blank M aximum VIH is not to exceed VDD H uman Body Model O peration under these conditions is neither implied, nor guaranteed. F requency Select pins which have tri-level input PCI3/CFG0 is optional If present. Not all parts have this feature. 10 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew 1 2 3 4 5 6 7 8 9 SYMBOL tSLR tFLR tSLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Differential Measurement Differential Measurement Differential Measurement MIN 2.5 2.5 300 300 MAX 4 4 20 550 140 1150 55 100 150 3000 -300 45 UNITS NOTES V/ns 2, 3 V/ns 2, 3 % 1, 10 mV 2 mV 1,4,5 mV 1,4,9 mV 1,7 mV 1,8 % 2 ps 1 ps 1 ps 1,6 NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Measurement taken for single ended waveform on a component test board (not in system) M easurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) O nly applies to the differential rising edge (Clock rising, Clock# falling) T otal distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps. T he max voltage including overshoot. T he min voltage including undershoot. T he total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute 10 M atching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage Clock Jitter Specs - Low Power Differential Outputs PARAMETER CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle 1 SYMBOL CPUJC2C SRCJC2C DOTJC2C CONDITIONS Differential Measurement Differential Measurement Differential Measurement MIN MAX 85 125 250 UNITS NOTES ps 1 ps 1 ps 1 NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver IDTTM PC MAIN CLOCK 1484B—01/21/10 6 ICS9LPRS525 PC MAIN CLOCK Differential Clock Tolerances PPM tolerance Cycle to Cycle Jitter Spread CPU 100 85 -0.50% SRC 100 125 -0.50% DOT96 100 250 0 BMC133 100 125 -0.50% ppm ps % Clock Periods - Differential Outputs with Spread Spectrum Disabled Center Freq. MHz 100.00 133.33 166.67 200.00 266.67 333.33 400.00 100.00 96.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term Period AbsPer Average Average Average Min Nominal Max Min Min 9.91400 9.99900 10.00000 10.00100 7.41425 7.49925 7.50000 7.50075 5.91440 5.99940 6.00000 6.00060 4.91450 4.99950 5.00000 5.00050 3.66462 3.74962 3.75000 3.75037 2.91470 2.99970 3.00000 3.00030 2.41475 2.49975 2.50000 2.50025 9.87400 9.99900 10.00000 10.00100 10.16563 10.41563 10.41667 10.41771 1 Clock 1us +SSC Short-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.08600 7.58575 6.08560 5.08550 3.83537 3.08530 2.58525 10.12600 10.66771 ns ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 SSC OFF CPU SRC/SATA DOT96 Clock Periods - Differential Outputs with Spread Spectrum Enabled Center Freq. MHz 99.75 133.00 166.25 199.50 266.00 332.50 399.00 99.75 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm -c2c jitter 0 ppm Short-Term Long-Term Long-Term AbsPer Period Average Average Average Min Nominal Min Min Max 9.91406 9.99906 10.02406 10.02506 10.02607 7.41430 7.49930 7.51805 7.51880 7.51955 5.91444 5.99944 6.01444 6.01504 6.01564 4.91453 4.99953 5.01203 5.01253 5.01303 3.66465 3.74965 3.75902 3.75940 3.75977 2.91472 2.99972 3.00722 3.00752 3.00782 2.41477 2.49977 2.50602 2.50627 2.50652 9.87406 9.99906 10.02406 10.02506 10.02607 1 Clock 1us +SSC Short-Term Average Max 10.05107 7.53830 6.03064 5.02553 3.76915 3.01532 2.51277 10.05107 1 Clock +c2c jitter Units Notes AbsPer Max 10.13607 7.62330 6.11564 5.11053 3.85415 3.10032 2.59777 10.17607 ns ns ns ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 SSC ON CPU SRC 1 2 Guaranteed by design and characterization, not 100% tested in production. A ll Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz. IDTTM PC MAIN CLOCK 1484B—01/21/10 7 ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs V OH V OL I OH I OL t SLR t FLR tskew tskew dt1 t jcy c-cy c CONDITIONS see Tperiod min-max values 33.33MHz output no spread 33.33MHz output spread 33.33MHz output no spread 33.33MHz output nominal/spread I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN -100 29.99700 30.08421 29.49700 29.56617 2.4 -33 30 1 1 100 45 MAX UNITS NOTES 100 ppm 1,2 30.00300 ns 2 30.23459 ns 2 30.50300 ns 2 30.58421 ns 2 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 4 V/ns 1 4 V/ns 1 250 ps 2 200 ps 2 55 % 2 500 ps 2 Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs THIGH TLOW V OH V OL I OH I OL t SLR t FLR dt1 t jcy c-cy c CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal MIN -100 20.83125 20.48125 8.216563 7.816563 2.4 -29 29 1 1 45 MAX UNITS NOTES 100 ppm 2,4 20.83542 ns 2,3 21.18542 ns 2 11.15198 V 10.95198 V V 0.55 V mA -23 mA mA 27 mA 2 V/ns 1 2 V/ns 1 55 % 2 350 ps 2 I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V IDTTM PC MAIN CLOCK 1484B—01/21/10 8 ICS9LPRS525 PC MAIN CLOCK Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle 1 2 3 4 SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V MIN -100 69.82033 69.83400 29.97543 29.57543 2.4 -33 30 1 1 45 MAX UNITS Notes 100 ppm 2, 4 69.86224 ns 2, 3 70.84800 ns 2 38.46654 V 38.26654 V V 0.4 V -33 38 4 4 55 1000 mA mA V/ns V/ns % ps 1 1 2 2 NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Edge rate in system is measured from 0.8V to 2.0V. Duty cycle, Peroid and Jitter are measured with respect to 1.5V The average period over any 1us period of time Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz IDTTM PC MAIN CLOCK 1484B—01/21/10 9 ICS9LPRS525 PC MAIN CLOCK Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 FSLB B0b6 0 0 1 1 0 0 1 1 1 FSLA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB DOT MHz MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6) Spread Pin 17 Pin 18 B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A % Comment PLL 3 disabled 0.5% Down Spread SRC clocks from SRC_MAIN 0.5% Down Spread Only SRCCLK1 from PLL3 1% Down Spread Only SRCCLK1 from PLL3 1.5% Down Spread Only SRCCLK1 from PLL3 2% Down Spread Only SRCCLK1 from PLL3 2.5% Down Spread Only SRCCLK1 from PLL3 N/A N/A None 24.576Mhz on SE1 and SE2 None 24.576Mhz on SE1, 98.304Mhz on SE2 None 98.304Mhz on SE1 and SE2 None 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A N/A IDTTM PC MAIN CLOCK 1484B—01/21/10 10 ICS9LPRS525 PC MAIN CLOCK Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V Table 4: Device ID table B8b7 0 B8b6 0 B8b5 0 B8b4 0 Comment 56 pin TSSOP Table 5: Slew Rate Selection Table Bit 1 0 0 1 1 Bit 0 0 1 0 1 Slew Rate HI-Z 0.7X (1.4V/ns) 0.8X (1.6 V/ns) 1X (2.0 V/ns) Table 6. PCI3 Configuration Table Note: 2 bits are needed since CFG0 is tri-level input SRC_Main_SE PCI3/CFG0 PCI2/TME PCI3_CFG1 PCI3_CFG0 L HW Strap HW Strap (By te 11, bit 7) (By te 11, bit 6) (By te 0, bit 2) Config Mode Low 0 or 1 0 0 0 0 = Default Mid 0 or 1 0 1 1 1 High TME=0 1 0 1 2 High TME=1 1 1 1 3 Table 7. PLL Modes for PCI3 Configurations PLL1 PLL2 Config Mode Outputs SSC Outputs PLL3 Outputs SSC SSC CPU/SRC/ 0 = Default PCI Down USB NA 1 CPU Down USB NA 2 CPU Center USB NA 3 CPU Center USB/LAN25 NA *Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18 SRC/PCI SRC/PCI SRC/PCI Down Down Down PLL Source PLL1 (Table 2 applies) 100MHz 100MHz PLL3 100MHz PLL3 25MHz SE PLL2* SRC1 Table 8. ME Clock Selection Table PCIF5/ ITP_EN iAMT_EN CPU2_AMT_EN CPU1_AMT_EN Description x 1 0 0 Reserved x 1 0 1 Default, CPU1 = iAMT Clock 1 1 1 0 CPU2 = iAMT Clock 1 1 1 1 CPU1 and CPU2 both run in iAMT mode IDTTM PC MAIN CLOCK 1484B—01/21/10 11 ICS9LPRS525 PC MAIN CLOCK PCI_STOP# Power Management Differential Clocks (Except CPU) Stoppable Free running Stoppable Free running Running Running Running Running CK= High Running CK# = Low Low Low CK= Pull down Running CK# = Low Low CK= Pull down, CK# = Low Single-ended Clocks SMBus OE Bit PCI_STOP# 1 0 X Enable Disable CPU_STOP# Power Management SMBus OE Bit PCI_STOP# 1 Enable 0 Disable CR# Power Management SMBus OE Bi t Enable Disable CR# 1 0 X Differential Clocks Stoppable Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low Differential Clocks Stoppable Free running Running CK= High CK# = Low CK= Pull down CK# = Low Low Running Running Running X PD# Power Management Single-ended Clocks Device State Latches Open Power Down Low M1 Virtual Power Cycle to Latches Open Hi-Z w/o Latched input w/Latched input CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CK= Pull down, CK# = Low CK= Pull down CK# = Low Running CK= Pull down, CK# = Low Differential Clocks (Except CPU1) CPU1 IDTTM PC MAIN CLOCK 1484B—01/21/10 12 ICS9LPRS525 PC MAIN CLOCK General SMBus serial interface information for the ICS9LPRS525 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK Byte N + X - 1 N P Not acknowledge stoP bit IDTTM PC MAIN CLOCK 1484B—01/21/10 13 ICS9LPRS525 PC MAIN CLOCK Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 4 3 2 1 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL Description Type 0 1 Default CPU Freq. Sel. Bit (Most Significant) Latch R See Table 1 : CPU Frequency Select CPU Freq. Sel. Bit Latch R Table Latch CPU Freq. Sel. Bit (Least Significant) R Set via SMBus or dynamically by CK505 if detects RW Legacy Mode iAMT Enabled 0 dynamic M1 Reserved RW 0 Select source for SRC Main Select source for SATA clock RW SRC Main = PLL1 SRC Main = PLL3 Latch RW SATA = SRC_Main SATA = PLL2 0 0 - PD_Restore 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold powerConfiguration Not RW on and go to latches open state Saved This bit is ignored and treated at '1' if device is in iAMT mode. Configuration Saved 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 Name SRC0_SEL PLL1_SSC_SEL PLL3_SSC_SEL PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Select 0.5% down or center SSC PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW 0 SRC0 Down spread Down spread 1 DOT96 Center spread Center spread Default 0 Latch 0 0 0 0 1 1 See Table 2: PLL3 Quick Configuration Only applies if Byte 0, bit 2 = 0. PCI from PLL1 PCI from SRC_MAIN Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE Description Output enable for REF, if disabled output is tristated Output enable for USB Output enable for PCI5 Output enable for PCI4 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Output enable for PCI0 Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Output Output Output Output Output Output Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved SRC8/ITP_OE SRC7_OE SRC6_OE SRC5_OE SRC4_OE Description Reserved Reserved Reserved Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW 0 Disabled Disabled Disabled Disabled Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Default 1 1 1 1 1 1 1 1 Output Output Output Output Output IDTTM PC MAIN CLOCK 1484B—01/21/10 14 ICS9LPRS525 PC MAIN CLOCK Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 Byte 5 Clock Request Enable/Configuration Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Enable CR#_B (clk req) Sets CR#_B -> SRC1 or SRC4 Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_D CR#_D -> SRC1 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Default 0 0 0 0 0 0 0 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 1 Pin Name CR#_E_EN CR#_F_EN Reserved Reserved Reserved Reserved SSCD_STP_CRTL (SRC1) SRC_STP_CRTL Description Enable CR#_E (clk req) -> SRC6 Enable CR#_F (clk req) -> SRC8 Reserved Reserved Reserved Reserved If set, SSCD (SRC1) stops with PCI_STOP# Type RW RW RW RW RW RW RW 0 Disable CR#_E Disable CR#_F Free Running 1 Enable CR#_E Enable CR#_F Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Default 0 0 0 0 0 0 0 0 If set, SRCs (except SRC1) stop with PCI_STOP# RW Free Running 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Vendor specific Vendor ID ICS is 0001, binary IDTTM PC MAIN CLOCK 1484B—01/21/10 15 ICS9LPRS525 PC MAIN CLOCK Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Output enable for SE2 Type R R R R RW RW RW RW 0 56-pin device Disabled Disabled Enabled Enabled 1 Default 0 0 0 0 0 0 0 0 Byte 9 Output Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback REF Strength Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 1 Default Stops with Free running PCI_STOP# 0 assertion normal operation no overclocking Latch 1X (2Loads) 2X (3 Loads) 1 Outputs HI-Z Outputs = REF/N 0 Normal operation Test mode 0 1 0 1 0 See Table 3: V_IO Selection (Default is 0.8V) Byte 10 Stop Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled Free Running Free Running 1 SRC5 Enabled Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 iAMT Enable Register Bit 7 6 5 4 3 2 1 Pin Name PCI3_CFG1 PCI3_CFG0 Reserved Reserved CPU2_AMT_EN CPU1_AMT_EN PCI-E_GEN2 Description See PCI3 Configuration Table 28 Reserved Reserved Determines if CPU2 runs in M1 mode. Only valid if ITP_EN=1. See Note. Determines if CPU1 runs in M1 mode. See Note. Determines if PCI-E Gen2 compliant Type R R RW RW RW RW R 0 1 See PCI3 Configuration Table Does not Run Does not Run non-Gen2 Free Running Runs Runs PCI-E Gen2 Compliant Stoppable Default Latch Latch 0 1 0 1 1 1 0 CPU 2 Stop Enable Enables control of CPU 0 with CPU_STOP# RW NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration. IDTTM PC MAIN CLOCK 1484B—01/21/10 16 ICS9LPRS525 PC MAIN CLOCK Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Read Back byte count register, max bytes = 32 Byte 13 to 28 Reserved Byte 29 Slew Rate Control Bit 7 6 5 4 3 2 1 0 Pin Name USB_Slew1 USB_Slew0 PCI_Slew1 PCI_Slew0 Reserved REF Slew Rate Reserved Reserved Description USB Slew Rate Control (MSB) USB Slew Rate Control (LSB) PCI Slew Rate Control (MSB) PCI Slew Rate Control (LSB) Changes Ref Slew Rate RW RW RW RW RW RW RW RW RW 0 1 See Slew Rate Selection Table See Slew Rate Selection Table 1.2V/ns 2.2V/ns Default 1 0 1 1 1 1 0 0 IDTTM PC MAIN CLOCK 1484B—01/21/10 17 ICS9LPRS525 PC MAIN CLOCK Test Clarification Table Comments FSLC/ TEST_SEL HW PIN HW SW REF/N or HI-Z B9b4 FSLB/ TEST TEST_MODE ENTRY BIT HW PIN B9b3 Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N