9LPRS535BGLF

Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential outputs Output Features: • Integrated Series Resistors on differential outputs • 2 - CPU differential push-pull pairs • 4 - SRC differential push-pull pairs • 1 - CPU/SRC selectable differential push-pull pair • 1 - SRC/DOT selectable differential push-pull pair • 1- SRC/Stop_Inputs selectable differential push-pull pair • 1 - 25MHz SE1 output for Wake-on-Lan applications • 3 - PCI, 33MHz • 1 - USB, 48MHz • 1 - REF, 14.31818MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/-100ppm frequency accuracy on all clocks Pin Configuration Features/Benefits: • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Table 1: CPU Frequency Select Table FSLC B0b7 0 0 0 0 1 1 1 1 2 FSLB B0b6 0 0 1 1 0 0 1 1 1 FS LA B0b5 0 1 0 1 0 1 0 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. PCI0/CR#_A VDDPCI PCI4/SRC5_EN PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR DOT96C_LPR/SRCC0_LPR GND VDD SE1 GND SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR GNDSRC SRCT3_LPR/CR#_C SRCC3_LPR/CR#_D VDDSRC_IO SRCT4_LPR SRCC4_LPR CPU_STOP#/SRCC5_LPR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0_LPR CPUC0_LPR GNDCPU CPUT1_LPR_F CPUC1_LPR_F VDDCPU_IO CPUT2_ITP_LPR/SRCT8_LPR CPUC2_ITP_LPR/SRCC8_LPR VDDSRC_IO SRCT7_LPR/CR#_F SRCC7_LPR/CR#_E GNDSRC VDDSRC PCI_STOP#/SRCT5_LPR 48-SSOP/TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 1461A—07/28/09 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. 9LPRS535 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet SSOP/TSSOP Pin Description PIN # 1 2 3 PIN NAME PCI0/CR#_A VDDPCI PCI4/SRC5_EN TYPE DESCRIPTION 4 5 6 7 8 9 10 PCI_F5/ITP_EN GNDPCI VDD48 USB_48MHz/FSLA GND48 VDD96_IO DOT96T_LPR/SRCT0_LPR 3.3V PCI clock output or CR#_A input. Default is PCI0. To configure this pin as CR#_A, the PCI output must first be disabled in Byte 2, bit 0. I/O Byte 5, bit 7: 0 = PCI0 enabled (default), 1= CR#_A enabled. Byte 5, bit 6: 0 = CR#_A controls SRC0 (default), 1= CR#_A# controls SRC2. PWR Power supply for PCI clocks, nominal 3.3V 3.3V PCI clock output / SRC5 enable strap. On powerup, the logic value on this pin determines if SRC5 or CPU_STOP#/PCI_STOP# is enabled. The latched value controls the pin function as follows I/O 0 = PCI_STOP#/CPU_STOP# 1 = SRC5/SRC5# Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. I/O 0 =SRC8/SRC8# 1 = ITP/ITP# PWR Ground pin for the PCI outputs PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed I/O 48MHz USB clock output. 3.3V. PWR Ground pin for the 48MHz outputs PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V. True clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRCT0. After powerup, this pin function may be changed to DOT96T via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0T 1=DOT96T Complementary clock of push-pull SRC or DOT96 with integrated series resistor. No 50 ohm pull down needed. Default is SRC0C. After powerup, this pin function may be changed to DOT96C via SMBus Byte 1, bit 7 as follows: OUT 0= SRC0C 1=DOT96C PWR Ground pin. PWR Power supply, nominal 3.3V OUT CK505 Singled Ended Output 1. 3.3V. PWR Ground pin. True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND OUT needed. Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor OUT to GND needed. PWR Ground pin for the SRC outputs True clock of push-pull SRC output with int. 33ohm series resistor/CR#_C input. Disable SRC3 via Byte 4, bit 7, before using as CR#_C. I/O Byte 5, bit 3: 0=SRC3 (default), 1=CR#_C. Byte 5, bit 2: 0=CR# C controls SRC0 (default), 1=CR# C controls SRC2 Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_D input. Disable SRC3 via Byte 4, bit 7, before using as CR#_D. I/O Byte 5, bit 1: 0=SRC3 (default),1=CR#_D. Byte 5, bit 0: 0=CR#_D controls N/A (default), 1=CR#_D controls SRC4 PWR 1.05V to 3.3V from external power supply OUT True clock of push-pull SRC output with int. 33ohm series resistor. OUT Complementary clock of push-pull SRC output with int. 33ohm series resistor. I/O Stops all CPUCLK, except those set to be free running clocks / Complementary clock of push-pull SRC pair with int. 33ohm series resistor. 11 12 13 14 15 16 17 18 19 DOT96C_LPR/SRCC0_LPR GND VDD SE1 GND SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR GNDSRC SRCT3_LPR/CR#_C 20 21 22 23 24 SRCC3_LPR/CR#_D VDDSRC_IO SRCT4_LPR SRCC4_LPR CPU_STOP#/SRCC5_LPR 1461A—07/28/09 2 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet SSOP/TSSOP Pin Description (Continued) 25 26 27 28 PCI_STOP#/SRCT5_LPR VDDSRC GNDSRC I/O Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this input. / True clock of push-pull SRC pair with int. 33ohm series resistor. PWR Supply for SRC clocks, 3.3V nominal 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PWR Ground pin for the SRC outputs Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3 before using as CR#_E. SRCC7_LPR/CR#_E I/O Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E Outputs controlled by CR#_E are not present on this device True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before SRCT7_LPR/CR#_F I/O using CR#_F. Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8. VDDSRC_IO PWR 1.05V to 3.3V from external power supply Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: CPUC2_ITP_LPR/SRCC8_LPR OUT Pin 7 latched input Value 0 = SRC8# 1 = ITP# True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows: CPUT2_ITP_LPR/SRCT8_LPR OUT Pin 7 latched input Value 0 = SRC8 1 = ITP VDDCPU_IO PWR 1.05V to 3.3V from external power supply Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running CPUC1_LPR_F OUT during iAMT. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during CPUT1_LPR_F OUT iAMT No 50 ohm resistor to GND needed. GNDCPU PWR Ground pin for the CPU outputs Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm CPUC0_LPR OUT resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to CPUT0_LPR OUT GND needed. VDDCPU CK_PWRGD/PD# FSLB/TEST_MODE GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK PWR Supply for CPU clocks, 3.3V nominal Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. PWR Ground pin for the REF outputs. OUT Crystal output, Nominally 14.318MHz IN Crystal input, Nominally 14.318MHz. PWR Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for I/O Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table I/O Data pin for SMBus circuitry, 3.3V tolerant. IN Clock pin of SMBus circuitry, 5V tolerant. IN 1461A—07/28/09 3 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet General Description ICS9LPRS535 is compliant to the Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop chipsets. ICS9LPRS535 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram X1 X2 OSC REF REF CPU(1:0) SRC8/ITP CPU PLL1 SS CPU SRC = SRC_MAIN SRC(7,5:3) PCI33MHz PCI(5:4,0) PLL3 Non-SS SE1 (25MHz) 25MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A,C:D) SRC5_EN ITP_EN FSLC/TESTSEL FSLB/TESTMODE SRC0/DOT96 Control Logic SATA PLL2 Non-SS DOT96MHz 48MHz 48MHz Power Groups Pin Number VDD 33 39 30, 21 13 9 6 45 2 1461A—07/28/09 Description GND 36 36 18, 27 15 12 8 42 5 CPU Outputs CPU/SRC Analog SRC Outputs PLL3 25MHz DOT96 outputs USB 48 Output/Analog Xtal, REF PCI outputs 4 Integrated Circuit Systems, Inc. Absolute Maximum Ratings - DC Parameters PARAMETER Maximum Supply Voltage Maximum Supply Voltage Maximum Input Voltage Minimum Input Voltage Storage Temperature Input ESD protection 1 2 3 ICS9LPRS535 Datasheet SYMBOL VDDxxx VDDxxx_IO VIH VIL Ts ESD prot CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply 3.3V Inputs Any Input Human Body Model MIN MAX 4.6 3.8 4.6 150 GND - 0.5 -65 2000 UNITS Notes V 7 V 7 V 4,5,7 V 4,7 ° 4,7 C V 6,7 Guaranteed by design and characterization, not 100% tested in production. O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed VDD AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Differential Voltage Swing Crossing Point Voltage Crossing Point Variation Maximum Output Voltage Minimum Output Voltage Duty Cycle CPU[1:0] Skew CPU[2_ITP:0] Skew SRC[10:0] Skew SYMBOL tSLR tFLR tSLVAR VSWING VXABS VXABSVAR VHIGH VLOW DCYC CPUSKEW10 CPUSKEW20 SRCSKEW CONDITIONS Averaging on Averaging on Averaging on Averaging off Averaging off Averaging off Averaging off Averaging off Averaging on Differential Measurement Differential Measurement Differential Measurement MIN 2.5 2.5 300 300 MAX 4 4 20 550 140 1150 55 100 150 3000 UNITS NOTES V/ns 2, 3 V/ns 2, 3 % 1, 10 mV 2 mV 1,4,5 mV 1,4,9 mV 1,7 mV 1,8 % 2 ps 1 ps 1 ps 1,6,11 -300 45 NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 2 3 4 5 6 7 8 9 Measurement taken for single ended waveform on a component test board (not in system) Measurement taken from differential waveform on a component test board. (not in system) Slew rate emastured through V_swing voltage range centered about differential zero Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system) O nly applies to the differential rising edge (Clock rising, Clock# falling) Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps. The max voltage including overshoot. The min voltage including undershoot. The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew. 10 11 Electrical Characteristics - PCICLK/PCICLK_F PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Pin to Pin Skew Intential PCI to PCI delay Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs VOH VOL I OH I OL t SLR t FLR tskew tskew dt1 tjc y c-c y c CONDITIONS see Tperiod min-max values 33.33MHz output no spread 33.33MHz output spread 33.33MHz output no spread 33.33MHz output nominal/spread IOH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN -100 29.99700 30.08421 29.49700 29.56617 2.4 -33 30 1 1 100 45 MAX UNITS NOTES 100 ppm 1,2 30.00300 ns 2 30.23459 ns 2 30.50300 ns 2 30.58421 ns 2 V 1 0.55 V 1 mA 1 -33 mA 1 mA 1 38 mA 1 4 V/ns 1 4 V/ns 1 250 ps 2 200 ps 2 55 % 2 500 ps 2 1461A—07/28/09 5 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Electrical Characteristics - Input/Supply/Common Output DC Parameters PARAMETER Ambient Operating Temp Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Low Threshold Input- High Voltage Low Threshold Input- FSC = '1' Voltage Low Threshold Input- FSA,FSB = '1' Voltage Low Threshold Input-Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Operating Supply Current iAMT Mode Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization Tdrive_CR_off Tdrive_CR_on Tdrive_CPU Tfall_SE Trise_SE SMBus Voltage Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency Spread Spectrum Modulation Frequency SYMBOL Tambient VDDxxx VDDxxx_IO VIHSE VILSE VIH_FS_TEST VIH_FS_FSC VIH_FS_FSAB VIL_FS IIN IINRES VOHSE VOLSE IDDOP3.3 IDDOPIO IDDiAMT3.3 IDDiAMTIO IDDPD3.3 IDDPDIO Fi Lpin CIN COUT CINX TSTAB TDRCROFF TDRCRON TDRSRC TFALL TRISE VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS fSSMOD Triangular Modulation 30 CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended 3.3V inputs Single-ended 3.3V inputs 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% VIN = VDD , VIN = GND Inputs with pull up or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Full Active, CL = Full load; Idd 3.3V Full Active, CL = Full load; IDD IO M1 mode, 3.3V Rail M1 Mode, IO Rail Power down mode, 3.3V Rail Power down mode, IO Rail VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock Output stop after CR deasserted Output run after CR asserted CPU output enable after PCI_STOP# de-assertion Fall/rise time of all 3.3V control inputs from 20-80% 2.7 @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) 4 1000 300 100 33 MIN 0 3.135 0.9975 2 VSS - 0.3 2 0.7 0.7 VSS - 0.3 -5 -200 2.4 0.4 125 50 40 10 5 0.1 15 7 5 6 6 1.8 400 0 10 10 10 5.5 0.4 MAX UNITS Notes 70 °C 3.465 V 3.465 V 10 VDD + 0.3 V 3 0.8 V 3 VDD + 0.3 V 8 1.5 VDD+0.3 0.35 5 200 V V V uA uA V V mA mA mA mA mA mA MHz nH pF pF pF ms ns us ns ns ns V V mA ns ns kHz kHz 1 1 10 2 8 10 1.5 NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). 1 2 3 4 5 6 7 8 9 Signal is required to be monotonic in this region. input leakage current does not include inputs with pull-up or pull-down resistors 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected. Intentionally blank Maximum VIH is not to exceed VDD Human Body Model Operation under these conditions is neither implied, nor guaranteed. Frequency Select pins which have tri-level input PCI3/CFG0 is optional If present. Not all parts have this feature. 10 1461A—07/28/09 6 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Electrical Characteristics - USB48MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cycle to cycle SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL I OH I OL tSLR tFLR dt1 tjc y c-c y c CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal MIN -100 20.83125 20.48125 8.216563 7.816563 2.4 -29 29 1 1 45 MAX UNITS NOTES 100 ppm 2,4 20.83542 ns 2,3 21.18542 ns 2 11.15198 V 10.95198 V V 0.55 V mA -23 mA mA 27 mA 2 V/ns 1 2 V/ns 1 55 % 2 350 ps 2 I OH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period CLK High Time CLK Low time Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter, Cy cle to c y cle 1 2 3 4 SYMBOL ppm Tperiod Tabs THIGH TLOW VOH VOL IOH IOL tSLR tFLR dt1 tjc y c-c y c CONDITIONS see Tperiod min-max values 14.318MHz output nominal 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V MIN -100 69.82033 69.83400 29.97543 29.57543 2.4 -33 30 1 1 45 MAX UNITS Notes 100 ppm 2, 4 69.86224 ns 2, 3 70.84800 ns 2 38.46654 V 38.26654 V V 0.4 V -33 38 4 4 55 1000 mA mA V/ns V/ns % ps 1 1 2 2 NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). Edge rate in system is measured from 0.8V to 2.0V. Duty cycle, Peroid and Jitter are measured with respect to 1.5V The average period over any 1us period of time Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz Clock Jitter Specs - Low Power Differential Outputs PARAMETER CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle 1 SYMBOL CPUJC2C SRCJC2C DOTJC2C CONDITIONS Differential Measurement Differential Measurement Differential Measurement MIN MAX 85 125 250 UNITS NOTES ps 1 ps 1,2 ps 1 NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production). JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement methodology is as defined by the PCI SIG. 2 1461A—07/28/09 7 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Table 2: PLL3 Quick Confi guration (Read Onl y) Pin 14 Spread B1b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B1b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MHz N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 25.000 N/A N/A N/A Comment % N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A None 25Mhz on SE1 N/A N/A N/A N/A N/A N/A Table 3: Vswing Select Table B9b2 B9b1 B9b0 Vswing 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V Table 4: Device ID table B8b7 0 B8b6 1 B8b5 1 B8b4 0 Comment 48 SSOP/TSSOP 1461A—07/28/09 8 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet PCI_STOP# Power Management Single-ended Clocks SMBus OE Bit Enable Disable PCI_STOP# 1 0 X Stoppable Running Low Low Free running Running Running Differential Clocks (Except CPU) Stoppable Free running Running Running CK= High Running CK# = Low CK= Pull down, CK# = Low CPU_STOP# Power Management SMBus OE Bit Enable 0 Disable CR# Power Management Differential Clocks (Except CPU) CR# controlled Free running Running Running CK= Pull down, CK# = Low CK = Pull down, CK# = Low X CPU_STOP# 1 CPU Clocks Free running Stoppable Running CK= High CK# = Low Low Running Running SMBus OE Bit Enable Disable PD# Power Management CR# 1 0 X Device State Latches Open Power Down Single-ended Clocks (Except SE1) w/o Latched input w/Latched input SE1 w/B11b5 = 0 SE1 w/B11b5 = 1 Low 25MHz Differential Clocks (Except CPU1) CK= Pull down, CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down, CK# = Low CPU1 CK= Pull down, CK# = Low CK= Pull down CK# = Low Running CK= Pull down, CK# = Low Low M1 Virtual Power Cycle to Latches Open Hi-Z Low 25MHz 25MHz 1461A—07/28/09 9 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet General SMBus serial interface information for the ICS9LPRS535 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK Byte N + X - 1 N P Not acknowledge stoP bit 1461A—07/28/09 10 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 4 3 2 1 Pin Name FSLC FSLB FSLA iAMT_EN Reserved SRC_Main_SEL SATA_SEL Description CPU Freq. Sel. Bit (Most Significant) CPU Freq. Sel. Bit CPU Freq. Sel. Bit (Least Significant) Set via SMBus or dynamically by CK505 if detects dynamic M1 Reserved Select source for SRC Main Select source for SATA clock 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold power-on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. Type R R R RW 0 1 See Table 1 : CPU Frequency Select Table Legacy Mode iAMT Enabled SRC Main = PLL3 SATA = PLL2 Default Latch Latch Latch 0 0 0 0 RW SRC Main = PLL1 R RW SATA = SRC_Main 0 - PD_Restore RW Configuration Not Saved Configuration Saved 1 Byte 1 DOT96 Select and PLL3 Quick Config Register Bit 7 6 5 4 3 2 1 0 Pin 13/14 Name SRC0_SEL PLL1_SSC_SEL Reserved PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Reserved PLL3 Quick PLL3 Quick PLL3 Quick PLL3 Quick Config Bit Config Bit Config Bit Config B it 3 2 1 0 Type RW RW RW R R R R R 0 SRC0 Down spread 1 DOT96 Center spread Default 0 0 1 1 1 0 0 1 25MHz from PLL3 Quick Config PCI from SRC_MAIN PCI_SEL P CI from PLL1 Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_OE USB_OE PCIF5_OE PCI4_OE Reserved Reserved Reserved PCI0_OE Description Output enable for REF, if disabled output is tri-stated Output enable for USB Output enable for PCI5 Output enable for PCI4 Reserved Reserved Reserved Output enable for PCI0 Type RW RW RW RW RW RW RW RW Output Output Output Output 0 Disabled Disabled Disabled Disabled Output Output Output Output 1 Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Output Disabled Output Enabled Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved SRC8/ITP_OE SRC7_OE Reserved SRC5_OE SRC4_OE Description Reserved Reserved Reserved Output enable for SRC8 or ITP Output enable for SRC7 Reserved Output enable for SRC5 Output enable for SRC4 Type RW RW RW RW RW RW RW RW 0 1 Default 1 1 1 1 1 1 1 1 Output Disabled Output Disabled Output Disabled Output Disabled Output Enabled Output Enabled Output Enabled Output Enabled 1461A—07/28/09 11 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE Reserved SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON Reserved Description Output enable for SRC3 Output enable for SATA/SRC2 Reserved Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Reserved Type RW RW RW RW RW RW RW RW 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Default 1 1 0 1 1 1 1 0 Byte 5 Clock Request Enable/Configuration Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL Reserved Reserved CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL Description Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect Sets CR#_A to control either SRC0 or SRC2 Reserved Reserved Enable CR#_C (clk req) Sets CR#_C -> SRC0 or SRC2 Enable CR#_D (clk req) Sets CR#_D -> SRC1 or SRC4 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 1 Enable CR#_A CR#_A -> SRC2 Default 0 0 0 0 0 0 0 0 Disable CR#_C CR#_C -> SRC0 Disable CR#_D NA, SRC1 not present Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved CR#_F_EN Reserved Reserved Reserved Reserved Reserved SRC_STP_CRTL Description Reserved Enable CR#_F (clk req) -> SRC8 Reserved Reserved Reserved Reserved Reserved If set, SRCs (except SRC1) stop with PCI_STOP# Type RW RW RW RW RW RW RW RW Free Running Stops with PCI_STOP# assertion 0 Disable CR#_F 1 Enable CR#_F Default 0 0 0 0 0 0 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Description Revision ID Rev B = 0001 Rev C = 0010 Vendor ID ICS is 0001, binary Type R R R R R R R R 0 B rev = 0001 C rev = 0010 1 Default X X X X 0 0 0 1 ICS is 0001 1461A—07/28/09 12 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved SE1_OE Reserved Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Output enable for SE1 Reserved Type R R R R RW RW RW RW 0 1 Default 0 1 1 0 0 0 1 0 See Device ID Table Disabled Enabled - Byte 9 Output Control Register Bit 7 6 5 4 3 2 1 0 Pin Name PCIF5 STOP EN TME_Readback REF Strength Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Allows control of PCIF5 with assertion of PCI_STOP# Truested Mode Enable (TME) strap status Sets the REF output drive strength Allows test select, ignores REF/FSC/TestSel Allows entry into test mode, ignores FSB/TestMode IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 0 Free running normal operation 1X (2Loads) Outputs HI-Z Normal operation 1 Stops with PCI_STOP# assertion no overclocking 2X (3 Loads) Outputs = REF/N Test mode Default 0 0 1 0 0 1 0 1 See Table 3: V_IO Selection (Default is 0.8V) Byte 10 Stop Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC5_EN Readback Reserved Reserved Reserved Reserved Reserved CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of SRC5 enable latch Type R RW RW RW RW RW RW RW 0 CPU/PCI Stop Enabled TBD TBD TBD TBD TBD Free Running Free Running 1 SRC5 Enabled TBD TBD TBD TBD TBD Stoppable Stoppable Default Latch 0 0 0 0 0 1 1 Reserved Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Byte 11 iAMT Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved WOL_STOP_EN Reserved CPU2_AMT_EN CPU1_AMT_EN PCI-E_GEN2 Description Reserved Reserved Enable 25MHz WLAN clock during M1 or Power Down. This bit is sticky 1. Reserved M1 mode clk enable, only if ITP_EN=1 M1 mode clk enable Determines if PCI-E Gen2 compliant Type RW RW RW RW RW RW R RW 0 25MHz disabled in Powerdown or M1 Disable Disable non-Gen2 Free Running 1 25MHz enabled in Powerdown or M1 Enable Enable PCI-E Gen2 Compliant Stoppable Default 0 0 NOTE 1 0 1 1 1 CPU 2 Stop Enable Enables control of CPU 2 (ITP)with CPU_STOP# Note Rev B device default is 0. Rev C device is 1 Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Read Back byte count register, max bytes = 32 Byte count is 13 decimal. 1461A—07/28/09 13 Integrated Circuit Systems, Inc. ICS9LPRS535 Datasheet Test Clarification Table Comments HW FSLC/ TEST_SEL HW PIN SW REF/N or HI-Z B9b4 FSLB/ TEST_MOD TEST E ENTRY BIT HW PIN B9b3 Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ Vlow Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control 2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N