9LRS4103BKLF

DATASHEET 32-pin CK505 for Intel Systems Recommended Application: CK505 clock, 32-pin for 5 series Intel chipsets Output Features: • 1 - CPU differential low power push-pull pairs • 1 - SRC differential low power push-pull pairs • 1 - Selectable 120MHz CK_SSC_Disp or 100 MHz SRC low power push-pull pair • 1 - SATA/SRC selectable differential low power push-pull pair • 1 - DOT differential low power push-pull pair • 1 - REF, 14.318MHz Key Specifications: • CPU outputs cycle-cycle jitter < 85ps • SRC output cycle-cycle jitter < 125ps • +/- 100ppm frequency accuracy on all outputs • SRC are PCIe Gen2 compliant ICS9LRS4103 Features/Benefits: • Supports spread spectrum modulation, default is 0.5% down spread • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning • Does not require external pass transistor for voltage regulator • Integrated 33Ω series resistors on differential outputs, Zo=50 Ω Table 1: CPU Frequency Select Table Pin Configuration REF14.318M/FSLC** CKPWRGD/PD#_3.3 SEL_SATA_NS# GNDXTAL VDDXTAL 100.00 14.318 96.00 VDDREF14M 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. X1 1 32 31 30 29 28 27 26 25 24 CPUC0 23 CPUT0 22 GNDCPU X2 2 SMBCLK_3.3 3 SEL_120M# Pin# 21 Pulled Low Pulled High Pin# 10/11 120MHz 100MHz SMBDAT_3.3 4 VDD96 5 DOT96T 6 DOT96C 7 GND96 8 9 GNDSSC VDDCPU 21 SEL_120M# 20 VDDSRC 19 SRC2C 18 SRC2T 17 GNDSRC GNDSATA 9LRS4103 CK_SSC_DISP_C CK_SSC_DISP_T VDDSSC SRC1T/SATA_NS_T VDDSATA SEL_SATA_NS# Pin# 31 0 1 Pin# 14/15 100MHz_nonSS 100MHz_SS 10 11 12 13 14 15 16 SRC1C/SATA_NS_C ** Internal Pull-Down Resistor IDT® PC MAIN CLOCK GNDREF FSLC B0b7 0 (Default) 1 CPU MHz 133.33 100.00 SRC MHz REF MHz DOT MHz 1520A—03/16/10 1 ICS9LRS4103 PC MAIN CLOCK Pin Description Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name X1 X2 SMBCLK_3.3 SMBDAT_3.3 VDD96 DOT96T DOT96C GND96 GNDSSC CK_SSC_DISP_T CK_SSC_DISP_C VDDSSC VDDSATA SRC1T/SATA_NS_T SRC1C/SATA_NS_C GNDSATA GNDSRC SRC2T SRC2C VDDSRC SEL_120M# GNDCPU Type Pin Description IN Crystal input, Nominally 14.318MHz. OUT IN I/O PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR IN Crystal output, Nominally 14.318MHzMHz. Clock pin of SMBus circuitry, 3.3V tolerant. Data pin for SMBus circuitry, 3.3V tolerant. Power pin for the DOT96MHz output 3.3V. True clock DOT96 output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock DOT96 output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Ground pin for the DOT96MHz output. Ground pin for the CK_SSC_DISP output. True clock of CK_SSC_DISP (100MHz or 120MHz) output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of CK_SSC_DISP (100MHz or 120MHz) output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Power pin for the CK_SSC_DISP output 3.3V Power pin for the SATA output 3.3V True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Ground pin for the SATA output. Ground pin for the SRC output. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. Power pin for the SRC output 3.3V. Selects pins #10/11 to be 120MHz or 100MHz. "0" = 120MHz, "1" = 100MHz. PWR Ground pin for the CPU output. True clock of differential pair 0.8V push-pull CPU outputs with integrated CPUT0 OUT 33ohm series resistor. No 50 ohm resistor to GND needed. Complementary clock of differential pair 0.8V push-pull CPU outputs with CPUC0 OUT integrated 33ohm series resistor. No 50 ohm resistor to GND needed. VDDCPU PWR Power pin for the CPU output 3.3V Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# CKPWRGD/PD#_3.3 IN mode VDDREF14M PWR Power pin for the REF output 3.3V Reference 14.318 MHz clock, which drives 3 loads on default / 3.3V tolerant REF14.318M_3X/FSLC** I/O input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. GNDREF PWR Ground pin for the REF output. VDDXTAL PWR Power pin for XTAL 3.3V SEL_SATA_NS# IN Selects pin #14/15 to be SRC1 or SATA_NS. "0" = SATA_NS, "1" = SRC1 GNDXTAL PWR Ground pin for XTAL. IDT® PC MAIN CLOCK 1520A—03/16/10 2 ICS9LRS4103 PC MAIN CLOCK General Description ICS9LRS4103 is compatible with the Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop 5 series chipsets. ICS9LRS4103 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support. Block Diagram PLL3 SSC_DISP (SS) SSC_DISP 120/100MHz Div PLL1 CPU/SRC (SS) Div CPU 100/133MHz SRC 100MHz Div PLL2 DOT96 SATA (non-SS/SS) 100MHz (Non-SS) 14.318M Div DOT96MHz (non-SS) REF 14.318MHz IDT® PC MAIN CLOCK 1520A—03/16/10 3 ICS9LRS4103 PC MAIN CLOCK Absolute Maximum Ratings PARAMETER Maximum Supply Voltage SYMBOL VDDxxx CONDITIONS Core/Logic Supply Low Voltage Differential I/O Supply 3.3V LVTTL Inputs Any Input Human Body Model MIN MAX 4.6 3.8 4.6 GND - 0.5 -65 2000 150 115 UNITS V V V V ° ° Notes 1,7 1,7 1,7,8 1,7 1,7 1,7 1,7 Maximum Supply Voltage VDDxxx_IO Maximum Input Voltage V IH Minimum Input Voltage VIL Storage Temperature Ts Case Temperature Tcase Input ESD protection ESD prot C C V Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER Ambient Operating Temp Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Input Leakage Current Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Power Down Current iAMT Mode Current Input Frequency Pin Inductance Input Capacitance Spread Spectrum Modulation Frequency SYMBOL Tambient VDDxxx VIHSE VILSE IIN IINRES VOHSE VOLSE V OHDIF V OLDIF V IH_FS VIL_FS IDD IDD_PD3.3 IDD_iAMT3.3 Fi Lpin CIN COUT CINX fSSMOD CONDITIONS Supply Voltage Single-ended inputs Single-ended inputs VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Differential Outputs Differential Outputs 3.3 V +/-5% 3.3 V +/-5% 3.3V supply 3.3V supply, Power Down Mode 3.3V supply, iAMT Mode VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation 1.5 MIN 0 3.135 2 VSS - 0.3 -5 -200 2.4 0.7 0.7 VSS - 0.3 0.4 0.9 0.4 VDD + 0.3 0.35 100 6 50 14.3182 7 5 6 6 33 MAX 70 3.465 VDD + 0.3 0.8 5 200 UNITS ° C V V V uA uA V V V V V V mA mA mA MHz nH pF pF pF kHz Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 30 IDT® PC MAIN CLOCK 1520A—03/16/10 4 ICS9LRS4103 PC MAIN CLOCK AC Electrical Characteristics - Input/Common Parameters PARAMETER Clk Stabilization Tfall_PD# Trise_PD# SYMBOL TSTAB TFALL TRISE CONDITIONS From VDD Power-Up or de-assertion of PD# to 1st clock Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MIN MAX 1.8 5 5 UNITS ms ns ns Notes 1 1 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER Rising Edge Slew Rate Falling Edge Slew Rate Slew Rate Variation Maximum Output Voltage Minimum Output Voltage Differential Voltage Swing Crossing Point Voltage SYMBOL tSLR tFLR tSLVAR VHIGH VLOW VSWING VXABS CONDITIONS Differential Measurement Differential Measurement Single-ended Measurement Includes overshoot Includes undershoot Differential Measurement Single-ended Measurement Single-ended Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement Differential Measurement, all SRC from same PLL 45 MIN 2.5 2.5 MAX 4 4 20 1150 UNITS V/ns V/ns % mV mV mV mV mV % ps ps ps ps NOTES 1,2 1,2 1 1 1 1 1,3,4 1,3,5 1 1 1 1 1 -300 300 300 550 140 55 85 125 250 200 Crossing Point Variation VXABSVAR Duty Cycle CPU Jitter - Cycle to Cycle SRC Jitter - Cycle to Cycle DOT Jitter - Cycle to Cycle SRC Skew DCYC CPUJC2C SRCJC2C DOTJC2C SRCSKEW Electrical Characteristics - REF-14.318MHz PARAMETER Long Accuracy Clock period Absolute min/max period Output High Voltage Output Low Voltage Output High Current Output Low Current Rising Edge Slew Rate Falling Edge Slew Rate Duty Cycle Jitter SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc CONDITIONS see Tperiod min-max values 14.318180 MHz output nominal 14.318180 MHz including cycle to cycle jitter IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V MIN 0 69.8413 MAX 0 69.8413 UNITS ppm ns ns V V mA mA V/ns V/ns % ps Notes 1,6 6 6 1 1 1 1 1 1 1 1 68.8413 70.84128 2.4 0.4 -33 30 1 1 45 -33 38 4 4 55 1000 IDT® PC MAIN CLOCK 1520A—03/16/10 5 ICS9LRS4103 PC MAIN CLOCK Electrical Characteristics - SMBus Interface PARAMETER SMBus Voltage Low-level Output Voltage Current sinking at V OLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency SYMBOL VDD VOLSMB IPULLUP TRI2C TFI2C FSMBUS CONDITIONS @ IPULLUP SMB Data Pin (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) Block Mode 4 1000 300 100 MIN 2.7 MAX 5.5 0.4 UNITS V V mA ns ns kHz Notes 1 1 1 1 1 1 Notes on Electrical Characteristics: 1 2 3 4 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK# 5 O nly applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF has been tuned to exactly 14.318180 MHz O peration under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD 7 6 8 IDT® PC MAIN CLOCK 1520A—03/16/10 6 ICS9LRS4103 PC MAIN CLOCK Differential Clock Tolerances PPM tolerance Cycle to Cycle Jitter Spread CPU 100 50 -0.50% SRC 100 125 -0.50% DOT96 100 250 0 CK_SSC_DISP 100 125 -0.50% ppm ps % Clock Periods - Differential Outputs with Spread Spectrum Disabled Center Freq. MHz 100.00 133.33 100.00 120.00 96.00 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm -c2c jitter Short-Term Long-Term 0 ppm Period Long-Term AbsPer Average Average Nominal Average Min Min Min Max 9.94900 9.99900 10.00000 10.00100 7.44925 7.49925 7.50000 7.50075 9.87400 9.99900 10.00000 10.00100 8.20750 8.33250 8.33333 8.33417 10.16563 10.41563 10.41667 10.41771 1 Clock 1us +SSC S hort-Term Average Max 1 Clock +c2c jitter Units Notes AbsPer Max 10.05100 7.55075 10.12600 8.45917 10.66771 ns ns ns ns ns 1,2 1,2 1,2 1,2 1,2 SSC OFF CPU SRC CK_SSC_DISP DOT96 Clock Periods - Differential Outputs with Spread Spectrum Enabled Center Freq. MHz 99.75 133.00 99.75 119.70 Measurement Window 1us 0.1s 0.1s 0.1s -SSC - ppm + ppm -c2c jitter Short-Term Long-Term 0 ppm Period Long-Term AbsPer Nominal Average Average Average Min Min Max Min 9.94906 9.99906 10.02406 10.02506 10.02607 7.44930 7.49930 7.51805 7.51880 7.51955 9.87406 9.99906 10.02406 10.02506 10.02607 8.20755 8.33255 8.35338 8.35422 8.35505 1 Clock 1us +SSC S hort-Term Average Max 10.05107 7.53830 10.05107 8.37589 1 Clock +c2c jitter Units Notes AbsPer Max 10.10107 7.58830 10.17607 8.50089 ns ns ns ns 1,2 1,2 1,2 1,2 SSC ON CPU SRC CK_SSC_DISP 1 2 Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz. IDT® PC MAIN CLOCK 1520A—03/16/10 7 ICS9LRS4103 PC MAIN CLOCK Table 1: CPU Frequency Select Table FSLC B0b7 0 (Default) 1 CPU MHz 133.33 100.00 SRC MHz 100.00 REF MHz DOT MHz 14.318 96.00 1. FSLC is a low-threshold input.Please see VIL_FS and VIH_FS s pecifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. Table 3: Device ID table B8b7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B8b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B8b5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B8b4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Comment Table 2: IO_Vout select table IO_ B9b2 B9b1 B9b0 Vout 0 0 0 0.3V 0 0 1 0.4V 0 1 0 0.5V 0 1 1 0.6V 1 0 0 0.7V 1 0 1 0.8V 1 1 0 0.9V 1 1 1 1.0V 56 pin TSSOP 64 pin TSSOP Reserved Reserved Reserved 72 pin QFN Reserved Reserved 32 pin QFN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Table 4: Series Resistors for REF Output Number of Loads REF Rs to Drive Strength D.C.Drive 1 1x 33 [39 ] Strength 1 2x 39 [43 ] 2 2x 27 [33 ] Notes: 1. Preferred drive strengths using CK505 clock sources. Transmission 2. Desktop/Mobile Platforms with Zo = 50/55 ohms use the first resistor value. 3. Systems with Zo = 60 ohms use the resistor values in brackets [ ]. IDT® PC MAIN CLOCK 1520A—03/16/10 8 ICS9LRS4103 PC MAIN CLOCK PD# Power Management Device State Latches Open Single-ended Clocks Differential Clocks w/o Latched input w/Latched input CPU0 CK= Pull down, CK# CK= Pull down, CK# = Low = Low Power Down Low M1 Hi-Z CK= Pull down CK# = Low CK= Pull down CK# = Low CK= Pull down CK# = Low Running Virtual Power Cycle to Latches Open CK= Pull down, CK# CK= Pull down, CK# = Low = Low IDT® PC MAIN CLOCK 1520A—03/16/10 9 ICS9LRS4103 PC MAIN CLOCK General SMBus serial interface information for the ICS9LRS4103 How to Write: • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the beginning byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ICS (Slave/Receiver) ACK ACK Byte N + X - 1 ACK P stoP bit ACK X Byte Byte N + X - 1 N P Not acknowledge stoP bit IDT® PC MAIN CLOCK 1520A—03/16/10 10 ICS9LRS4103 PC MAIN CLOCK Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 4 3 2 1 Pin Name FSLC Reserved Reserved iAMT_EN Reserved SEL_120M# SEL_SATA_NS# Description CPU Freq. Sel. Bit Reserved Reserved Set via SMBus Reserved Selects pins #10/11 to be 120MHz or 100MHz Select source for SATA clock 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold poweron and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. Type R RW RW RW (Sticky 1) RW R R 0 Legacy Mode 120MHz SATA (100MHz_nonSS) 1 iAMT Enabled 100MHz SRC1 (100MHz SS) Default Latch 0 1 0 0 Latch Latch 0 PD_Restore RW Configuration Not Saved Configuration Saved 1 Byte 1 CPU/SRC Spread Selection Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved CK505 PLL1_SSC_SEL Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Select 0.5% down or center SSC Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Down spread 1 Center spread Default 0 0 0 0 0 0 1 1 Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name REF_3L_OE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Output enable for REF0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Output Disabled 1 Output Enabled Default 1 1 1 1 1 1 1 1 Byte 3 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 1 1 1 1 1 1 1 1 IDT® PC MAIN CLOCK 1520A—03/16/10 11 ICS9LRS4103 PC MAIN CLOCK Byte 4 Output and Spread Spectrum Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name CK_SSC_DISP SATA/SRC1_OE SRC2_OE DOT96_OE Reserved CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for CK_SSC_DISP Output enable for SATA/SRC1 Output enable for SRC2 Output enable for DOT96 Reserved Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation Type RW RW RW RW RW RW RW RW 0 Disabled Disabled Disabled Disabled Output Disabled Spread Disabled Spread Disabled Output Output Output Output 1 Enabled Enabled Enabled Enabled Output Enabled Spread Enabled Spread Enabled Output Output Output Output Default 1 1 1 1 1 1 1 1 Byte 5 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 0 0 Byte 6 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit Description 3 2 1 0 3 2 1 0 Revision ID Type R R R R R R R R 0 1 Default X X X X 0 0 0 1 Vendor specific Vendor ID ICS is 0001, binary Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 Reserved Reserved Reserved Reserved Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Reserved Reserved Reserved Reserved Type R R R R RW RW RW RW 0 32-pin device 1 Default 1 0 0 0 0 0 0 0 1520A—03/16/10 IDT® PC MAIN CLOCK 12 ICS9LRS4103 PC MAIN CLOCK Byte 9 Amplitude Control Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved REF Strength Reserved Reserved IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Reserved Reserved Sets the REF output drive strength Reserved Reserved IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit) Type RW R RW RW RW RW RW RW 0 1X (2Loads) 1 2X (3 Loads) Default 0 0 1 0 0 1 0 1 See Table 2: V_IO Selection (Default is 0.8V) Byte 10 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 0 1 1 Byte 11 iAMT Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved Reserved CPU0_AMT_EN PCI-E_GEN2 Reserved Description Reserved Reserved Reserved Reserved Reserved M1 mode clk enable Determines if PCI-E Gen2 compliant Reserved Type RW RW RW RW RW RW R RW 0 1 Default 0 0 0 1 0 1 1 1 Disable non-Gen2 - Enable PCI-E Gen2 Compliant - Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Description Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 1 1 0 1 Read Back byte count register, max bytes = 32 IDT® PC MAIN CLOCK 1520A—03/16/10 13 ICS9LRS4103 PC MAIN CLOCK Seating Plane Index Area N 1 E Top View Anvil Singulation OR Sawn Singulation E2 E2 2 A1 A3 L (Ref. ) (N D - 1)x e (Ref. ) ND & NE Even N e (Typ.) 2 If N D & N E are Even 1 2 (N E - 1)x e (Ref. ) b A (Ref.) e D2 2 D2 D ND & NE Odd C Thermal Base Chamfer 4x 0.6 x 0.6 max OPTIONAL 0.08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL N ND NE 32L 32 8 8 DIMENSIONS (mm) SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. MIN. MAX. 0.8 1.0 0 0.05 0.20 Reference 0.18 0.3 0.50 BASIC 5.00 x 5.00 3.0 3.3 3.0 3.3 0.3 0.5 Marking Diagram ICS RS4103BL YYWW ORIGIN ###### Ordering Information Part / Order Number 9LRS4103BKLF 9LRS4103BKLFT Shipping Packaging Tubes Tape and Reel Package 32-pin MLF 32-pin MLF Temperature 0 to +70° C 0 to +70° C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. "B" is the device revision designator (will not correlate with the datasheet revision). IDT® PC MAIN CLOCK 1520A—03/16/10 14 ICS9LRS4103 PC MAIN CLOCK Revision History Rev. 0.1 Issue Date WHO Description 10/08/08 RDW Initial Release Updated Electrical Characterisitcs 1) Updated Idd characteristics for 32-pin parts. Old Idd values were for 56/64 pin devices RDW 2) Updated REF to be 0 ppm – tuned by user with external load caps. It is not +/-300ppm. 3) Minor updates to pagination 4) Added connector dot to SRC output to indicate connection. RDW 1) Removed Reference to Wake-On-LAN current spec in data sheet, this part does not s upport WOL. RDW SRC Skew from: 500ps to: 200ps RDW Added top-side marking 1. Updated electrical characteristics per char data 2. Added Table 4: Series Resistor values for REF 3. Corrected SMBus reference to REF strength. REF is 1 load/2load strength. RDW 4. Release to final Page # - 0.2 11/03/08 Various 0.3 0.4 0.5 11/05/08 12/17/08 04/13/09 A 03/15/10 Various This product is protected by United States Patent NO. 7,342,420 and other patents. Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 Europe IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. A ccelerated T hinking is a service mark of Integrated Device Technology, Inc. A ll other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 15