9P936AFLF

DATASHEET Low Skew Dual Bank DDR I/II Fan-out Buffer Description Dual DDR I/II fanout buffer for VIA Chipset AVDD2.5 ICS9P936 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND VDDQ2.5/1.8 AVDD2.5 AGND DDRT5 DDRC5 GND VDDQ2.5/1.8 DDRT4 DDRC4 DDRT3 DDRC3 SDATA SCLK Output Features • • • • • • • • • Low skew, fanout buffer SMBus for functional and output control Single bank 1-6 differential clock distribution 1 pair of differential feedback pins for input to output synchronization Supports up to 2 DDR DIMMs 266MHz (DDRI 533) output frequency support 400MHz (DDRII 800) output frequency support Programmable skew through SMBus Individual output control programmable through SMBus AGND BUF_INT BUF_INC DDRT0 DDRC0 DDRT1 DDRC1 GND VDDQ2.5/1.8 FB_OUTT FB_OUTC DDRT2 DDRC2 Key Specifications • • • • • OUTPUT - OUTPUT skew: