ACS422MX00

DATASHEET PORTABLE CONSUMER CODEC LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC ACS422Mx00 FEATURES • High fidelity 24-bit stereo CODEC • • DAC 102dB SNR; THD+N better than -82dB ADC 90dB SNR, THD + N better than -80dB 3D stereo enhancement Dual (cascaded) stereo 6-band parametric equalizers Programmable Compressor/Limiter/Expander Psychoacoustic Bass and Treble enhancement processing DESCRIPTION The ACS422Mx00 is a low-power, high-fidelity integrated CODEC targeted at portable applications such as tablet computers, personal navigation devices, portable projectors and speaker docks. In addition to a high-fidelity low-power CODEC, the device integrates a MONO DDXTM Class D speaker amplifier a true cap-less headphone amplifier, and four programmable system PLLs to enable the timing management of the systems applications processor, USB interface, secondary audio and other subsystems. Beyond high-fidelity for portable systems, the device offers an enriched “audio presence” through built-in audio processing capability. The ACS422Mx00 has been designed with rapid customization in mind. IDT is able to rapidly provide varying levels of integration, additional audio processing, more or fewer PLLs, etc, according to the needs of large markets or customers. • Built in audio controls and processing • • • • • Filterless Mono DDXTM Class D Speaker Driver • • • • • 1W/channel (8) or 2W/channel (4), 0.05% THD+N typical Tri-state DDXTM Class D achieves low EMI and high efficiency >80% efficiency at 1W Spread spectrum support for reduced EMI output power mode Anti-Pop circuitry 40 mW output power (16) Charge-pump allows true ground centered outputs SNR of 102dB TARGET APPLICATIONS • • • • • Tablet Computers Portable Navigation Devices Personal Media Players Portable Projectors Speaker Docks • • • On-chip true cap-less headphone driver • • • I2S data interface Microphone/line-in interface • • • Analog microphone or line-in inputs Digital microphone (ACS422MD00) Automatic level control • 4 on-chip low-jitter PLLs for internal and system timing • • Multiple frequency options Spread spectrum support 1.7 V CODEC supports 1Vrms Very low standby and no-signal power consumption 1.8V digital / 1.7V analog supply for low power • Low power with built in power management • • • • • 2-wire (I2C compatible) control interface 68-pin dual row 6x6 mm Thermal Leadless Array package DDXTM and the DDX logo are trademarks of Apogee Technology. 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC TABLE OF CONTENTS 1. OVERVIEW ................................................................................................................................ 3 1.1. Block Diagram ...................................................................................................................................3 1.2. Audio Outputs ....................................................................................................................................3 1.3. Audio Inputs .......................................................................................................................................4 1.4. On-Chip PLLs ....................................................................................................................................4 2. POWER MANAGEMENT .......................................................................................................... 5 2.1. Control Registers ...............................................................................................................................5 2.2. Stopping the Master Clock .................................................................................................................6 3. OUTPUT AUDIO PROCESSING ............................................................................................... 7 3.1. DC Removal ......................................................................................................................................7 3.2. Volume Control ..................................................................................................................................8 3.3. Digital DAC Volume Control ...............................................................................................................9 3.4. Parametric Equalizer .........................................................................................................................9 3.4.1. Prescaler & Equalizer Filter .................................................................................................9 3.4.2. EQ Registers ......................................................................................................................10 3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................11 3.5. Gain and Dynamic Range Control ...................................................................................................15 3.6. Limiter ..............................................................................................................................................15 3.7. Compressor .....................................................................................................................................16 3.7.1. Configuration ......................................................................................................................17 3.7.2. Controlling parameters .......................................................................................................17 3.7.3. Overview ............................................................................................................................18 3.7.4. Limiter/Compressor Registers ............................................................................................20 3.7.5. Expander Registers ...........................................................................................................22 3.8. Output Effects ..................................................................................................................................23 3.9. Stereo Depth (3-D) Enhancement ...................................................................................................23 3.10. Psychoacoustic Bass Enhancement ..............................................................................................24 3.10.1. Non-linear function ...........................................................................................................24 3.10.2. Signal processing summary .............................................................................................25 3.10.3. Control Points ..................................................................................................................25 3.11. Treble Enhancement .....................................................................................................................26 3.11.1. Enhanced Treble NLF ......................................................................................................26 3.11.2. Signal processing summary .............................................................................................26 3.11.3. Control Points ..................................................................................................................27 3.12. Mute and De-Emphasis .................................................................................................................27 3.13. Mono Operation and Phase Inversion ...........................................................................................27 3.13.1. DAC Control Register .....................................................................................................27 3.13.2. Interpolation and Filtering ................................................................................................28 3.14. Analog Outputs ..............................................................................................................................29 3.14.1. Headphone Output ...........................................................................................................29 3.14.2. Speaker Outputs ..............................................................................................................29 3.14.3. DDXTMClass D Audio Processing ....................................................................................30 3.15. Other Output Capabilities ..............................................................................................................36 3.15.1. Audio Output Control .......................................................................................................36 3.15.2. Headphone Switch ...........................................................................................................36 3.15.3. Headphone Operation ......................................................................................................37 3.15.4. EQ Operation ...................................................................................................................37 3.16. Thermal Shutdown .........................................................................................................................38 3.16.1. Algorithm description: ......................................................................................................38 3.16.2. Thermal Trip Points. .........................................................................................................38 3.16.3. Temperature Limit State Diagram: ...................................................................................39 3.16.4. Instant Cut Mode ..............................................................................................................39 3.16.5. Short Circuit Protection ....................................................................................................40 3.16.6. Thermal Shutdown Registers ...........................................................................................40 4. INPUT AUDIO PROCESSING ................................................................................................. 43 4.1. Analog Inputs ...................................................................................................................................43 4.1.1. Input Registers ...................................................................................................................44 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.2. Mono Mixing and Output Configuration ...........................................................................................44 4.2.1. ADC Registers ...................................................................................................................45 4.3. Microphone Bias ..............................................................................................................................46 4.3.1. Microphone Bias Control Register .....................................................................................46 4.4. Programmable Gain Control ............................................................................................................46 4.4.1. Input PGA Software Control Register. ...............................................................................47 4.5. ADC Digital Filter .............................................................................................................................47 4.5.1. ADC Signal Path Control Register .....................................................................................49 4.5.2. ADC High Pass Filter Enable modes .................................................................................49 4.6. Digital ADC Volume Control .............................................................................................................49 4.6.1. ADC Digital Registers ........................................................................................................50 4.7. Automatic Level Control (ALC) ........................................................................................................50 4.7.1. ALC Operation ..................................................................................................................50 4.7.2. ALC Registers ....................................................................................................................52 4.7.3. Peak Limiter .......................................................................................................................53 4.7.4. Input Threshold ..................................................................................................................53 4.8. Digital Microphone Support .............................................................................................................53 4.8.1. DMIC Register ...................................................................................................................56 5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 57 5.1. Data Interface ..................................................................................................................................57 5.2. Master and Slave Mode Operation ..................................................................................................57 5.3. Audio Data Formats .........................................................................................................................58 5.4. Left Justified Audio Interface ...........................................................................................................58 5.5. Right Justified Audio Interface (assuming n-bit word length) ...........................................................58 5.6. I2S Format Audio Interface ..............................................................................................................59 5.7. Data Interface Registers ..................................................................................................................59 5.7.1. Audio Data Format Control Register ..................................................................................59 5.7.2. Audio Interface Output Tri-state .........................................................................................60 5.7.3. Audio Interface Bit Clock and LR Clock configuration ........................................................60 5.7.4. Bit Clock and LR Clock Mode Selection ............................................................................61 5.7.5. ADC Output Pin State ........................................................................................................62 5.7.6. Audio Interface Control 3 Register .....................................................................................62 5.8. Bit Clock Mode .................................................................................................................................62 5.9. Control Interface ..............................................................................................................................63 5.9.1. Register Write Cycle ..........................................................................................................63 5.9.2. Multiple Write Cycle ...........................................................................................................64 5.9.3. Register Read Cycle ..........................................................................................................64 5.9.4. Multiple Read Cycle ...........................................................................................................65 5.9.5. Device Addressing and Identification .................................................................................65 6. AUDIO CLOCK GENERATION ............................................................................................... 67 6.1. Internal Clock Generation ................................................................................................................67 6.2. Clocking and Sample Rates ............................................................................................................67 6.3. DAC/ADC Modulator Rate Control ...................................................................................................68 7. PLL SECTION ........................................................................................................................ 70 7.1. PLL Block diagram ...........................................................................................................................70 8. CHARACTERISTICS ............................................................................................................... 71 8.1. Electrical Specifications ...................................................................................................................71 8.1.1. Absolute Maximum Ratings ...............................................................................................71 8.1.2. Recommended Operating Conditions ................................................................................71 8.2. Device Characteristics .....................................................................................................................72 8.3. PLL Section DC Electrical Characteristics .......................................................................................74 8.4. PLL Section AC Timing Specs .........................................................................................................74 8.5. Typical Power Consumption ............................................................................................................75 8.6. Low Power Mode Power Consumption ............................................................................................75 9. REGISTER MAP ...................................................................................................................... 76 10. PACKAGE INFORMATION ................................................................................................... 78 10.1. Package Drawing ...........................................................................................................................78 10.2. Pb Free Process- Package Classification Reflow Temperatures ..................................................78 11. PIN INFORMATION ............................................................................................................... 79 2 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 11.1. ACS422MA00 Pin Diagram ...........................................................................................................79 11.2. ACS422MD00 Pin Diagram ...........................................................................................................80 11.3. Pin Tables ......................................................................................................................................81 11.3.1. Power Pins .......................................................................................................................81 11.3.2. Reference Pins ................................................................................................................81 11.3.3. Analog Input Pins .............................................................................................................82 11.3.4. Analog Output Pins ..........................................................................................................82 11.3.5. Data and Control Pins ......................................................................................................82 11.3.6. PLL Pins ...........................................................................................................................83 12. APPLICATION INFORMATION ............................................................................................ 84 13. ORDERING INFORMATION ................................................................................................. 84 14. DISCLAIMER ......................................................................................................................... 84 15. DOCUMENT REVISION HISTORY ....................................................................................... 85 3 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422x00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF FIGURES Figure 1. Block Diagram ...................................................................................................................................3 Figure 2. Output Audio Processing ..................................................................................................................7 Figure 3. Prescaler & EQ Filters ....................................................................................................................10 Figure 4. 6-Tap IIR Equalizer Filter ................................................................................................................10 Figure 5. DAC Coefficient RAM Write Sequence ...........................................................................................12 Figure 6. DAC Coefficient RAM Read Sequence ...........................................................................................13 Figure 7. Gain Compressor, Output vs Input .................................................................................................16 Figure 8. Compressor block diagram .............................................................................................................18 Figure 9. 3-D Channel Inversion ....................................................................................................................23 Figure 10. Bass Enhancement .......................................................................................................................24 Figure 11. Treble Enhancement ....................................................................................................................26 Figure 12. Interpolation and Filtering .............................................................................................................28 Figure 13. Constant Output Power Error ........................................................................................................32 Figure 14. Constant Output Power nominal and high/low ..............................................................................32 Figure 15. Temp sense volume adjustment algorithm ...................................................................................39 Figure 16. Input Audio Processing .................................................................................................................43 Figure 17. Mic Bias ........................................................................................................................................46 Figure 18. ADC Filter Data path .....................................................................................................................47 Figure 19. ADC Input processing ...................................................................................................................48 Figure 20. ALC Operation ..............................................................................................................................50 Figure 21. Single Digital Microphone (data is ported to both left and right channels) ....................................55 Figure 22. Stereo Digital Microphone Configuration ......................................................................................56 Figure 23. Master mode .................................................................................................................................57 Figure 24. Slave mode ...................................................................................................................................57 Figure 25. Left Justified Audio Interface (assuming n-bit word length) ..........................................................58 Figure 26. Right Justified Audio Interface (assuming n-bit word length) ........................................................58 Figure 27. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................59 Figure 28. Bit Clock mode ..............................................................................................................................63 Figure 29. 2-Wire Serial Control Interface ......................................................................................................64 Figure 30. Multiple Write Cycle ......................................................................................................................64 Figure 31. Read Cycle ...................................................................................................................................65 Figure 32. Multiple Read Cycle ......................................................................................................................65 Figure 33. PLL Block Diagram .......................................................................................................................70 Figure 34. Package Outline ...........................................................................................................................78 Figure 35. ACS422MA00 Pinout ....................................................................................................................79 Figure 36. ACS422MD00 Pinout ....................................................................................................................80 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.8 04/11 ACS422X00 ACS422x00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF TABLES Table 1. Power Management Register 1 ..........................................................................................................5 Table 2. Power Management Register 2 ..........................................................................................................5 Table 3. Power Management Register1 -- Master Clock Disable ....................................................................6 Table 4. DC_COEF_SEL Register ...................................................................................................................7 Table 5. CONFIG0 Register .............................................................................................................................7 Table 6. Volume Update Control Register .......................................................................................................8 Table 7. Gain Control Register .........................................................................................................................8 Table 8. DAC Volume Control Registers ..........................................................................................................9 Table 9. CONFIG1 Register ...........................................................................................................................10 Table 10. DACCRAM Read/Write Registers .................................................................................................11 Table 11. DACCRAM Address Register ........................................................................................................11 Table 12. DACCRAM Status Register ...........................................................................................................11 Table 13. DACCRAM EQ Addresess .............................................................................................................14 Table 14. DACCRAM Bass/Treble Addresses ...............................................................................................14 Table 15. CLECTL Register ...........................................................................................................................20 Table 16. MUGAIN Register ..........................................................................................................................20 Table 17. COMPTH Register .........................................................................................................................20 Table 18. CMPRAT Register ..........................................................................................................................20 Table 19. CATKTCL Register ........................................................................................................................20 Table 20. CATKTCH Register ........................................................................................................................21 Table 21. CRELTCL Register ........................................................................................................................21 Table 22. CRELTCH Register ........................................................................................................................21 Table 23. LIMTH Register ..............................................................................................................................21 Table 24. LIMTGT Register ............................................................................................................................21 Table 25. LATKTCL Register .........................................................................................................................21 Table 26. LATKTCH Register ........................................................................................................................21 Table 27. LRELTCL Register .........................................................................................................................21 Table 28. LRELTCH Register ........................................................................................................................22 Table 29. EXPTH Register .............................................................................................................................22 Table 30. EXPRAT Register ..........................................................................................................................22 Table 31. XATKTCL Register .........................................................................................................................22 Table 32. XATKTCH Register ........................................................................................................................22 Table 33. XRELTCL Register .........................................................................................................................22 Table 34. XRELTCH Register ........................................................................................................................22 Table 35. FX Control Register ........................................................................................................................23 Table 36. CNVRTR1 Register ........................................................................................................................27 Table 37. HPVOL L/R Registers ....................................................................................................................29 Table 38. SPKVOL L/R Registers ..................................................................................................................30 Table 39. Constant Output Power 1 Register ................................................................................................33 Table 40. Constant Output Power 2 Register ................................................................................................33 Table 41. Constant Output Power 3 Register ................................................................................................34 Table 42. CONFIG0 Register .........................................................................................................................34 Table 43. PWM0 Register ..............................................................................................................................34 Table 44. PWM1 Register ..............................................................................................................................35 Table 45. PWM2 Register ..............................................................................................................................35 Table 46. PWM3 Register ..............................................................................................................................35 Table 47. Power Management 2 Register ......................................................................................................36 Table 48. Additional Control Register ............................................................................................................37 Table 49. Headphone Operation ....................................................................................................................37 Table 50. EQ Operation .................................................................................................................................37 Table 51. Additional Control Register ............................................................................................................40 Table 52. THERMTS Register .......................................................................................................................41 Table 53. THERMTSPKR1 Register ..............................................................................................................42 Table 54. THERMTSPKR2 Register ..............................................................................................................42 Table 55. Input Software Control Register .....................................................................................................44 Table 56. INMODE Register ..........................................................................................................................45 Table 57. CNVRTR0 Register ........................................................................................................................45 Table 58. AIC2 Register .................................................................................................................................45 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.8 04/11 ACS422X00 ACS422x00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Table 59. Power Management 1 Register - Mic Bias Enable .........................................................................46 Table 60. INVOL L&R Registers ....................................................................................................................47 Table 61. CNVRTR0 Register ........................................................................................................................49 Table 62. ADC HPF Enable ...........................................................................................................................49 Table 63. L/R ADC Digital Volume Registers .................................................................................................50 Table 64. ALC Control Registers ...................................................................................................................52 Table 65. NGATE Register ............................................................................................................................53 Table 66. DMIC Clock ....................................................................................................................................54 Table 67. Valid Digital Mic Configurations .....................................................................................................55 Table 68. DMICCTL Register .........................................................................................................................56 Table 69. AIC1 Register .................................................................................................................................59 Table 70. AIC2 Register .................................................................................................................................60 Table 71. Bit Clock and LR Clock Mode Selection .........................................................................................61 Table 72. ADC Data Output pin state ............................................................................................................62 Table 73. AIC3 Register .................................................................................................................................62 Table 74. Master Mode BCLK Frequency Control Register ...........................................................................63 Table 75. DEVADRl Register .........................................................................................................................65 Table 76. DEVID H&L Registers ....................................................................................................................66 Table 77. REVID Register ..............................................................................................................................66 Table 78. RESET Register .............................................................................................................................66 Table 79. ADCSR Register ............................................................................................................................67 Table 80. DACSR Register ............................................................................................................................68 Table 81. Master Clock and Sample Rates ....................................................................................................68 Table 82. CONFIG0 Register .........................................................................................................................69 Table 83. SDM Rates .....................................................................................................................................69 Table 84. Electrical Specification: Maximum Ratings ....................................................................................71 Table 85. Recommended Operating Conditions ............................................................................................71 Table 86. Device Characteristics ...................................................................................................................72 Table 87. PLL Section DC Characteristics .....................................................................................................74 Table 88. PLL Section AC Characteristics .....................................................................................................74 Table 89. Typical Power Consumption ..........................................................................................................75 Table 90. Low power mode power consumption ............................................................................................75 Table 91. Register Map ..................................................................................................................................76 Table 92. Reflow Temperatures .....................................................................................................................78 Table 93. Power Pins .....................................................................................................................................81 Table 94. Reference Pins ..............................................................................................................................81 Table 95. Analog Input Pins ...........................................................................................................................82 Table 96. Analog Output Pins ........................................................................................................................82 Table 97. Data and Control Pins ....................................................................................................................82 Table 98. PLL Pins .........................................................................................................................................83 2 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.8 04/11 ACS422X00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. OVERVIEW 1.1. Block Diagram The ACS422Mx00 is an advanced low power codec with integrated amplifiers and timing generators. To support the design of audio subsystems in a portable device, the ACS422Mx00 features an intelligent codec architecture with advanced audio processing algorithms, integrated with a true capless headphone amplifier, 1W/channel (8) or 2W/channel (4) filterless DDXTM mono class D amplifier, and microphone interface with programmable gain. Clocking 4 PLLs CPVDD VDD_XTAL VDD_PLL2 VDDO1 VDD_PLL3 VDDO2 VDD_PLL1 VDD_PLSS DVDD_CORE DVDD_IO Digital PWM controller CAP+ CAP- 2 V- 2 AVDD 3 PVDD 4 SPKR + SPKR - vol BTL PLL OUT(s) Charge-Pump Internal Audio Clock(s) REF_OUT XTAL_IN XTAL_OUT DAC Left Digital Volume DAC Antipop HP HP Out Left I2C_SDA I2C_SCL HP_DET TEST Vref AFILT1 Control AFILT2 DAC Right Digital Volume DAC Antipop HP HP Out Righ Audio Processing DACBCLK DACLRCLK DACIN Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander DAC Left DAC Right MUX LIN1 LIN2 RIN1 RIN2 AGND Vref + D2S D2S ADCOUT ADCLRCLK ADCBCLK Source Select Switch -97 to +30 dB In 0.5 dB steps -17 to +30dB in 0.75dB steps Audio Processing +0/+10/+20/+30 dB MUX - LIN1 MUX MUX LIN2 LIN3 D2S + MIC Bias mute VOL ADCL 1 bit AGC Boost LIN1 LIN2 -97 to +30 dB In 0.5 dB steps Automatic Level Control S RIN1 MUX MUX AGC Boost LIN3/DMIC_CLK* Audio Processing mute VOL ADCR 1 bit RIN2 RIN3 D2S RIN1 RIN2 RIN3/DMIC_DAT* -17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB *Digital Microphone Products VSS_PLSS VSSO VSS_PLL VSS_XTAL DVSS AVSS 3 CPGND PVSS 4 Figure 1. Block Diagram 1.2. Audio Outputs The ACS422Mx00 provides multiple outputs for analog sound. Audio outputs include: • A 1W/channel (8) or 2W/channel (4) filterless MONO DDXTM Class D amplifier. This amplifier is capable of driving the speakers typically found in portable equipment, providing high fidelity, high efficiency, and excellent sound quality. • A line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones without requiring an external DC blocking capacitor. Each endpoint features independent volume controls, including a soft-mute capability which can slowly ramp up or down the volume changes to avoid unwanted audio artifacts. 3 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The ACS422Mx00 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are enabled when the ACS422Mx00 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be separately enabled by individual control bits. The digital filter and audio processing block processes the data to provide volume control and numerous sound enhancement algorithms. Two high performance sigma-delta audio DACs convert the digital data into analog. The digital audio data is converted to oversampled bit streams using 24-bit digital interpolation filters, which then enters sigma-delta DACs, and become converted to high quality analog audio signals. To enhance the sound available from the small, low-power speakers typically found in a portable device, the ACS422Mx00 provides numerous audio enhancement capabilities. The ACS422Mx00 features dual, independent, programmable left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. A compressor/limiter features programmable attack and release thresholds, enabling the system designer to attenuate loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be played at a louder volume without distortion. For compressed audio, a programmable expander is available to help restore the dynamic range of the original content. A stereo depth enhancement algorithm allows common left/right content (e.g. dialog) to be attenuated separately from other content, providing a perceived depth separation between background and foreground audio. Psychoacoustic bass and treble enhancement algorithms achieve a rich, full tone even from originally compressed content, and even with speakers generally unable to play low-frequency sounds. 1.3. Audio Inputs On the analog input side, the device features multiple line-in/microphone inputs, which can be used for analog microphone, or line-in inputs. In addition, digital microphones are also supported. The device provides input gain control, separate volume controls, automatic leveling capability, and programmable microphone boost to smooth input recording. A programmable silence “floor” or “threshold” can be set to minimize background noise. 1.4. On-Chip PLLs Beyond audio processing, the ACS422Mx00 also provides a higher level of system integration. It contains a low-power, low-jitter clock synthesizer developed for portable systems to replace multiple crystals and crystal oscillators. 4 PLLs provide internal timing and five high-quality, high-frequency clock outputs for other major elements of a portable system. Using a single fundamental mode crystal, the ACS422Mx00 can generate a reference output, and selectable outputs (one with spread spectrum) to drive a local applications processor and other peripherals. 4 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2. POWER MANAGEMENT 2.1. Control Registers The ACS422Mx00 has control registers to enable system software to control which functions are active. To minimize power consumption, unused functions should be disabled. To avoid audio artifacts, it is important to enable or disable functions in the correct order. Register Address Bit 7 6 5 0x1A Power Management 1 4 3 2 1 0 Label BSTL BSTR PGAL PGAR ADCL ADCR MICB DIGENB Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Description Analog in Boost Left 0 = Power down, 1 = Power up Analog in Boost Right 0 = Power down, 1 = Power up Analog in PGA Left 0 = Power down, 1 = Power up Analog in PGA Right 0 = Power down, 1 = Power up ADC Left 0 = Power down,1 = Power up ADC Right 0 = Power down. 1 = Power up MICBIAS 0 = Power down, 1 = Power up Master clock disable 0: master clock enabled, 1: master clock disabled Table 1. Power Management Register 1 Register Address Bit 7 6 5 0x1B Power Management 2 4 3 2 1 0 Label D2S HPL HPR SPKL SPKR INSELL INSELR VREF Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Description Analog in D2S AMP 0 = Power down, 1 = Power up LHP Output Buffer + DAC 0 = Power down, 1 = Power up RHP Output Buffer + DAC 0 = Power down, 1 = Power up LSPK Output Buffer 0 = Power down, 1 = Power up RSPK Output Buffer 0 = Power down, 1 = Power up Analog in Select Mux Left 0 = Power down, 1 = Power up Analog in Select Mux Right 0 = Power down, 1 = Power up VREF (necessary for all other functions) 0 = Power down, 1 = Power up Table 2. Power Management Register 2 5 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2.2. Stopping the Master Clock In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by setting the DIGENB bit (R25, bit 0). Register Address 0x1A Power Management 1 Bit 0 Label DIGENB Type RW Default 0 Description Master clock disable 0 = master clock enabled, 1 = master clock disabled Table 3. Power Management Register1 -- Master Clock Disable Note: Before DIGENB can be set, the control bits ADCL, ADCR, HPL, HPR, SPKL, and SPKR must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain fading to complete. Any failure to follow this procedure may cause pops or, if less than 1mS, may prevent the DACs and ADCs from re-starting correctly. 6 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3. OUTPUT AUDIO PROCESSING PA Treble DACCRAM ADh Mono Mix 18h DMonoMix DC Removal PA Bass 3-D DACCRAM 96h DACCRAM AFh DACCRAM 00h – 3Dh DACCRAM 40h – 7Dh DACCRAM 80h – 96h DACCRAM 97h – ADh DACCRAM AEh – AFh Prescale 1 EQ1 EQ1 Coefficients EQ2 Coefficients Bass Coefficients Treble Coefficients 3D Coefficients Prescale 2 EQ2 Deemphasis Compressor Limiter Expander 33h – 38h GAIN 0 to 46.5 dB In 1.5 dB steps Expander Phase Invert DAC Volume Mute 0 to -95.25dB 0.375dB steps DAC_L/R 41h DC-Coef_Sel 18h De-emphasis 18h DACPOL 2Dh – 32h Limiter 26h – 2Ch Compressor 25h Control 04h – 05h 18h DAC Volume 39h FXCTRL 3Ah – 3Ch WRITE 3Dh – 3Fh READ 40h 8Ah ADDRESS STATUS Mute 02h +12 to -77.25 dB In 0.75 dB steps 1Ch – 1Eh 88h Digital PWM controller Thermal Limit BTL/HP Power Management 1Bh SPKR VOL BTL SPKR HP Volume (Digital) Audio Processing Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander LEFT DAC Antipop HP HP Out Left +6 to -88.5 dB In 0.75 dB steps DAC_L/R Interpolation 00h HP Detect RIGHT HP Volume (Digital) +6 to -88.5 dB In 0.75 dB steps DAC Antipop HP HP Out Right 01h HP Detect Figure 2. Output Audio Processing 3.1. DC Removal Before processing, a DC removal filter removes the DC component from the incoming audio data. The DC removal filter is programmable. Register Address Bit 7:3 Label – Type R Default 0 Description Reserved for future use. 0: dc_coef = 24'h100000; //2^^-3 = 0.125 1: dc_coef = 24'h040000; 2: dc_coef = 24'h010000; 3: dc_coef = 24'h004000; 4: dc_coef = 24'h001000; 5: dc_coef = 24'h000400; 6: dc_coef = 24'h000100; //2^^-15 = 0.00030517 7: dc_coef = 24'h000040; //2^^-17 R65 (41h) DCOFSEL 2:0 - RW 5 Table 4. DC_COEF_SEL Register Register Address Bit 7:6 5:4 R31 (1Fh) CONFIG0 3:2 1 0 Label ASDM[1:0] DSDM[1:0] RSVD dc_bypass RSVD Type RW RW R RW R Default 10h 10h 0h 0 0 Description ADC Modulator Rate DAC Modulator Rate Reserved for future use. 1 = bypass DC removal filter (WARNING DC content can damage BTL output) Reserved Table 5. CONFIG0 Register 7 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.2. Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. The Volume Update bits control the updating of volume control data; when a bit is written as ‘0’, the Left Volume control associated with that bit is updated whenever the left volume register is written and the Right Volume control is updated when ever the right volume register is written. When a bit is written as ‘1’, the left volume data is placed into an internal holding register when the left volume register is written and both the left and right volumes are updated when the right volume register is written. This enables a simultaneous left and right volume update Register Address Bit 7 6 5 4 Label ADCFade DACFade RSVD INVOLU Type RW RW R RW Default 1 1 0 0 Description 1 = volume fades between old/new value 0 = volume/mute changes immediately 1 = volume fades between old/new value 0 = volume/mute changes immediately Reserved for future use. 0 = Left input volume updated immediately 1 = Left input volume held until right input volume register written. 0 = Left ADC volume updated immediately 1 = Left ADC volume held until right ADC volume register written. 0 = Left DAC volume updated immediately 1 = Left DAC volume held until right DAC volume register written. 0 = Left speaker volume updated immediately 1 = Left speaker volume held until right speaker volume register written. 0 = Left headphone volume updated immediately 1 = Left headphone volume held until right headphone volume register written. R10 (0Ah) VUCTL 3 ADCVOLU RW 0 2 DACVOLU RW 0 1 SPKVOLU RW 0 0 HPVOLU RW 0 Table 6. Volume Update Control Register The output path may be muted automatically when a long string of zero data is received. The length of zeros is programmable and a detection flag indicates when a stream of zero data has been detected. Register Address Bit 7 6 R33 (21h) Gain Control (GAINCTL) 5:4 3 2 1 0 7 Label zerodet_flag RSVD zerodetlen RSVD auto_mute RSVD RSVD zerodet_flag Type R R RW R RW R R R Default 0 0 2 0 1 0 0 0 Description 1 = zero detect length exceeded. Reserved for future use. Enable mute if input consecutive zeros exceeds this length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples Reserved for future use. 1 = auto mute if detect long string of zeros on input Reserved for future use. Reserved for future use. 1 = zero detect length exceeded. Table 7. Gain Control Register 8 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.3. Digital DAC Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. Register Address Bit Label Type Default Description Left DAC Volume Level 0000 0000 = Digital Mute 0000 0001 = -95.25dB 0000 0010 = -94.875dB ... 0.375dB steps up to 1111 1111 = 0dB Note: If DACVOLU is set, this setting will take effect after the next write to the Right Input Volume register. Right DAC Digital Volume Level 0000 0000 = Digital Mute 0000 0001 = -95.25dB 0000 0010 = -94.875dB ... 0.375dB steps up to 1111 1111 = 0dB R4 (04h) Left DAC Volume Control 7:0 DACVOL_L [7:0] RW FF (0dB) R5 (05h) Right DAC Volume Control 7:0 DACVOL_R [7:0] RW FF (0dB) Table 8. DAC Volume Control Registers 3.4. Parametric Equalizer The ACS422Mx00 has a dual 6-band digital parametric equalizer to enable fine tuning of the audio response and preferences for a given system. Each EQ may be enabled or disabled independently. Typically one EQ will be used for speaker compensation and disabled when only headphones are in use while the other EQ is used to alter the audio to make it more pleasing to the listener. This function operates on the digital audio data before it is converted back to analog by the audio DACs. In all, 186 bytes of memory are required to store the parameters for each equalizer: each filter requires 5, 24-bit coefficients. There are 6 filters per channel, requiring a total of 180 bytes of EQ coefficient RAM. Two additional 24-bit values per channel store the prescale value, resulting in 372 bytes total, described later. Rather than having all 372 bytes be in the I2C address space of the device, access to the EQ ram occurs through the Control/Status registers. 3.4.1. Prescaler & Equalizer Filter The Equalizer Filter consists of a Prescaler and 6 cascaded 6-tap IIR Filters. The Prescaler allows the input to be attenuated prior to the EQ filters in case the EQ filters introduce gain, and would thus clip if not prescaled. IDT provides a tool to enable an audio designer to determine appropriate coefficients for the equalizer filters. The filters enable the implementation of a 6-band parametric equalizer with selectable frequency bands, gain, and filter characteristics (high, low, or bandpass). DATA IN EQ Filter 0 eq_prescale EQ Filter 1 EQ Filter 2 EQ Filter 3 EQ Filter 4 EQ Filter 5 DATA OUT Figure 3. Prescaler & EQ Filters 9 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The figure below shows the structure of a single EQ filter. The a(0) tap is always normalized to be equal to 1 (400000h). The remaining 5 taps are 24-bit twos compliment format programmable coefficients. (-2 coefficient  +2). x(n) y(n) Z-1 b(0) *2 b(0) Z-1 Z-1 b(1) *2 b(1) a(1) *2 a(1) Z-1 b(2) a(2) Figure 4. 6-Tap IIR Equalizer Filter 3.4.2. • EQ Registers EQ Filter Enable Register Register Address Bit 7 Label EQ2_EN Type R/W Default 0 Description EQ bank 2 enable 0 = second EQ bypassed, 1 = second EQ enabled EQ2 band enable. When the EQ is enabled the following EQ stages are executed. 0 - Prescale only 1 - Prescale and Filter Band 0 ... 6 - Prescale and Filter Bands 0 to 5 7 - RESERVED EQ bank 1 enable 0 = first EQ bypassed, 1 = first EQ enabled EQ1 band enable. When the EQ is enabled the following EQ stages are executed. 0 - Prescale only 1 - Prescale and Filter Band 0 ... 6 - Prescale and Filter Bands 0 to 5 7 - RESERVED 6:4 EQ2_BE[2:0] R/W 0 R32 (20h) CONFIG1 3 EQ1_EN R/W 0 2:0 EQ1_BE[2:0] R/W 0 Table 9. CONFIG1 Register • DACCRAM Read Data (0x3D–LO, 0x3E–MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI) Registers These two 24-bit registers provide the 24-bit data holding registers used when doing indirect writes/reads to the DAC 10 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Coefficient RAM. Register Address R58 (3Ah) DACCRAM_WRITE_LO R59 (3Bh) DACCRAM_WRITE_MID R60 (3Ch) DACCRAM_WRITE_HI R61 (3Dh) DACCRAM_READ_LO Bit 7:0 Label DACCRWD[7:0] Type R/W Default 0 Description Low byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. Middle byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. High byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. Low byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. Middle byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. High byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. 7:0 DACCRWD[15:8] R/W 0 7:0 DACCRWD[23:16] R/W 0 7:0 DACCRRD[7:0] R 0 R62 (3Eh) DACCRAM_READ_MID 7:0 DACCRRD[15:8] R 0 R63 (3Fh) DACCRAM_READ_HI 7:0 DACCRRD[23:16] R 0 Table 10. DACCRAM Read/Write Registers • DACCRAM Address Register This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the DAC Coefficient RAM. Register Address Bit Label Type Default Description Contains the address (between 0 and 255) of the DACCRAM to be accessed by a read or write. This is not a byte address--it is the address of the 24-bit data item to be accessed from the DACCRAM.This address is automatically incremented after writing to DACCRAM_WRITE_HI or reading from DACCRAM_READ_HI (and the 24 bit data from the next RAM location is fetched.) R64 (40h) DACCRADDR 7:0 DACCRADD R/W 0 Table 11. DACCRAM Address Register • DACCRAM STATUS Register This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM. Register Address R138 (8Ah) DACCRSTAT Bit 7 6:0 Label DACCRAM_Busy RSVD Type R R Default 0 0 Description 1 = read/write to DACCRAM in progress, cleared by HW when done. Reserved Table 12. DACCRAM Status Register 3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM The DAC Coefficient RAM is a single port 161x24 synchronous RAM. It is programmed indirectly through the Control Bus in the following manner: 11 V1.0 07/11 ACS422MX00 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. Write target address to DACCRAM_ADDR register. 2. Write D7:0 to the DACCRAM_WRITE_LO register 3. Write D15:8 to the DACCRAM_WRITE_MID register 4. Write D23:16 to the DACCRAM_WRITE_HI register 5. On successful receipt of the DACCRAM_WRITE_HI data, the part will automatically start a write cycle. The DACCRAM_Busy bit will be set high to indicate that a write is in progress. 6. On completion of the internal write cycle, the DACCRAM_Busy bit will be 0 (when operating the control interface at high speeds - TBD - software must poll this bit to ensure the write cycle is complete before starting another write cycle.) 7. The bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consecutive EQ RAM locations. Generic write operation S SDA SCL 2.5 uS min. EQ RAM read finished; EQ Read Data valid (time not fixed) write EQ RAM Write Lo S writing 1 reigster DA0 W AS RA7 RA1 RA0 AS RD7 RD0 AS multiple write cycle RD7 RD0 AS multiple write cycle P DA6 RD7 RD0 AS register write here 28 SCL cycles 70 uS min. EQ RAM write req = 1 write EQ RAM Write Mid RD[7:0] write EQ RAM Write Hi RD[7:0] S register write here EQ RAM Write Lo updated here EQ RAM write must have finished here; EQ_A ++ write EQ RAM Write Lo write EQ RAM Write Mid RD[7:0] EQ RAM write operation write EQ RAM Address S EQ_A updated; EQ RAM read req = 1 DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] RD[7:0] repeat for multiple consecutive EQ RAM locations writes Figure 5. DAC Coefficient RAM Write Sequence Reading back a value from the DACCRAM is done in this manner: 1. Write target address to DACCRAM_ADDR register.(EQ data is pre-fetched for read even if we don’t use it) 2. Start (or repeat start) a write cycle to DACCRAM_READ_LO and after the second byte (register address) is acknowledged, go to step 3. (Do not complete the write cycle.) 3. Signal a repeat start and indicate a read operation 4. Read D7:0 (register address incremented after ack by host) 5. Read D15:8 (register address incremented after ack by host) 6. Read D23:16 (register address incremented and next EQ location pre-fetched after ack by host) 7. The host stops the bus cycle To repeat a read cycle for consecutive EQ RAM locations: 1. Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating DACCRAM_RD_LO as the target address. 2. After the second byte is acknowledged, signal a repeated start. 3. Indicate a read operation 4. Read the DACCRAM_READ_LO register as described in step 4 5. Read the DACCRAM_READ_MID register as described in step 5 6. Read the DACCRAM_READ_HI register as described in step 6 12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 7. Repeat steps 8-13 as desired Generic read operation read 1 register multiple read cycle R AS RD7 RD0 AM RD7 RD0 AM multiple read cycle RD7 RD0 NM Sr SDA SCL EQ_A updated; EQ RAM read req = 1 RA7 RA1 RA0 AS DA6 DA0 NACK from master to end read cycle 30 SCL cycles 75 uS min. write EQ RAM Read Lo, truncate EQ RAM Data must be valid here EQ_A ++; prefetch data write EQ RAM Read Lo, truncate PS EQ RAM Data must be valid here EQ RAM read operation write EQ RAM Address P S S Sr read EQ RAM Data Lo DA[6:0], R RD[7:0] read EQ RAM Data Mid RD[7:0] read EQ RAM Data Hi RD[7:0] Sr read EQ RAM Data Lo DA[6:0], R RD[7:0] DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] DA[6:0], W RA[7:0] repeat for multiple consecutive EQ RAM locations reads 1. 2. 3. 4. 5. DA: Device Address RA: Register Address EQ_A: EQ RAM Address RD: Register Data A S : Acknowledge from slave 6. A M : Acknowledge from master 7. N M : Not Acknowledge from master 8. S: Start 9. S r: Repeated Start 10. P: Stop Figure 6. DAC Coefficient RAM Read Sequence • DACCRAM EQ Addresess EQ 0 Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 Channel 0 Coefficients EQ_COEF_0F0_B0 EQ_COEF_0F0_B1 EQ_COEF_0F0_B2 EQ_COEF_0F0_A1 EQ_COEF_0F0_A2 EQ_COEF_0F1_B0 EQ_COEF_0F1_B1 EQ_COEF_0F1_B2 EQ_COEF_0F1_A1 EQ_COEF_0F1_A2 EQ_COEF_0F2_B0 EQ_COEF_0F2_B1 EQ_COEF_0F2_B2 EQ_COEF_0F2_A1 EQ_COEF_0F2_A2 EQ_COEF_0F3_B0 EQ_COEF_0F3_B1 EQ_COEF_0F3_B2 EQ_COEF_0F3_A1 Addr 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 Channel 1 Coefficients EQ_COEF_1F0_B0 EQ_COEF_1F0_B1 EQ_COEF_1F0_B2 EQ_COEF_1F0_A1 EQ_COEF_1F0_A2 EQ_COEF_1F1_B0 EQ_COEF_1F1_B1 EQ_COEF_1F1_B2 EQ_COEF_1F1_A1 EQ_COEF_1F1_A2 EQ_COEF_1F2_B0 EQ_COEF_1F2_B1 EQ_COEF_1F2_B2 EQ_COEF_1F2_A1 EQ_COEF_1F2_A2 EQ_COEF_1F3_B0 EQ_COEF_1F3_B1 EQ_COEF_1F3_B2 EQ_COEF_1F3_A1 Addr 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 Channel 0 Coefficients EQ_COEF_2F0_B0 EQ_COEF_2F0_B1 EQ_COEF_2F0_B2 EQ_COEF_2F0_A1 EQ_COEF_2F0_A2 EQ_COEF_2F1_B0 EQ_COEF_2F1_B1 EQ_COEF_2F1_B2 EQ_COEF_2F1_A1 EQ_COEF_2F1_A2 EQ_COEF_2F2_B0 EQ_COEF_2F2_B1 EQ_COEF_2F2_B2 EQ_COEF_2F2_A1 EQ_COEF_2F2_A2 EQ_COEF_2F3_B0 EQ_COEF_2F3_B1 EQ_COEF_2F3_B2 EQ_COEF_2F3_A1 EQ1 Addr 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 Channel 1 Coefficients EQ_COEF_3F0_B0 EQ_COEF_3F0_B1 EQ_COEF_3F0_B2 EQ_COEF_3F0_A1 EQ_COEF_3F0_A2 EQ_COEF_3F1_B0 EQ_COEF_3F1_B1 EQ_COEF_3F1_B2 EQ_COEF_3F1_A1 EQ_COEF_3F1_A2 EQ_COEF_3F2_B0 EQ_COEF_3F2_B1 EQ_COEF_3F2_B2 EQ_COEF_3F2_A1 EQ_COEF_3F2_A2 EQ_COEF_3F3_B0 EQ_COEF_3F3_B1 EQ_COEF_3F3_B2 EQ_COEF_3F3_A1 13 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC EQ 0 Addr 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Channel 0 Coefficients EQ_COEF_0F3_A2 EQ_COEF_0F4_B0 EQ_COEF_0F4_B1 EQ_COEF_0F4_B2 EQ_COEF_0F4_A1 EQ_COEF_0F4_A2 EQ_COEF_0F5_B0 EQ_COEF_0F5_B1 EQ_COEF_0F5_B2 EQ_COEF_0F5_A1 EQ_COEF_0F5_A2 EQ_PRESCALE0 Addr 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Channel 1 Coefficients EQ_COEF_1F3_A2 EQ_COEF_1F4_B0 EQ_COEF_1F4_B1 EQ_COEF_1F4_B2 EQ_COEF_1F4_A1 EQ_COEF_1F4_A2 EQ_COEF_1F5_B0 EQ_COEF_1F5_B1 EQ_COEF_1F5_B2 EQ_COEF_1F5_A1 EQ_COEF_1F5_A2 EQ_PRESCALE1 Addr 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F Channel 0 Coefficients EQ_COEF_2F3_A2 EQ_COEF_2F4_B0 EQ_COEF_2F4_B1 EQ_COEF_2F4_B2 EQ_COEF_2F4_A1 EQ_COEF_2F4_A2 EQ_COEF_2F5_B0 EQ_COEF_2F5_B1 EQ_COEF_2F5_B2 EQ_COEF_2F5_A1 EQ_COEF_2F5_A2 EQ_PRESCALE2 EQ1 Addr 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Channel 1 Coefficients EQ_COEF_3F3_A2 EQ_COEF_3F4_B0 EQ_COEF_3F4_B1 EQ_COEF_3F4_B2 EQ_COEF_3F4_A1 EQ_COEF_3F4_A2 EQ_COEF_3F5_B0 EQ_COEF_3F5_B1 EQ_COEF_3F5_B2 EQ_COEF_3F5_A1 EQ_COEF_3F5_A2 EQ_PRESCALE3 Table 13. DACCRAM EQ Addresess • DACCRAM Bass/Treble Addresses Addr 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D Bass Coefficients1 BASS_COEF_EXT1_B0 BASS_COEF_EXT1_B1 BASS_COEF_EXT1_B2 BASS_COEF_EXT1_A1 BASS_COEF_EXT1_A2 BASS_COEF_EXT2_B0 BASS_COEF_EXT2_B1 BASS_COEF_EXT2_B2 BASS_COEF_EXT2_A1 BASS_COEF_EXT2_A2 BASS_COEF_NLF_M12 BASS_COEF_NLF_M2 BASS_COEF_LMT_B0 BASS_COEF_LMT_B1 Addr 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 Treble Coefficients TREB_COEF_EXT1_B0 TREB_COEF_EXT1_B1 TREB_COEF_EXT1_B2 TREB_COEF_EXT1_A1 TREB_COEF_EXT1_A2 TREB_COEF_EXT2_B0 TREB_COEF_EXT2_B1 TREB_COEF_EXT2_B2 TREB_COEF_EXT2_A1 TREB_COEF_EXT2_A2 TREB_COEF_NLF_M1 TREB_COEF_NLF_M2 TREB_COEF_LMT_B0 TREB_COEF_LMT_B1 Addr 0xAE 0xAF 3D Coefficients 3D_COEF 3D_MIX Table 14. DACCRAM Bass/Treble Addresses 14 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Addr 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 Bass Coefficients1 BASS_COEF_LMT_B2 BASS_COEF_LMT_A1 BASS_COEF_LMT_A2 BASS_COEF_CTO_B0 BASS_COEF_CTO_B1 BASS_COEF_CTO_B2 BASS_COEF_CTO_A1 BASS_COEF_CTO_A2 BASS_MIX Addr 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD Treble Coefficients TREB_COEF_LMT_B2 TREB_COEF_LMT_A1 TREB_COEF_LMT_A2 TREB_COEF_CTO_B0 TREB_COEF_CTO_B1 TREB_COEF_CTO_B2 TREB_COEF_CTO_A1 TREB_COEF_CTO_A2 TREB_MIX Addr 3D Coefficients Table 14. DACCRAM Bass/Treble Addresses 1.All B0 coefficients are set to unity (400000h) by default. All others, including M1 and M2, are 0 by default. 2.NLF coefficients (M1, M2) have a range defined as +/-8, with 1 sign bit, 3 integer bits, and 20 fraction bits. So, unity for these values is 100000h. This is as opposed to the rest of the coefficient RAM, which has a range defined as +/-2, with 1 sign bit, 1 integer bit, and 22 fraction bits. 3.5. Gain and Dynamic Range Control The gain for a given channel is controlled by the DACVOL registers. The range of gain supported is from -95.625db to 0db in 0.375db steps. If the result of the gain multiply step would result in overflow of the 24-bit output word width, the output is saturated at the max positive or negative value. In addition to simple gain control, the ACS422Mx00 also provides sophisticated dynamic range control. The dynamic range control processing element implements limiting, dynamic range compression, and dynamic range expansion functions. 3.6. Limiter The Limiter function will limit the output of the DSP module to the Class-D and DAC modules. If the signal is greater than 0dB it will saturate at 0dB as the final processing step within the DSP module. There are times when the user may intentionally want the output Limiter to perform this saturation, for example +6dB of gain applied within the DSP gain control and then limited to 0dB when output to the Class-D module would result in a clipped signal driving the speaker output. This clipped signal would obviously contribute to increased distortion on the speaker output which from the user listening perception it would “sound louder”. At other times, the system implementor may wish to protect speakers from overheating or provide hearing protection by intentionally limiting the output level before full scale is reached. A limit threshold, independent of the compressor threshold is provided for this purpose. It is expected that the limit threshold is set to a higher level than the compressor threshold. 15 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7. Compressor 0 -2 -4 -6 -8 -10 -12 Compressed Output Range -14 Natural Output Range -16 -18 -20 -22 -22 -20 -18 -16 -14 -12 -10 Input (dBFS) -8 -6 -4 -2 0 Expanded Output Range Limit Threshold Compressor Threshold Limit Threshold: -6 dBFS Compressor Threshold: -14.25 dBFS Expander Threshold: -18 dBFS Compressor Ratio: Expander Ratio: 3:1 1:2 Output (dBFS) Expander Threshold Figure 7. Gain Compressor, Output vs Input The traditional compressor algorithm provides two functions simultaneously (depending on signal level). For higher level signals, it can provide a compression function to reduce the signal level. For lower level signals, it can provide an expansion function for either increasing dynamic range or noise gating. The compressor monitors the signal level and, if the signal is higher than a threshold, will reduce the gain by a programmed ratio to restrict the dynamic range. Limiting is an extreme example of the compressor where, as the input signal level is increased, the gain is decreased to maintain a specific output level. In addition to limiting the bandwidth of the compressed audio, it is common for compressed audio to also compress the dynamic range of the audio. The expansion function in the ACS422Mx00 can help restore the original dynamics to the audio. The expander is a close relative of the compressor. Rather than using signal dependent gain to restrict the dynamic range, the expander uses signal dependent gain to expand the dynamic range. Thus if a signal level is below a particular threshold, the expander will reduce the gain even further to extend the dynamic range of the material. 16 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.1. Configuration This compressor limiter provides the following configurable parameters. • Compressor • Threshold – The threshold above which the compressor will reduce the dynamic range of the audio in the compression region. • Ratio – The ratio between the input dynamic range and the output dynamic range. For example, a ratio of 3 will reduce an input dynamic range of 9db to 3db. • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the compressor. • Release Time – The amount of time that changes in gain are smoothed over during the release phase of the compressor. • Makeup gain – Used to increase the overall level of the compressed audio. Limiter • Threshold – The threshold above which the limiter will reduce the dynamic range of the audio in the compression region. • Target – The limit of the output level (typically set to the same as threshold). • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the limiter. • Release Time – The amount of time that changes in gain are smoothed over during the release phase of the limiter. Expander • Threshold – The threshold below which the expander will increase the dynamic range of the audio. • Ratio – The ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. For example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db. • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the expander • Release Time - The amount of time that changes in gain are smoothed over during the release phase of the expander. Two level detection algorithms • RMS – Use an RMS measurement for the level. • Peak – Use a peak measurement for the level. • • • 3.7.2. Controlling parameters In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are: • Compressor/limiter • Threshold – -40db to 0db relative to full scale. • Ratio – 1 to 20 • Attack Time – typically 0 to 500ms • Release Time – typically 25ms to 2 seconds • Makeup gain – 0 to 40db 17 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Expander • Threshold – -30 to -60 dB • Ratio – 1 to 6 • Attack Time – same as above • Release Time – same as above. Two level detection algorithms • RMS • Peak • 3.7.3. Overview A basic block diagram of the compressor is shown below: Audio In Audio Out Level Detector Gain Calc Attack/ release filter Peak or RMS Compare to Thresholds Lowpass filter Gains based on Calc Gain Attack and release Figure 8. Compressor block diagram As this diagram shows, there are 3 primary components of the compressor. 1. Level Detector: The level detector, oddly enough, detects the level of the incoming signal. Since the comp/limiter is designed to work on blocks of signals, the level detector will either find the peak value of the block of samples to be processed or the rms level of the samples within a block. 2. Gain Calculation: The gain calculation block is responsible for taking the output of the level detector and calculating a target gain based on that level and the compressor and expander thresholds. The compressor recalculates the target gain value every block, typically every 10ms. • The gain calculation operates in 3 regions: • Linear region – If the level is higher than the expander threshold and lower than the compression threshold, then the gain is 1.0 • Compression region – When the level is higher than the compressor threshold, then the comp/limiter is in the compression region. The gain is a function of the compressor ratio and the signal level. • Expansion region – When the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. In this region, the gain is a function of the signal level and the expansion ratio. • Compression region gain calculation: In the compression region, the gain calculation is: Atten(in db) = (1-1/ratio)(threshold(in db) – level(in db); • For example, • Ratio = 4:1 compression • Threshold = -16db • Level = -4 db 18 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The required attenuation is: 9db or a gain coefficient of 0.1259. Translating this calculation from log space to linear yields the formula: Gain =(level/threshold)1/ratio*(threshold/level) • Expansion region gain calculation: In the expansion region, the attenuation calculation is: Atten(in db) = (1 - ratio)(threshold-level); • For example, • Ratio = 3:1 • Threshold = -40db • Level = -44 db The resulting attenuation required is 8db or a gain value of 0.1585. The linear equation for calculating the gain is: Gain =(level/threshold)ratio*(threshold/level) • State Transitions: In addition to calculating the new gain for the compressor, the gain calculation block will also select the filter coefficient for the attack/release filter. The rules for selecting the coefficient are as follows: In the compression region: • If the gain calculated is less than the last gain calculated (more compression is being applied), then the filter coefficient is the compressor attack. • If the gain calculated is more than the last gain calculated (less compression), the filter coefficient is the compressor release. • In the expansion region: • If the calculated gain is less than the last gain calculated (closing expander, the filter coefficient is the expander attack. • If the calculated gain is more than the last gain calculated, the filter coefficient is the expander release. In the linear region: • Modify gain until a gain of 1.0 is obtained. • If the last non-linear state was compression, use the compressor release. • If the last non-linear state was expansion, use the expander attack. 3. Attack/Release filter: In order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. In the PC-based comp/limiter, this is achieved using a simple tracking lowpass filter to smooth out the abrupt transitions. The calculation (using the coefficient (coeff) selected by the gain block) is: Filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; This creates a exponential ramp from the current gain value to the new value. 19 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.4. • Limiter/Compressor Registers Bit 7:5 4 Label RSVD Lvl_Mode Type R RW Default 0h 0 Reserved CLE Level Detection Mode 0 = Average 1 = Peak Window width selection for level detection: 0 = equivalent of 512 samples of selected Base Rate (~10-16ms) 1 = equivalent of 64 samples of selected Base Rate (~1.3-2ms) 1 = enable expander 1 = enable limiter 1 = enable compressor Description General compressor/limiter/expander control Register Address R37 (25h) CLECTL 3 WindowSel RW 0 2 1 0 Exp_en Limit_en Comp_en RW RW RW 0 0 0 Table 15. CLECTL Register • Compressor/Limiter/Expander make-up gain Register Address R38 (26h) MUGAIN Bit 7:5 4:0 Label RSVD CLEMUG[4:0] Type R RW Default 0h 0h Reserved 0dB..46.5dB in 1.5dB steps Description Table 16. MUGAIN Register • Compressor Threshold Register Address R39 (27h) COMPTH Bit 7:0 Label COMPTH[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 17. COMPTH Register • Compressor ratio register Register Address Bit 7:5 R40 (28h) CMPRAT Label RSVD Type R Default 000 Reserved Compressor Ratio 00h = Reserved 01h = 1.5:1 02h..14h = 2:1..20:1 15h..1Fh = Reserved Description 4:0 CMPRAT[4:0] RW 00h Table 18. CMPRAT Register • Compressor Attack Time Constant Register (Low) Register Address R41 (29h) CATKTCL Bit 7:0 Label CATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a compressor attack phase. Table 19. CATKTCL Register 20 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Compressor Attack Time Constant Register (High) Register Address R42 (2Ah) CATKTCH Bit 7:0 Label CATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a compressor attack phase. Table 20. CATKTCH Register • Compressor Release Time Constant Register (Low) Register Address R43 (2Bh) CRELTCL Bit 7:0 Label CRELTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a compressor release phase. Table 21. CRELTCL Register • Compressor Release Time Constant Register (High) Register Address R44 (2Ch) CRELTCH Bit 7:0 Label CRELTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a compressor release phase. Table 22. CRELTCH Register • Limiter Threshold Register Register Address R45 (2Dh) LIMTH Bit 7:0 Label LIMTH[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 23. LIMTH Register • Limiter Target Register Register Address R46 (2Eh) LIMTGT Bit 7:0 Label LIMTGT[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 24. LIMTGT Register • Limiter Attack Time Constant Register (Low) Register Address R47 (2Fh) LATKTCL Bit 7:0 Label LATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a limiter attack phase. Table 25. LATKTCL Register • Limiter Attack Time Constant Register (High) Register Address R48 (30h) LATKTCH Bit 7:0 Label LATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a limiter attack phase. Table 26. LATKTCH Register • Limiter Release Time Constant Register (Low) Register Address R49 (31h) LRELTCL Bit 7:0 Label LRELTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a limiter release phase. Table 27. LRELTCL Register 21 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Limiter Release Time Constant Register (High) Register Address R50 (32h) LRELTCH Bit 7:0 Label LRELTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a limiter release phase. Table 28. LRELTCH Register 3.7.5. • Expander Registers Bit 7:0 Label EXPTH[7:0] Type RW Default 00h Description Expander threshold: 0..95.625dB in 0.375dB steps Expander Threshold Register Register Address R51 (33h) EXPTH Table 29. EXPTH Register • Expander Ratio Register Register Address R52 (34h) EXPRAT Bit 7:3 Label RSVD EXPRAT[2:0] Type R RW Default 00h 000 Reserved Expander Ratio 0h..1h = Reserved 2h..7h = 1:2..1:7 Description Table 30. EXPRAT Register • Expander Attack Time Constant Register (Low) Register Address R53 (35h) XATKTCL Bit 7:0 Label XATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a expander attack phase. Table 31. XATKTCL Register • Expander Attack Time Constant Register (High) Register Address R54 (36h) XATKTCH Bit 7:0 Label XATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a expander attack phase. Table 32. XATKTCH Register • Expander Release Time Constant Register (Low) Register Address R55 (37h) XRELTCL Bit 7:0 Label XRELTC[7:0] Type RW Default 0 Description Low byte of the time constant used to ramp to a new gain value during a expander release phase. Table 33. XRELTCL Register • Expander Release Time Constant Register (High) Register Address R56 (38h) XRELTCH Bit 7:0 Label XRELTC[15:8] Type RW Default 0 Description High byte of the time constant used to ramp to a new gain value during a expander release phase. Table 34. XRELTCH Register 22 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.8. Output Effects The ACS422Mx00 offers Bass enhancement, Treble enhancement, Stereo Depth enhancement. The output effects processing is outlined in the following sections.l Register Address Bit 7:5 4 3 R57 (39h) FXCTL 2 1 0 Label RSVD 3DEN TEEN TNLFBYP BEEN BNLFBYP Type R RW RW RW RW RW Default 000 0 0 0 0 0 Reserved 3D Enhancement Enable 0 = Disabled 1 = Enabled Treble Enhancement Enable 0 = Disabled 1 = Enabled Treble Non-linear Function Bypass: 0 = Enabled 1 = Bypassed Bass Enhancement Enable 0 = Disabled 1 = Enabled Bass Non-linear Function Bypass: 0 = Enabled 1 = Bypassed Description Table 35. FX Control Register 3.9. Stereo Depth (3-D) Enhancement The ACS422Mx00 has a digital depth enhancement option to artificially increase the separation between the left and right channels, by enabling the attenuation of the content common to both channels. The amount of attenuation is programmable within a range. The input is prescaled (fixed) before summation to prevent saturation. The 3-D enhancement algorithm is a tried and true algorithm that uses two principles. 1. If the material common to the two channels is removed, then the speakers will sound more 3-D. 2. If the material for the opposite channel is presented to the current channel inverted, it will tend to cancel any material from the opposite channel on the current ear. For example, if the material from the right is presented to the left ear inverted, it will cancel some of the material from the right ear that is leaking into the right ear. Left Left Right Right Figure 9. 3-D Channel Inversion Note: 3D_Mix specifies the amount of the common signal that is subtracted from the left and right channels. This number is a fractional amount between 0 and 1. For proper operation, this value is typically negative. 23 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.10. Psychoacoustic Bass Enhancement One of the primary audio quality issues with small speaker systems is their inability to reproduce significant amounts of energy in the bass region (below 200Hz). While there is no magic mechanism to make a speaker reproduce frequencies that it is not capable of, there are mechanisms for fooling the ear into thinking that the bass material is being heard. The psychoacoustic bass processor relies on a psychoacoustic principle called “missing fundamental”. If the human ear hears a proper series of harmonics for a particular bass note, the listener will hear the fundamental of that series, even if it is not present. A processing algorithm using this principle allows for improving the apparent low frequency response of an audio system below what it is actually capable of. Below is a diagram of the implementation of this algorithm. . Cutoff Filter Extract Filter NLF Limit Filter Figure 10. Bass Enhancement This implementation is composed of 5 major components: 1. Extract filter – This filter extracts the bass information that the speaker system can't reproduce. This is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves. 2. NLF – This is a Nonlinear function that is used to generate the harmonics of the fundamentals in the extracted audio. More on this function later. 3. Limit Filter – This filter will limit the amplitude of the harmonics generated to prevent the harmonics from creating noise in the midrange. Too many harmonics will spill into the mid range and be heard as unwanted buzzing. Too few and the psychoacoustic effect is not reached. The exact composition of this filter is still or be determined. A 2nd order filter is currently sufficient for the NLF function employed. 4. Mixing – This structure allows mixing of the generated harmonics and the original material. 5. Cutoff Filter – This filter is used to remove all material below the cutoff frequency of the speaker systems. This includes the fundamentals used to create the psychoacoustic effect, since they can't be reproduced. This is a 2nd order high pass filter. 3.10.1. Non-linear function A new, more pleasing, non-linear function has been found. In particular, the new non-linear function involves two separate operations: Taking the sine of the input signal, which generates odd harmonics, half wave rectifying the signal, which generates even harmonics. The transfer function is shown below: // Sine part Temp = in*mix1; Temp = clip(Temp); // Mix 1 can be between 0 and 8.0 // clip this result to between -1 and 1 24 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 07/11 ACS422MX00 ACS422Mx00 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SineOut = sin(Temp*pi/2); usage. // Take the sine of this, the pi/2 provides full // half wave rectifier part Temp = in*mix2; Temp = clip(temp); halfOut = rect(in); // Mix 2 can be between 0 and 8.0 // clip this result //Half wave rectify input; // if input