ACS522D01AHGYYX

DATASHEET PORTABLE CONSUMER CODEC LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC ACS522D01 FEATURES • High fidelity 24-bit stereo CODEC • • DAC 102dB SNR; THD+N better than -82dB ADC 90dB SNR, THD + N better than -80dB 3D stereo enhancement Dual (cascaded) stereo 6-band parametric equalizers Programmable Compressor/Limiter/Expander Psychoacoustic Bass and Treble enhancement processing 35 mW output power (16) Charge-pump allows true ground centered outputs SNR of 102dB DESCRIPTION The ACS522D01 is a low-power, high-fidelity integrated CODEC targeted at portable applications such as tablet computers, personal navigation devices, portable projectors and speaker docks. In addition to a high-fidelity low-power CODEC, the device integrates a true cap-less headphone amplifier. Beyond high-fidelity for portable systems, the device offers an enriched “audio presence” through built-in audio processing capability. • Built in audio controls and processing • • • • • On-chip true cap-less headphone driver • • • TARGET APPLICATIONS • • • • • Tablet Computers Portable Navigation Devices Personal Media Players Portable Projectors Speaker Docks • • I2S data interface Microphone/line-in interface • • • 2 Analog inputs for analog microphone or line-in support 1 Digital input for digital microphone support Automatic level control • • On-chip low-jitter PLL for audio timing Low power with built in power management • • • 1.7 V CODEC supports 1Vrms Very low standby and no-signal power consumption 1.8V digital / 1.7V analog supply for low power • • 2-wire (I2C compatible) control interface 41-ball WLCSP RoHs package 1 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522x01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC TABLE OF CONTENTS 1. OVERVIEW ................................................................................................................................ 7 1.1. Block Diagram ...................................................................................................................................7 1.2. Audio Outputs ....................................................................................................................................7 1.3. Audio Inputs .......................................................................................................................................8 2. POWER MANAGEMENT .......................................................................................................... 9 2.1. Control Registers ...............................................................................................................................9 2.2. Stopping the Master Clock .................................................................................................................9 3. OUTPUT AUDIO PROCESSING ............................................................................................. 10 3.1. DC Removal ....................................................................................................................................10 3.2. Volume Control ................................................................................................................................11 3.3. Digital DAC Volume Control .............................................................................................................12 3.4. Parametric Equalizer .......................................................................................................................12 3.4.1. Prescaler & Equalizer Filter ...............................................................................................12 3.4.2. EQ Registers ......................................................................................................................13 3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................15 3.5. Gain and Dynamic Range Control ...................................................................................................18 3.6. Limiter ..............................................................................................................................................18 3.7. Compressor .....................................................................................................................................19 3.7.1. Configuration ......................................................................................................................20 3.7.2. Controlling parameters .......................................................................................................20 3.7.3. Overview ............................................................................................................................21 3.7.4. Limiter/Compressor Registers ............................................................................................23 3.7.5. Expander Registers ...........................................................................................................25 3.8. Output Effects ..................................................................................................................................26 3.9. Stereo Depth (3-D) Enhancement ...................................................................................................26 3.10. Psychoacoustic Bass Enhancement ..............................................................................................27 3.11. Treble Enhancement .....................................................................................................................27 3.12. Mute and De-Emphasis .................................................................................................................28 3.13. Mono Operation and Phase Inversion ...........................................................................................29 3.13.1. DAC Control Register .....................................................................................................29 3.13.2. Interpolation and Filtering ................................................................................................30 3.14. Analog Outputs ..............................................................................................................................31 3.14.1. Headphone Output ...........................................................................................................31 3.15. Other Output Capabilities ..............................................................................................................32 3.15.1. Audio Output Control .......................................................................................................32 3.15.2. Headphone Switch ...........................................................................................................32 3.15.3. Headphone Operation ......................................................................................................33 3.15.4. EQ Operation ...................................................................................................................33 4. INPUT AUDIO PROCESSING ................................................................................................. 34 4.1. Analog Inputs ...................................................................................................................................34 4.1.1. Input Registers ...................................................................................................................35 4.2. Mono Mixing and Output Configuration ...........................................................................................35 4.2.1. ADC Registers ...................................................................................................................36 4.3. Microphone Bias ..............................................................................................................................37 4.3.1. Microphone Bias Control Register .....................................................................................37 4.4. Programmable Gain Control ............................................................................................................37 4.4.1. Input PGA Software Control Register. ...............................................................................38 4.5. ADC Digital Filter .............................................................................................................................38 4.5.1. ADC Signal Path Control Register .....................................................................................40 4.5.2. ADC High Pass Filter Enable modes .................................................................................40 4.6. Digital ADC Volume Control .............................................................................................................40 4.6.1. ADC Digital Registers ........................................................................................................41 4.7. Automatic Level Control (ALC) ........................................................................................................41 4.7.1. ALC Operation ..................................................................................................................41 4.7.2. ALC Registers ....................................................................................................................43 4.7.3. Peak Limiter .......................................................................................................................44 4.7.4. Input Threshold ..................................................................................................................44 2 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.5 04/11 ACS522X01 ACS522x01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.8. Digital Microphone Support .............................................................................................................44 4.8.1. DMIC Register ...................................................................................................................47 5. DIGITAL AUDIO AND CONTROL INTERFACES ................................................................... 48 5.1. Data Interface ..................................................................................................................................48 5.2. Master and Slave Mode Operation ..................................................................................................48 5.3. Audio Data Formats .........................................................................................................................49 5.4. Left Justified Audio Interface ...........................................................................................................49 5.5. Right Justified Audio Interface (assuming n-bit word length) ...........................................................49 5.6. I2S Format Audio Interface ..............................................................................................................50 5.7. Data Interface Registers ..................................................................................................................50 5.7.1. Audio Data Format Control Register ..................................................................................50 5.7.2. Audio Interface Output Tri-state .........................................................................................51 5.7.3. Audio Interface Bit Clock and LR Clock configuration ........................................................51 5.7.4. Bit Clock and LR Clock Mode Selection ............................................................................52 5.7.5. ADC Output Pin State ........................................................................................................53 5.7.6. Audio Interface Control 3 Register .....................................................................................53 5.8. Bit Clock Mode .................................................................................................................................53 5.9. Control Interface ..............................................................................................................................54 5.9.1. Register Write Cycle ..........................................................................................................54 5.9.2. Multiple Write Cycle ...........................................................................................................55 5.9.3. Register Read Cycle ..........................................................................................................55 5.9.4. Multiple Read Cycle ...........................................................................................................56 5.9.5. Device Addressing and Identification .................................................................................56 6. AUDIO CLOCK GENERATION ............................................................................................... 58 6.1. Internal Clock Generation (ACLK) ...................................................................................................58 6.2. ACLK Clocking and Sample Rates ..................................................................................................58 6.3. DAC/ADC Modulator Rate Control ...................................................................................................59 7. CHARACTERISTICS ............................................................................................................... 61 7.1. Electrical Specifications ...................................................................................................................61 7.1.1. Absolute Maximum Ratings ...............................................................................................61 7.1.2. Recommended Operating Conditions ................................................................................61 7.2. Device Characteristics .....................................................................................................................62 7.3. Typical Power Consumption ............................................................................................................64 7.4. Low Power Mode Power Consumption ............................................................................................64 8. REGISTER MAP ...................................................................................................................... 65 9. PINOUT ................................................................................................................................... 67 9.1. Pin Tables ........................................................................................................................................68 9.1.1. Power Pins .........................................................................................................................68 9.1.2. Reference Pins ..................................................................................................................68 9.1.3. Analog Input Pins ...............................................................................................................69 9.1.4. Analog Output Pins ............................................................................................................69 9.1.5. Data and Control Pins ........................................................................................................69 9.1.6. Clock and No Connect Pins ...............................................................................................70 10. PACKAGE INFORMATION ................................................................................................... 70 10.1. Package Diagram ..........................................................................................................................70 11. APPLICATION INFORMATION ............................................................................................ 71 12. ORDERING INFORMATION ................................................................................................. 71 13. DISCLAIMER ......................................................................................................................... 71 14. DOCUMENT REVISION HISTORY ....................................................................................... 72 3 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.5 04/11 ACS522X01 ACS522x01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF FIGURES Figure 1. Block Diagram ...................................................................................................................................7 Figure 2. Output Audio Processing ................................................................................................................10 Figure 3. Prescaler & EQ Filters ....................................................................................................................12 Figure 4. 6-Tap IIR Equalizer Filter ................................................................................................................13 Figure 5. DAC Coefficient RAM Write Sequence ...........................................................................................15 Figure 6. DAC Coefficient RAM Read Sequence ...........................................................................................16 Figure 7. Gain Compressor, Output vs Input .................................................................................................19 Figure 8. Compressor block diagram .............................................................................................................21 Figure 9. 3-D Channel Inversion ....................................................................................................................26 Figure 10. Bass Enhancement .......................................................................................................................27 Figure 11. Treble Enhancement ....................................................................................................................28 Figure 12. Interpolation and Filtering .............................................................................................................30 Figure 13. Input Audio Processing .................................................................................................................34 Figure 14. Mic Bias ........................................................................................................................................37 Figure 15. ADC Filter Data path .....................................................................................................................38 Figure 16. ADC Input processing ...................................................................................................................39 Figure 17. ALC Operation ..............................................................................................................................41 Figure 18. Single Digital Microphone (data is ported to both left and right channels) ....................................46 Figure 19. Stereo Digital Microphone Configuration ......................................................................................47 Figure 20. Master mode .................................................................................................................................48 Figure 21. Slave mode ...................................................................................................................................48 Figure 22. Left Justified Audio Interface (assuming n-bit word length) ..........................................................49 Figure 23. Right Justified Audio Interface (assuming n-bit word length) ........................................................49 Figure 24. I2S Justified Audio Interface (assuming n-bit word length) ...........................................................50 Figure 25. Bit Clock mode ..............................................................................................................................54 Figure 26. 2-Wire Serial Control Interface ......................................................................................................55 Figure 27. Multiple Write Cycle ......................................................................................................................55 Figure 28. Read Cycle ...................................................................................................................................56 Figure 29. Multiple Read Cycle ......................................................................................................................56 Figure 30. ACSS522D01 Pinout ....................................................................................................................67 Figure 31. Package Drawing ..........................................................................................................................70 4 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.5 04/11 ACS522X01 ACS522x01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF TABLES Table 1. Power Management Register 1 ..........................................................................................................9 Table 2. Power Management Register 2 ..........................................................................................................9 Table 3. Power Management Register1 -- Master Clock Disable ....................................................................9 Table 4. DC_COEF_SEL Register .................................................................................................................10 Table 5. CONFIG0 Register ...........................................................................................................................10 Table 6. Volume Update Control Register .....................................................................................................11 Table 7. Gain Control Register .......................................................................................................................11 Table 8. DAC Volume Control Registers ........................................................................................................12 Table 9. CONFIG1 Register ...........................................................................................................................13 Table 10. DACCRAM Read/Write Registers .................................................................................................14 Table 11. DACCRAM Address Register ........................................................................................................14 Table 12. DACCRAM Status Register ...........................................................................................................14 Table 13. DACCRAM EQ Addresess .............................................................................................................17 Table 14. DACCRAM Bass/Treble Addresses ...............................................................................................17 Table 15. CLECTL Register ...........................................................................................................................23 Table 16. MUGAIN Register ..........................................................................................................................23 Table 17. COMPTH Register .........................................................................................................................23 Table 18. CMPRAT Register ..........................................................................................................................23 Table 19. CATKTCL Register ........................................................................................................................23 Table 20. CATKTCH Register ........................................................................................................................24 Table 21. CRELTCL Register ........................................................................................................................24 Table 22. CRELTCH Register ........................................................................................................................24 Table 23. LIMTH Register ..............................................................................................................................24 Table 24. LIMTGT Register ............................................................................................................................24 Table 25. LATKTCL Register .........................................................................................................................24 Table 26. LATKTCH Register ........................................................................................................................24 Table 27. LRELTCL Register .........................................................................................................................24 Table 28. LRELTCH Register ........................................................................................................................25 Table 29. EXPTH Register .............................................................................................................................25 Table 30. EXPRAT Register ..........................................................................................................................25 Table 31. XATKTCL Register .........................................................................................................................25 Table 32. XATKTCH Register ........................................................................................................................25 Table 33. XRELTCL Register .........................................................................................................................25 Table 34. XRELTCH Register ........................................................................................................................25 Table 35. FX Control Register ........................................................................................................................26 Table 36. CNVRTR1 Register ........................................................................................................................29 Table 37. HPVOL L/R Registers ....................................................................................................................31 Table 38. Power Management 2 Register ......................................................................................................32 Table 39. Additional Control Register ............................................................................................................33 Table 40. Headphone Operation ....................................................................................................................33 Table 41. EQ Operation .................................................................................................................................33 Table 42. Input Software Control Register .....................................................................................................35 Table 43. INMODE Register ..........................................................................................................................36 Table 44. CNVRTR0 Register ........................................................................................................................36 Table 45. AIC2 Register .................................................................................................................................36 Table 46. Power Management 1 Register - Mic Bias Enable .........................................................................37 Table 47. INVOL L&R Registers ....................................................................................................................38 Table 48. CNVRTR0 Register ........................................................................................................................40 Table 49. ADC HPF Enable ...........................................................................................................................40 Table 50. L/R ADC Digital Volume Registers .................................................................................................41 Table 51. ALC Control Registers ...................................................................................................................43 Table 52. NGATE Register ............................................................................................................................44 Table 53. DMIC Clock ....................................................................................................................................45 Table 54. Valid Digital Mic Configurations .....................................................................................................46 Table 55. DMICCTL Register .........................................................................................................................47 Table 56. AIC1 Register .................................................................................................................................50 Table 57. AIC2 Register .................................................................................................................................51 Table 58. Bit Clock and LR Clock Mode Selection .........................................................................................52 5 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.5 04/11 ACS522X01 ACS522x01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Table 59. ADC Data Output pin state ............................................................................................................53 Table 60. AIC3 Register .................................................................................................................................53 Table 61. Master Mode BCLK Frequency Control Register ...........................................................................54 Table 62. DEVADRl Register .........................................................................................................................56 Table 63. DEVID H&L Registers ....................................................................................................................57 Table 64. REVID Register ..............................................................................................................................57 Table 65. RESET Register .............................................................................................................................57 Table 66. ADCSR Register ............................................................................................................................58 Table 67. DACSR Register ............................................................................................................................59 Table 68. ACLK and Sample Rates ...............................................................................................................59 Table 69. CONFIG0 Register .........................................................................................................................60 Table 70. SDM Rates .....................................................................................................................................60 Table 71. Electrical Specification: Maximum Ratings ....................................................................................61 Table 72. Recommended Operating Conditions ............................................................................................61 Table 73. Device Characteristics ...................................................................................................................62 Table 74. Typical Power Consumption ..........................................................................................................64 Table 75. Low power mode power consumption ............................................................................................64 Table 76. Register Map ..................................................................................................................................65 Table 77. Power Pins .....................................................................................................................................68 Table 78. Reference Pins ..............................................................................................................................68 Table 79. Analog Input Pins ...........................................................................................................................69 Table 80. Analog Output Pins ........................................................................................................................69 Table 81. Data and Control Pins ....................................................................................................................69 Table 82. Clock and No Connect Pins ...........................................................................................................70 6 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V0.5 04/11 ACS522X01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. OVERVIEW 1.1. Block Diagram The ACS522D01 is an advanced low power codec with integrated headphone amplifiers and PLL. To support the design of audio subsystems in a portable device, the ACS522D01 features an intelligent codec architecture with advanced audio processing algorithms, integrated with a true cap-less headphone amplifier, and microphone interface with programmable gain. Clocking VDD_PLL2 VDD_PLL1 CPVDD DVDD_CORE DVDD_IO CAP+ CAPVAVDD 2 PVDD Charge-Pump MCLK PLLs Internal Audio Clock(s) DAC Left Digital Volume DAC Antipop HP HP Out Left I2C_SDA I2C_SCL HP_DET TEST Vref AFILT1 Control AFILT2 DAC Right Digital Volume DAC Antipop HP HP Out Right Audio Processing DACBCLK DACLRCLK DACIN Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander DAC Left DAC Right MUX LIN1 LIN2 RIN1 RIN2 AGND Vref + D2S D2S ADCOUT ADCLRCLK ADCBCLK Source Select Switch -97 to +30 dB In 0.5 dB steps -17 to +30dB in 0.75dB steps Audio Processing +0/+10/+20/+30 dB MUX - LIN1 MUX MUX LIN2 LIN3 D2S + MIC Bias mute VOL ADCL 1 bit AGC Boost LIN1 LIN2 -97 to +30 dB In 0.5 dB steps Automatic Level Control S RIN1 MUX MUX AGC Boost LIN3/DMIC_CLK* Audio Processing mute VOL ADCR 1 bit RIN2 RIN3 D2S RIN1 RIN2 RIN3/DMIC_DAT* -17 to +30dB in 0.75dB steps +0/+10/+20/+30 dB *Digital Microphone Products VSS_PLL VSS_XTAL DVSS AVSS 2 CPGND Figure 1. Block Diagram 1.2. Audio Outputs The ACS522D01 provides a line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones without requiring an external DC blocking capacitor. Each endpoint features independent volume controls, including a soft-mute capability which can slowly ramp up or down the volume changes to avoid unwanted audio artifacts. The ACS522D01 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are enabled when the ACS522D01 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be separately enabled by individual control bits. The digital filter and audio processing block processes the data to provide volume control and numerous sound enhancement algorithms. Two high performance sigma-delta audio DACs convert the digital data into analog. 7 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The digital audio data is converted to oversampled bit streams using 24-bit digital interpolation filters, which then enters sigma-delta DACs, and become converted to high quality analog audio signals. To enhance the sound available from the small, low-power speakers typically found in a portable device, the ACS522D01 provides numerous audio enhancement capabilities. The ACS522D01 features dual, independent, programmable left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. A compressor/limiter features programmable attack and release thresholds, enabling the system designer to attenuate loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be played at a louder volume without distortion. For compressed audio, a programmable expander is available to help restore the dynamic range of the original content. A stereo depth enhancement algorithm allows common left/right content (e.g. dialog) to be attenuated separately from other content, providing a perceived depth separation between background and foreground audio. Psychoacoustic bass and treble enhancement algorithms achieve a rich, full tone even from originally compressed content, and even with speakers generally unable to play low-frequency sounds. 1.3. Audio Inputs On the analog input side, the device features multiple line-in/microphone inputs, which can be used for analog microphone, or line-in inputs. In addition, digital microphones are also supported. The device provides input gain control, separate volume controls, automatic leveling capability, and programmable microphone boost to smooth input recording. A programmable silence “floor” or “threshold” can be set to minimize background noise. 8 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2. POWER MANAGEMENT 2.1. Control Registers The ACS522D01 has control registers to enable system software to control which functions are active. To minimize power consumption, unused functions should be disabled. To avoid audio artifacts, it is important to enable or disable functions in the correct order. Register Address Bit 7 6 5 0x1A Power Management 1 4 3 2 1 0 Label BSTL BSTR PGAL PGAR ADCL ADCR MICB DIGENB Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Description Analog in Boost Left 0 = Power down, 1 = Power up Analog in Boost Right 0 = Power down, 1 = Power up Analog in PGA Left 0 = Power down, 1 = Power up Analog in PGA Right 0 = Power down, 1 = Power up ADC Left ADC Right MICBIAS 0 = Power down,1 = Power up 0 = Power down. 1 = Power up 0 = Power down, 1 = Power up Master clock disable 0: master clock enabled, 1: master clock disabled Table 1. Power Management Register 1 Register Address Bit 7 6 5 0x1B Power Management 2 4:3 2 1 0 Label D2S HPL HPR RSVD INSELL INSELR VREF Type RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 Description Analog in D2S AMP 0 = Power down, 1 = Power up LHP Output Buffer + DAC 0 = Power down, 1 = Power up RHP Output Buffer + DAC 0 = Power down, 1 = Power up Reserved Analog in Select Mux Left 0 = Power down, 1 = Power up Analog in Select Mux Right 0 = Power down, 1 = Power up VREF (necessary for all other functions) 0 = Power down, 1 = Power up Table 2. Power Management Register 2 2.2. Stopping the Master Clock In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by setting the DIGENB bit (R25, bit 0). Register Address 0x1A Power Management 1 Bit 0 Label DIGENB Type RW Default 0 Description Master clock disable 0 = master clock enabled, 1 = master clock disabled Table 3. Power Management Register1 -- Master Clock Disable Note: Before DIGENB can be set, the control bits ADCL, ADCR, HPL and HPR must be set to zero and a waiting time of 100ms must be observed to allow port ramping/gain fading to complete. Any failure to follow this procedure may cause pops or, if less than 1mS, may prevent the DACs and ADCs from re-starting correctly. 9 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3. OUTPUT AUDIO PROCESSING PA Treble DACCRAM ADh DACCRAM 00h – 3Dh DACCRAM 40h – 7Dh DACCRAM 80h – 96h DACCRAM 97h – ADh DACCRAM 96h DACCRAM AFh EQ1 Coefficients EQ2 Coefficients Bass Coefficients Treble Coefficients 3D Coefficients Prescale 2 EQ2 Deemphasis Compressor Limiter Expander GAIN 0 to 46.5 dB In 1.5 dB steps Expander DAC Volume Mute 0 to -95.25dB 0.375dB steps Mono Mix 18h DMonoMix DC Removal PA Bass 3-D DACCRAM AEh – AFh Prescale 1 EQ1 41h DC-Coef_Sel Phase Invert DAC_L/R 39h FXCTRL 3Ah – 3Ch WRITE 3Dh – 3Fh READ 40h 8Ah ADDRESS STATUS 18h De-emphasis 33h – 38h 18h DACPOL 2Dh – 32h Limiter 26h – 2Ch Compressor 25h Control 04h – 05h 18h DAC Volume Mute HP Volume (Digital) Audio Processing Bass/Treble Enhancement SYSTEM EQ SPEAKER EQ 3-D effect Compressor-limiter Dynamic Range Expander LEFT DAC Antipop HP HP Out Left +6 to -88.5 dB In 0.75 dB steps DAC_L/R Interpolation 00h HP Detect RIGHT HP Volume (Digital) +6 to -88.5 dB In 0.75 dB steps DAC Antipop HP HP Out Right 01h HP Detect Figure 2. Output Audio Processing 3.1. DC Removal Before processing, a DC removal filter removes the DC component from the incoming audio data. The DC removal filter is programmable. Register Address Bit 7:3 Label – Type R Default 0 Description Reserved for future use. 0: dc_coef = 24'h100000; //2^^-3 = 0.125 1: dc_coef = 24'h040000; 2: dc_coef = 24'h010000; 3: dc_coef = 24'h004000; 4: dc_coef = 24'h001000; 5: dc_coef = 24'h000400; 6: dc_coef = 24'h000100; //2^^-15 = 0.00030517 7: dc_coef = 24'h000040; //2^^-17 R65 (41h) DCOFSEL 2:0 - RW 5 Table 4. DC_COEF_SEL Register Register Address Bit 7:6 5:4 R31 (1Fh) CONFIG0 3:2 1 0 Label ASDM[1:0] DSDM[1:0] RSVD dc_bypass RSVD Type RW RW R RW R Default 10h 10h 0h 0 0 Description ADC Modulator Rate DAC Modulator Rate Reserved for future use. 1 = bypass DC removal filter (WARNING DC content can damage speakers) Reserved Table 5. CONFIG0 Register 10 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.2. Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. The Volume Update bits control the updating of volume control data; when a bit is written as ‘0’, the Left Volume control associated with that bit is updated whenever the left volume register is written and the Right Volume control is updated when ever the right volume register is written. When a bit is written as ‘1’, the left volume data is placed into an internal holding register when the left volume register is written and both the left and right volumes are updated when the right volume register is written. This enables a simultaneous left and right volume update Register Address Bit 7 6 5 4 R10 (0Ah) VUCTL Label ADCFade DACFade RSVD INVOLU Type RW RW R RW Default 1 1 0 0 Description 1 = volume fades between old/new value 0 = volume/mute changes immediately 1 = volume fades between old/new value 0 = volume/mute changes immediately Reserved for future use. 0 = Left input volume updated immediately 1 = Left input volume held until right input volume register written. 0 = Left ADC volume updated immediately 1 = Left ADC volume held until right ADC volume register written. 0 = Left DAC volume updated immediately 1 = Left DAC volume held until right DAC volume register written. Reserved 0 = Left headphone volume updated immediately 1 = Left headphone volume held until right headphone volume register written. 3 ADCVOLU RW 0 2 1 0 DACVOLU RSVD HPVOLU RW RW RW 0 0 0 Table 6. Volume Update Control Register The output path may be muted automatically when a long string of zero data is received. The length of zeros is programmable and a detection flag indicates when a stream of zero data has been detected. Register Address Bit 7 6 R33 (21h) Gain Control (GAINCTL) 5:4 3 2 1 0 7 Label zerodet_flag RSVD zerodetlen RSVD auto_mute RSVD RSVD zerodet_flag Type R R RW R RW R R R Default 0 0 2 0 1 0 0 0 Description 1 = zero detect length exceeded. Reserved for future use. Enable mute if input consecutive zeros exceeds this length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples Reserved for future use. 1 = auto mute if detect long string of zeros on input Reserved for future use. Reserved for future use. 1 = zero detect length exceeded. Table 7. Gain Control Register 11 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.3. Digital DAC Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level of attenuation is specified by an eight-bit code, ‘DACVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates mute; other values select the number of 0.375dB steps above -95.625dB for the volume level. Register Address Bit Label Type Default Description Left DAC Volume Level 0000 0000 = Digital Mute 0000 0001 = -95.25dB 0000 0010 = -94.875dB ... 0.375dB steps up to 1111 1111 = 0dB Note: If DACVOLU is set, this setting will take effect after the next write to the Right Input Volume register. Right DAC Digital Volume Level 0000 0000 = Digital Mute 0000 0001 = -95.25dB 0000 0010 = -94.875dB ... 0.375dB steps up to 1111 1111 = 0dB R4 (04h) Left DAC Volume Control 7:0 DACVOL_L [7:0] RW FF (0dB) R5 (05h) Right DAC Volume Control 7:0 DACVOL_R [7:0] RW FF (0dB) Table 8. DAC Volume Control Registers 3.4. Parametric Equalizer The ACS522D01 has a dual 6-band digital parametric equalizer to enable fine tuning of the audio response and preferences for a given system. Each EQ may be enabled or disabled independently. In all, 186 bytes of memory are required to store the parameters for each equalizer: each filter requires 5, 24-bit coefficients. There are 6 filters per channel, requiring a total of 180 bytes of EQ coefficient RAM. Two additional 24-bit values per channel store the prescale value, resulting in 372 bytes total, described later. Rather than having all 372 bytes be in the I2C address space of the device, access to the EQ ram occurs through the Control/Status registers. 3.4.1. Prescaler & Equalizer Filter The Equalizer Filter consists of a Prescaler and 6 cascaded 6-tap IIR Filters. The Prescaler allows the input to be attenuated prior to the EQ filters in case the EQ filters introduce gain, and would thus clip if not prescaled. IDT provides a tool to enable an audio designer to determine appropriate coefficients for the equalizer filters. The filters enable the implementation of a 6-band parametric equalizer with selectable frequency bands, gain, and filter characteristics (high, low, or bandpass). DATA IN EQ Filter 0 eq_prescale EQ Filter 1 EQ Filter 2 EQ Filter 3 EQ Filter 4 EQ Filter 5 DATA OUT Figure 3. Prescaler & EQ Filters The figure below shows the structure of a single EQ filter. The a(0) tap is always normalized to be equal to 1 (400000h). The remaining 5 taps are 24-bit twos compliment format programmable coeffi- 12 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC cients. (-2 coefficient  +2). x(n) y(n) Z-1 b(0) *2 b(0) Z-1 Z-1 b(1) *2 b(1) a(1) *2 a(1) Z-1 b(2) a(2) Figure 4. 6-Tap IIR Equalizer Filter 3.4.2. • EQ Registers EQ Filter Enable Register Register Address Bit 7 Label EQ2_EN Type R/W Default 0 Description EQ bank 2 enable 0 = second EQ bypassed, 1 = second EQ enabled EQ2 band enable. When the EQ is enabled the following EQ stages are executed. 0 - Prescale only 1 - Prescale and Filter Band 0 ... 6 - Prescale and Filter Bands 0 to 5 7 - RESERVED EQ bank 1 enable 0 = first EQ bypassed, 1 = first EQ enabled EQ1 band enable. When the EQ is enabled the following EQ stages are executed. 0 - Prescale only 1 - Prescale and Filter Band 0 ... 6 - Prescale and Filter Bands 0 to 5 7 - RESERVED 6:4 EQ2_BE[2:0] R/W 0 R32 (20h) CONFIG1 3 EQ1_EN R/W 0 2:0 EQ1_BE[2:0] R/W 0 Table 9. CONFIG1 Register 13 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • DACCRAM Read Data (0x3D–LO, 0x3E–MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI) Registers These two 24-bit registers provide the 24-bit data holding registers used when doing indirect writes/reads to the DAC Coefficient RAM. Register Address R58 (3Ah) DACCRAM_WRITE_LO R59 (3Bh) DACCRAM_WRITE_MID R60 (3Ch) DACCRAM_WRITE_HI R61 (3Dh) DACCRAM_READ_LO Bit 7:0 Label DACCRWD[7:0] Type R/W Default 0 Description Low byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. Middle byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. High byte of a 24-bit data register, contains the values to be written to the DACCRAM. The address written will have been specified by the DACCRAM Address fields. Low byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. Middle byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. High byte of a 24-bit data register, contains the contents of the most recent DACCRAM address read from the RAM. The address read will have been specified by the DACCRAM Address fields. 7:0 DACCRWD[15:8] R/W 0 7:0 DACCRWD[23:16] R/W 0 7:0 DACCRRD[7:0] R 0 R62 (3Eh) DACCRAM_READ_MID 7:0 DACCRRD[15:8] R 0 R63 (3Fh) DACCRAM_READ_HI 7:0 DACCRRD[23:16] R 0 Table 10. DACCRAM Read/Write Registers • DACCRAM Address Register This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the DAC Coefficient RAM. Register Address Bit Label Type Default Description Contains the address (between 0 and 255) of the DACCRAM to be accessed by a read or write. This is not a byte address--it is the address of the 24-bit data item to be accessed from the DACCRAM.This address is automatically incremented after writing to DACCRAM_WRITE_HI or reading from DACCRAM_READ_HI (and the 24 bit data from the next RAM location is fetched.) R64 (40h) DACCRADDR 7:0 DACCRADD R/W 0 Table 11. DACCRAM Address Register • DACCRAM STATUS Register This control register provides the write/read enable when doing indirect writes/reads to the DAC Coefficient RAM. Register Address R138 (8Ah) DACCRSTAT Bit 7 6:0 Label DACCRAM_Busy RSVD Type R R Default 0 0 Description 1 = read/write to DACCRAM in progress, cleared by HW when done. Reserved Table 12. DACCRAM Status Register 14 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.4.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM The DAC Coefficient RAM is a single port 161x24 synchronous RAM. It is programmed indirectly through the Control Bus in the following manner: 1. Write target address to DACCRAM_ADDR register. 2. Write D7:0 to the DACCRAM_WRITE_LO register 3. Write D15:8 to the DACCRAM_WRITE_MID register 4. Write D23:16 to the DACCRAM_WRITE_HI register 5. On successful receipt of the DACCRAM_WRITE_HI data, the part will automatically start a write cycle. The DACCRAM_Busy bit will be set high to indicate that a write is in progress. 6. On completion of the internal write cycle, the DACCRAM_Busy bit will be 0 (when operating the control interface at high speeds - TBD - software must poll this bit to ensure the write cycle is complete before starting another write cycle.) 7. The bus cycle may be terminated by the host or steps 2-6 may be repeated for writes to consecutive EQ RAM locations. Generic write operation S SDA SCL DA6 DA0 W AS RA7 RA1 writing 1 reigster RA0 AS RD7 RD0 AS multiple write cycle RD7 RD0 AS multiple write cycle P RD7 RD0 AS 2.5 uS min. EQ RAM read finished; EQ Read Data valid (time not fixed) write EQ RAM Write Lo S register write here 28 SCL cycles 70 uS min. EQ RAM write req = 1 write EQ RAM Write Mid RD[7:0] write EQ RAM Write Hi RD[7:0] S register write here EQ RAM Write Lo updated here EQ RAM write must have finished here; EQ_A ++ write EQ RAM Write Lo write EQ RAM Write Mid RD[7:0] EQ RAM write operation write EQ RAM Address S EQ_A updated; EQ RAM read req = 1 DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] RD[7:0] repeat for multiple consecutive EQ RAM locations writes Figure 5. DAC Coefficient RAM Write Sequence Reading back a value from the DACCRAM is done in this manner: 1. Write target address to DACCRAM_ADDR register.(EQ data is pre-fetched for read even if we don’t use it) 2. Start (or repeat start) a write cycle to DACCRAM_READ_LO and after the second byte (register address) is acknowledged, go to step 3. (Do not complete the write cycle.) 3. Signal a repeat start and indicate a read operation 4. Read D7:0 (register address incremented after ack by host) 5. Read D15:8 (register address incremented after ack by host) 6. Read D23:16 (register address incremented and next EQ location pre-fetched after ack by host) 7. The host stops the bus cycle To repeat a read cycle for consecutive EQ RAM locations: 1. Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating DACCRAM_RD_LO as the target address. 2. After the second byte is acknowledged, signal a repeated start. 3. Indicate a read operation 4. Read the DACCRAM_READ_LO register as described in step 4 15 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5. Read the DACCRAM_READ_MID register as described in step 5 6. Read the DACCRAM_READ_HI register as described in step 6 7. Repeat steps 8-13 as desired Generic read operation read 1 register multiple read cycle R AS RD7 RD0 AM RD7 RD0 AM multiple read cycle RD7 RD0 NM Sr SDA SCL EQ_A updated; EQ RAM read req = 1 RA7 RA1 RA0 AS DA6 DA0 NACK from master to end read cycle 30 SCL cycles 75 uS min. write EQ RAM Read Lo, truncate EQ RAM Data must be valid here EQ_A ++; prefetch data write EQ RAM Read Lo, truncate PS EQ RAM Data must be valid here EQ RAM read operation write EQ RAM Address P S S Sr read EQ RAM Data Lo DA[6:0], R RD[7:0] read EQ RAM Data Mid RD[7:0] read EQ RAM Data Hi RD[7:0] Sr read EQ RAM Data Lo DA[6:0], R RD[7:0] DA[6:0], W RA[7:0] RD[7:0] DA[6:0], W RA[7:0] DA[6:0], W RA[7:0] repeat for multiple consecutive EQ RAM locations reads 1. 2. 3. 4. 5. DA: Device Address RA: Register Address EQ_A: EQ RAM Address RD: Register Data A S : Acknowledge from slave 6. A M : Acknowledge from master 7. N M : Not Acknowledge from master 8. S: Start 9. S r: Repeated Start 10. P: Stop Figure 6. DAC Coefficient RAM Read Sequence • DACCRAM EQ Addresess EQ 0 Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 Channel 0 Coefficients EQ_COEF_0F0_B0 EQ_COEF_0F0_B1 EQ_COEF_0F0_B2 EQ_COEF_0F0_A1 EQ_COEF_0F0_A2 EQ_COEF_0F1_B0 EQ_COEF_0F1_B1 EQ_COEF_0F1_B2 EQ_COEF_0F1_A1 EQ_COEF_0F1_A2 EQ_COEF_0F2_B0 EQ_COEF_0F2_B1 EQ_COEF_0F2_B2 EQ_COEF_0F2_A1 EQ_COEF_0F2_A2 EQ_COEF_0F3_B0 EQ_COEF_0F3_B1 Addr 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 Channel 1 Coefficients EQ_COEF_1F0_B0 EQ_COEF_1F0_B1 EQ_COEF_1F0_B2 EQ_COEF_1F0_A1 EQ_COEF_1F0_A2 EQ_COEF_1F1_B0 EQ_COEF_1F1_B1 EQ_COEF_1F1_B2 EQ_COEF_1F1_A1 EQ_COEF_1F1_A2 EQ_COEF_1F2_B0 EQ_COEF_1F2_B1 EQ_COEF_1F2_B2 EQ_COEF_1F2_A1 EQ_COEF_1F2_A2 EQ_COEF_1F3_B0 EQ_COEF_1F3_B1 Addr 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 Channel 0 Coefficients EQ_COEF_2F0_B0 EQ_COEF_2F0_B1 EQ_COEF_2F0_B2 EQ_COEF_2F0_A1 EQ_COEF_2F0_A2 EQ_COEF_2F1_B0 EQ_COEF_2F1_B1 EQ_COEF_2F1_B2 EQ_COEF_2F1_A1 EQ_COEF_2F1_A2 EQ_COEF_2F2_B0 EQ_COEF_2F2_B1 EQ_COEF_2F2_B2 EQ_COEF_2F2_A1 EQ_COEF_2F2_A2 EQ_COEF_2F3_B0 EQ_COEF_2F3_B1 EQ1 Addr 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 Channel 1 Coefficients EQ_COEF_3F0_B0 EQ_COEF_3F0_B1 EQ_COEF_3F0_B2 EQ_COEF_3F0_A1 EQ_COEF_3F0_A2 EQ_COEF_3F1_B0 EQ_COEF_3F1_B1 EQ_COEF_3F1_B2 EQ_COEF_3F1_A1 EQ_COEF_3F1_A2 EQ_COEF_3F2_B0 EQ_COEF_3F2_B1 EQ_COEF_3F2_B2 EQ_COEF_3F2_A1 EQ_COEF_3F2_A2 EQ_COEF_3F3_B0 EQ_COEF_3F3_B1 16 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC EQ 0 Addr 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Channel 0 Coefficients EQ_COEF_0F3_B2 EQ_COEF_0F3_A1 EQ_COEF_0F3_A2 EQ_COEF_0F4_B0 EQ_COEF_0F4_B1 EQ_COEF_0F4_B2 EQ_COEF_0F4_A1 EQ_COEF_0F4_A2 EQ_COEF_0F5_B0 EQ_COEF_0F5_B1 EQ_COEF_0F5_B2 EQ_COEF_0F5_A1 EQ_COEF_0F5_A2 EQ_PRESCALE0 Addr 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Channel 1 Coefficients EQ_COEF_1F3_B2 EQ_COEF_1F3_A1 EQ_COEF_1F3_A2 EQ_COEF_1F4_B0 EQ_COEF_1F4_B1 EQ_COEF_1F4_B2 EQ_COEF_1F4_A1 EQ_COEF_1F4_A2 EQ_COEF_1F5_B0 EQ_COEF_1F5_B1 EQ_COEF_1F5_B2 EQ_COEF_1F5_A1 EQ_COEF_1F5_A2 EQ_PRESCALE1 Addr 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F Channel 0 Coefficients EQ_COEF_2F3_B2 EQ_COEF_2F3_A1 EQ_COEF_2F3_A2 EQ_COEF_2F4_B0 EQ_COEF_2F4_B1 EQ_COEF_2F4_B2 EQ_COEF_2F4_A1 EQ_COEF_2F4_A2 EQ_COEF_2F5_B0 EQ_COEF_2F5_B1 EQ_COEF_2F5_B2 EQ_COEF_2F5_A1 EQ_COEF_2F5_A2 EQ_PRESCALE2 EQ1 Addr 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Channel 1 Coefficients EQ_COEF_3F3_B2 EQ_COEF_3F3_A1 EQ_COEF_3F3_A2 EQ_COEF_3F4_B0 EQ_COEF_3F4_B1 EQ_COEF_3F4_B2 EQ_COEF_3F4_A1 EQ_COEF_3F4_A2 EQ_COEF_3F5_B0 EQ_COEF_3F5_B1 EQ_COEF_3F5_B2 EQ_COEF_3F5_A1 EQ_COEF_3F5_A2 EQ_PRESCALE3 Table 13. DACCRAM EQ Addresess • DACCRAM Bass/Treble Addresses Addr 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A Bass Coefficients1 BASS_COEF_EXT1_B0 BASS_COEF_EXT1_B1 BASS_COEF_EXT1_B2 BASS_COEF_EXT1_A1 BASS_COEF_EXT1_A2 BASS_COEF_EXT2_B0 BASS_COEF_EXT2_B1 BASS_COEF_EXT2_B2 BASS_COEF_EXT2_A1 BASS_COEF_EXT2_A2 BASS_COEF_NLF_M12 Addr 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 Treble Coefficients TREB_COEF_EXT1_B0 TREB_COEF_EXT1_B1 TREB_COEF_EXT1_B2 TREB_COEF_EXT1_A1 TREB_COEF_EXT1_A2 TREB_COEF_EXT2_B0 TREB_COEF_EXT2_B1 TREB_COEF_EXT2_B2 TREB_COEF_EXT2_A1 TREB_COEF_EXT2_A2 TREB_COEF_NLF_M1 Addr 0xAE 0xAF 3D Coefficients 3D_COEF 3D_MIX Table 14. DACCRAM Bass/Treble Addresses 17 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Addr 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 Bass Coefficients1 BASS_COEF_NLF_M2 BASS_COEF_LMT_B0 BASS_COEF_LMT_B1 BASS_COEF_LMT_B2 BASS_COEF_LMT_A1 BASS_COEF_LMT_A2 BASS_COEF_CTO_B0 BASS_COEF_CTO_B1 BASS_COEF_CTO_B2 BASS_COEF_CTO_A1 BASS_COEF_CTO_A2 BASS_MIX Addr 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD Treble Coefficients TREB_COEF_NLF_M2 TREB_COEF_LMT_B0 TREB_COEF_LMT_B1 TREB_COEF_LMT_B2 TREB_COEF_LMT_A1 TREB_COEF_LMT_A2 TREB_COEF_CTO_B0 TREB_COEF_CTO_B1 TREB_COEF_CTO_B2 TREB_COEF_CTO_A1 TREB_COEF_CTO_A2 TREB_MIX Addr 3D Coefficients Table 14. DACCRAM Bass/Treble Addresses 1.All B0 coefficients are set to unity (400000h) by default. All others, including M1 and M2, are 0 by default. 2.NLF coefficients (M1, M2) have a range defined as +/-8, with 1 sign bit, 3 integer bits, and 20 fraction bits. So, unity for these values is 100000h. This is as opposed to the rest of the coefficient RAM, which has a range defined as +/-2, with 1 sign bit, 1 integer bit, and 22 fraction bits. 3.5. Gain and Dynamic Range Control The gain for a given channel is controlled by the DACVOL registers. The range of gain supported is from -95.625db to 0db in 0.375db steps. If the result of the gain multiply step would result in overflow of the 24-bit output word width, the output is saturated at the max positive or negative value. In addition to simple gain control, the ACS522D01 also provides sophisticated dynamic range control. The dynamic range control processing element implements limiting, dynamic range compression, and dynamic range expansion functions. 3.6. Limiter The Limiter function will limit the output of the DSP module to the DAC modules. If the signal is greater than 0dB it will saturate at 0dB as the final processing step within the DSP module. There are times when the user may intentionally want the output Limiter to perform this saturation, for example +6dB of gain applied within the DSP gain control and then limited to 0dB when output to the module would result in a clipped signal driving the speaker output. This clipped signal would obviously contribute to increased distortion on the speaker output which from the user listening perception it would “sound louder”. At other times, the system implementor may wish to protect speakers from overheating or provide hearing protection by intentionally limiting the output level before full scale is reached. A limit threshold, independent of the compressor threshold is provided for this purpose. It is expected that the limit threshold is set to a higher level than the compressor 18 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC threshold. 3.7. Compressor 0 -2 -4 -6 -8 -10 -12 Compressed Output Range -14 Natural Output Range -16 -18 -20 -22 -22 -20 -18 -16 -14 -12 -10 Input (dBFS) -8 -6 -4 -2 0 Expanded Output Range Limit Threshold Compressor Threshold Limit Threshold: -6 dBFS Compressor Threshold: -14.25 dBFS Expander Threshold: -18 dBFS Compressor Ratio: Expander Ratio: 3:1 1:2 Output (dBFS) Expander Threshold Figure 7. Gain Compressor, Output vs Input The traditional compressor algorithm provides two functions simultaneously (depending on signal level). For higher level signals, it can provide a compression function to reduce the signal level. For lower level signals, it can provide an expansion function for either increasing dynamic range or noise gating. The compressor monitors the signal level and, if the signal is higher than a threshold, will reduce the gain by a programmed ratio to restrict the dynamic range. Limiting is an extreme example of the compressor where, as the input signal level is increased, the gain is decreased to maintain a specific output level. In addition to limiting the bandwidth of the compressed audio, it is common for compressed audio to also compress the dynamic range of the audio. The expansion function in the ACS522D01 can help restore the original dynamics to the audio. The expander is a close relative of the compressor. Rather than using signal dependent gain to restrict the dynamic range, the expander uses signal dependent gain to expand the dynamic range. Thus if a signal level is below a particular threshold, the expander will reduce the gain even further to extend the dynamic range of the material. 19 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.1. Configuration This compressor limiter provides the following configurable parameters. • Compressor • Threshold – The threshold above which the compressor will reduce the dynamic range of the audio in the compression region. • Ratio – The ratio between the input dynamic range and the output dynamic range. For example, a ratio of 3 will reduce an input dynamic range of 9db to 3db. • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the compressor. • Release Time – The amount of time that changes in gain are smoothed over during the release phase of the compressor. • Makeup gain – Used to increase the overall level of the compressed audio. Limiter • Threshold – The threshold above which the limiter will reduce the dynamic range of the audio in the compression region. • Target – The limit of the output level (typically set to the same as threshold). • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the limiter. • Release Time – The amount of time that changes in gain are smoothed over during the release phase of the limiter. Expander • Threshold – The threshold below which the expander will increase the dynamic range of the audio. • Ratio – The ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. For example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db. • Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the expander • Release Time - The amount of time that changes in gain are smoothed over during the release phase of the expander. Two level detection algorithms • RMS – Use an RMS measurement for the level. • Peak – Use a peak measurement for the level. • • • 3.7.2. Controlling parameters In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are: • Compressor/limiter • Threshold – -40db to 0db relative to full scale. • Ratio – 1 to 20 • Attack Time – typically 0 to 500ms • Release Time – typically 25ms to 2 seconds • Makeup gain – 0 to 40db 20 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Expander • Threshold – -30 to -60 dB • Ratio – 1 to 6 • Attack Time – same as above • Release Time – same as above. Two level detection algorithms • RMS • Peak • 3.7.3. Overview A basic block diagram of the compressor is shown below: Audio In Audio Out Level Detector Gain Calc Attack/ release filter Peak or RMS Compare to Thresholds Lowpass filter Gains based on Calc Gain Attack and release Figure 8. Compressor block diagram As this diagram shows, there are 3 primary components of the compressor. 1. Level Detector: The level detector, oddly enough, detects the level of the incoming signal. Since the comp/limiter is designed to work on blocks of signals, the level detector will either find the peak value of the block of samples to be processed or the rms level of the samples within a block. 2. Gain Calculation: The gain calculation block is responsible for taking the output of the level detector and calculating a target gain based on that level and the compressor and expander thresholds. The compressor recalculates the target gain value every block, typically every 10ms. • The gain calculation operates in 3 regions: • Linear region – If the level is higher than the expander threshold and lower than the compression threshold, then the gain is 1.0 • Compression region – When the level is higher than the compressor threshold, then the comp/limiter is in the compression region. The gain is a function of the compressor ratio and the signal level. • Expansion region – When the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. In this region, the gain is a function of the signal level and the expansion ratio. • Compression region gain calculation: In the compression region, the gain calculation is: Atten(in db) = (1-1/ratio)(threshold(in db) – level(in db); • For example, • Ratio = 4:1 compression • Threshold = -16db • Level = -4 db 21 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The required attenuation is: 9db or a gain coefficient of 0.1259. Translating this calculation from log space to linear yields the formula: Gain =(level/threshold)1/ratio*(threshold/level) • Expansion region gain calculation: In the expansion region, the attenuation calculation is: Atten(in db) = (1 - ratio)(threshold-level); • For example, • Ratio = 3:1 • Threshold = -40db • Level = -44 db The resulting attenuation required is 8db or a gain value of 0.1585. The linear equation for calculating the gain is: Gain =(level/threshold)ratio*(threshold/level) • State Transitions: In addition to calculating the new gain for the compressor, the gain calculation block will also select the filter coefficient for the attack/release filter. The rules for selecting the coefficient are as follows: In the compression region: • If the gain calculated is less than the last gain calculated (more compression is being applied), then the filter coefficient is the compressor attack. • If the gain calculated is more than the last gain calculated (less compression), the filter coefficient is the compressor release. • In the expansion region: • If the calculated gain is less than the last gain calculated (closing expander, the filter coefficient is the expander attack. • If the calculated gain is more than the last gain calculated, the filter coefficient is the expander release. In the linear region: • Modify gain until a gain of 1.0 is obtained. • If the last non-linear state was compression, use the compressor release. • If the last non-linear state was expansion, use the expander attack. 3. Attack/Release filter: In order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated by the gain calculation block. In the PC-based comp/limiter, this is achieved using a simple tracking lowpass filter to smooth out the abrupt transitions. The calculation (using the coefficient (coeff) selected by the gain block) is: Filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain; This creates a exponential ramp from the current gain value to the new value. 22 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.4. • Limiter/Compressor Registers Bit 7:5 4 Label RSVD Lvl_Mode Type R RW Default 0h 0 Reserved CLE Level Detection Mode 0 = Average 1 = Peak Window width selection for level detection: 0 = equivalent of 512 samples of selected Base Rate (~10-16ms) 1 = equivalent of 64 samples of selected Base Rate (~1.3-2ms) 1 = enable expander 1 = enable limiter 1 = enable compressor Description General compressor/limiter/expander control Register Address R37 (25h) CLECTL 3 WindowSel RW 0 2 1 0 Exp_en Limit_en Comp_en RW RW RW 0 0 0 Table 15. CLECTL Register • Compressor/Limiter/Expander make-up gain Register Address R38 (26h) MUGAIN Bit 7:5 4:0 Label RSVD CLEMUG[4:0] Type R RW Default 0h 0h Reserved 0dB..46.5dB in 1.5dB steps Description Table 16. MUGAIN Register • Compressor Threshold Register Address R39 (27h) COMPTH Bit 7:0 Label COMPTH[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 17. COMPTH Register • Compressor ratio register Register Address Bit 7:5 R40 (28h) CMPRAT Label RSVD Type R Default 000 Reserved Compressor Ratio 00h = Reserved 01h = 1.5:1 02h..14h = 2:1..20:1 15h..1Fh = Reserved Description 4:0 CMPRAT[4:0] RW 00h Table 18. CMPRAT Register • Compressor Attack Time Constant Register (Low) Register Address R41 (29h) CATKTCL Bit 7:0 Label CATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a compressor attack phase. Table 19. CATKTCL Register 23 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Compressor Attack Time Constant Register (High) Register Address R42 (2Ah) CATKTCH Bit 7:0 Label CATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a compressor attack phase. Table 20. CATKTCH Register • Compressor Release Time Constant Register (Low) Register Address R43 (2Bh) CRELTCL Bit 7:0 Label CRELTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a compressor release phase. Table 21. CRELTCL Register • Compressor Release Time Constant Register (High) Register Address R44 (2Ch) CRELTCH Bit 7:0 Label CRELTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a compressor release phase. Table 22. CRELTCH Register • Limiter Threshold Register Register Address R45 (2Dh) LIMTH Bit 7:0 Label LIMTH[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 23. LIMTH Register • Limiter Target Register Register Address R46 (2Eh) LIMTGT Bit 7:0 Label LIMTGT[7:0] Type RW Default 00h Description FFh..00h = 0dB..95.625dB in 0.375dB steps. Table 24. LIMTGT Register • Limiter Attack Time Constant Register (Low) Register Address R47 (2Fh) LATKTCL Bit 7:0 Label LATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a limiter attack phase. Table 25. LATKTCL Register • Limiter Attack Time Constant Register (High) Register Address R48 (30h) LATKTCH Bit 7:0 Label LATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a limiter attack phase. Table 26. LATKTCH Register • Limiter Release Time Constant Register (Low) Register Address R49 (31h) LRELTCL Bit 7:0 Label LRELTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a limiter release phase. Table 27. LRELTCL Register 24 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Limiter Release Time Constant Register (High) Register Address R50 (32h) LRELTCH Bit 7:0 Label LRELTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a limiter release phase. Table 28. LRELTCH Register 3.7.5. • Expander Registers Bit 7:0 Label EXPTH[7:0] Type RW Default 00h Description Expander threshold: 0..95.625dB in 0.375dB steps Expander Threshold Register Register Address R51 (33h) EXPTH Table 29. EXPTH Register • Expander Ratio Register Register Address R52 (34h) EXPRAT Bit 7:3 Label RSVD EXPRAT[2:0] Type R RW Default 00h 000 Reserved Expander Ratio 0h..1h = Reserved 2h..7h = 1:2..1:7 Description Table 30. EXPRAT Register • Expander Attack Time Constant Register (Low) Register Address R53 (35h) XATKTCL Bit 7:0 Label XATKTC[7:0] Type RW Default 00h Description Low byte of the time constant used to ramp to a new gain value during a expander attack phase. Table 31. XATKTCL Register • Expander Attack Time Constant Register (High) Register Address R54 (36h) XATKTCH Bit 7:0 Label XATKTC[15:8] Type RW Default 00h Description High byte of the time constant used to ramp to a new gain value during a expander attack phase. Table 32. XATKTCH Register • Expander Release Time Constant Register (Low) Register Address R55 (37h) XRELTCL Bit 7:0 Label XRELTC[7:0] Type RW Default 0 Description Low byte of the time constant used to ramp to a new gain value during a expander release phase. Table 33. XRELTCL Register • Expander Release Time Constant Register (High) Register Address R56 (38h) XRELTCH Bit 7:0 Label XRELTC[15:8] Type RW Default 0 Description High byte of the time constant used to ramp to a new gain value during a expander release phase. Table 34. XRELTCH Register 25 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.8. Output Effects The ACS522D01 offers Bass enhancement, Treble enhancement, Stereo Depth enhancement. The output effects processing is outlined in the following sections.l Register Address Bit 7:5 4 3 R57 (39h) FXCTL 2 1 0 Label RSVD 3DEN TEEN TNLFBYP BEEN BNLFBYP Type R RW RW RW RW RW Default 000 0 0 0 0 0 Reserved 3D Enhancement Enable 0 = Disabled 1 = Enabled Treble Enhancement Enable 0 = Disabled 1 = Enabled Treble Non-linear Function Bypass: 0 = Enabled 1 = Bypassed Bass Enhancement Enable 0 = Disabled 1 = Enabled Bass Non-linear Function Bypass: 0 = Enabled 1 = Bypassed Description Table 35. FX Control Register 3.9. Stereo Depth (3-D) Enhancement The ACS522D01 has a digital depth enhancement option to artificially increase the separation between the left and right channels, by enabling the attenuation of the content common to both channels. The amount of attenuation is programmable within a range. The input is prescaled (fixed) before summation to prevent saturation. The 3-D enhancement algorithm is a tried and true algorithm that uses two principles. 1. If the material common to the two channels is removed, then the speakers will sound more 3-D. 2. If the material for the opposite channel is presented to the current channel inverted, it will tend to cancel any material from the opposite channel on the current ear. For example, if the material from the right is presented to the left ear inverted, it will cancel some of the material from the right ear that is leaking into the right ear. Left Left Right Right Figure 9. 3-D Channel Inversion Note: 3D_Mix specifies the amount of the common signal that is subtracted from the left and right channels. This number is a fractional amount between 0 and 1. For proper operation, this value is typically negative. 26 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.10. Psychoacoustic Bass Enhancement One of the primary audio quality issues with small speaker systems is their inability to reproduce significant amounts of energy in the bass region (below 200Hz). While there is no magic mechanism to make a speaker reproduce frequencies that it is not capable of, there are mechanisms for fooling the ear into thinking that the bass material is being heard. The psychoacoustic bass processor relies on a psychoacoustic principle called “missing fundamental”. If the human ear hears a proper series of harmonics for a particular bass note, the listener will hear the fundamental of that series, even if it is not present. A processing algorithm using this principle allows for improving the apparent low frequency response of an audio system below what it is actually capable of. Below is a diagram of the implementation of this algorithm. . Cutoff Filter Extract Filter NLF Limit Filter Figure 10. Bass Enhancement This implementation is composed of 5 major components: 1. Extract filter – This filter extracts the bass information that the speaker system can't reproduce. This is a 4th order band pass filter with a typical bandwidth of 1.5 to 2 octaves. 2. NLF – This is a Nonlinear function that is used to generate the harmonics of the fundamentals in the extracted audio. More on this function later. 3. Limit Filter – This filter will limit the amplitude of the harmonics generated to prevent the harmonics from creating noise in the midrange. Too many harmonics will spill into the mid range and be heard as unwanted buzzing. Too few and the psychoacoustic effect is not reached. The exact composition of this filter is still or be determined. A 2nd order filter is currently sufficient for the NLF function employed. 4. Mixing – This structure allows mixing of the generated harmonics and the original material. 5. Cutoff Filter – This filter is used to remove all material below the cutoff frequency of the speaker systems. This includes the fundamentals used to create the psychoacoustic effect, since they can't be reproduced. This is a 2nd order high pass filter. 3.11. Treble Enhancement One of the mechanisms used to limit the bit rate for compressed audio is to first remove high frequency information before compression. When these files are decompressed, this can lead to dull sounding audio. The IDT treble enhancement replaces these lost high frequencies. 27 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The enhanced treble function works much like the enhanced bass, however it's intended use is different. The enhanced treble uses a non linear function to add treble harmonics to a signal that has limited high-frequency bandwidth (such as a low bit rate MP3). In this case, the algorithm makes use of the audio fact that presence of audio between 4-8K is a good predictor of audio between 10K-20K. Extract Filter NLF Limit Filter Figure 11. Treble Enhancement This implementation extracts the high frequency content that is available in the audio, generates harmonics of those frequencies. These harmonics are then summed back into the original signal, providing a brighter sound. This algorithm has 4 components. • • • • Extract Filter– This filter is used to extract the treble between 4-8K. This is 2 2nd order high pass filters. Enhanced Treble Non-Linear Function– Generates high frequency components Limit Filter– This filter limits the harmonics generated by the NLF to prevent any significant aliasing. A second order filter is sufficient. Mixing Network – This simply sums the generated harmonic signals into the original signal. 3.12. Mute and De-Emphasis The ACS522D01 has a Soft Mute function, which is used to gradually attenuate the digital signal volume to zero. The gain returns to its previous setting if the soft mute is removed. At startup, the codec is muted by default; to enable audio play, the mute bit must be cleared to 0. After the equalization filters, de-emphasis may be performed on the audio data to compensate for pre-emphasis that may be included in the audio stream. De-emphasis filtering is only available for 48kHz, 44.1kHz, and 32kHz sample rates. 28 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.13. Mono Operation and Phase Inversion Normal stereo operation converts left and right channel digital audio data to analog in separate DACs. However, it is also possible to have the same signal (left or right) appear on both analog output channels by disabling one channel; alternately, there is a mono-mix mode that mixes the two channels digitally before converting to analog using only one DAC. In this mode, the other DAC is switched off, and the resulting mixed stream signal can appear on both analog output channels. The DAC output defaults to non-inverted. Setting DACPOLL and DACPOLR bits will invert the DAC output phase on the left and right channels. 3.13.1. DAC Control Register Bit 7 6 Label DACPOLR DACPOLL DMONOMIX [1:0] Type RW RW Default 0 0 Description Invert DAC Right signal Invert DAC Left signal DAC mono mix 00: stereo 01: mono ((L/2)+(R/2)) into DACL, ‘0’ into DACR 10: mono ((L/2)+(R/2)) into DACR, ‘0’ into DACL 11: mono ((L/2)+(R/2)) into DACL and DACR Digital Soft Mute 1 = mute 0 = no mute (signal active) De-emphasis Enable 1 = De-emphasis Enabled 0 = No De-emphasis Reserved Register Address 5:4 R24 (18h) CNVRTR1 3 RW 00 DACMU RW 1 2 1:0 DEEMP RSVD RW R 0 00 Table 36. CNVRTR1 Register 29 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.13.2. Interpolation and Filtering AUTO Input Rate = From I2S 8/11.024/12kHz (QX): Input Rate = From I2S 16/22.05/24kHz (HX): Input Rate = 32/44.1/48kHz (1X): Input Rate = 64/88.2/96kHz (2X): 24 2X 22 2X 22 2X 22 2X 20 20X 1 57T FIR-A 8kHz 11.025kHz 12kHz 24 11T FIR-B 16kHz 22.05kHz 24kHz 22 7T FIR-C 32kHz 44.1kHz 48kHz 22 7T FIR-D 64kHz 88.2kHz 96kHz 20 SDM 128kHz 176.4kHz 192kHz 1 To Analog DAC 2.560MHz 3.528MHz 3.840MHz 2X 2X 2X 20X 57T FIR-A 16kHz 22.05kHz 24kHz 24 11T FIR-B 32kHz 44.1kHz 48kHz 22 7T FIR-C 64kHz 88.2kHz 96kHz 22 SDM 128kHz 176.4kHz 192kHz 20 To Analog DAC 2.560MHz 3.528MHz 3.840MHz 1 2X 2X 2X 20X From I2S 32kHz 44.1kHz 48kHz 24 57T FIR-A 2X 64kHz 88.2kHz 96kHz 22 11T FIR-B 2X 128kHz 176.4kHz 192kHz 20 7T FIR-C 20X 256kHz 352.8kHz 384kHz 1 SDM 5.120MHz 7.056MHz 7.680MHz To Analog DAC From I2S 64kHz 88.2kHz 96kHz 57T FIR-A 128kHz 176.4kHz 192kHz 11T FIR-B 256kHz 352.8kHz 384kHz SDM 5.120MHz 7.056MHz 7.680MHz To Analog DAC Full Input Rate = From I2S 8/11.024/12kHz (QX): Input Rate = From I2S 16/22.05/24kHz (HX): Input Rate = 32/44.1/48kHz (1X): Input Rate = 64/88.2/96kHz (2X): 24 2X 22 2X 22 2X 22 2X 20 2X 20 20X 1 57T FIR-A 8kHz 11.025kHz 12kHz 24 11T FIR-B 16kHz 22.05kHz 24kHz 22 7T FIR-C 32kHz 44.1kHz 48kHz 22 7T FIR-D 64kHz 88.2kHz 96kHz 20 7T FIR-E 128kHz 176.4kHz 192kHz 20 SDM 256kHz 352.8kHz 384kHz 1 To Analog DAC 5.120MHz 7.056MHz 7.680MHz 2X 2X 2X 2X 20X 57T FIR-A 16kHz 22.05kHz 24kHz 24 11T FIR-B 32kHz 44.1kHz 48kHz 22 7T FIR-C 64kHz 88.2kHz 96kHz 22 7T FIR-D 128kHz 176.4kHz 192kHz 20 SDM 256kHz 352.8kHz 384kHz 1 To Analog DAC 5.120MHz 7.056MHz 7.680MHz 2X 2X 2X 20X From I2S 32kHz 44.1kHz 48kHz 24 57T FIR-A 2X 64kHz 88.2kHz 96kHz 22 11T FIR-B 2X 128kHz 176.4kHz 192kHz 20 7T FIR-C 20X 256kHz 352.8kHz 384kHz 1 SDM 5.120MHz 7.056MHz 7.680MHz To Analog DAC From I2S 64kHz 88.2kHz 96kHz 57T FIR-A 128kHz 176.4kHz 192kHz 11T FIR-B 256kHz 352.8kHz 384kHz SDM 5.120MHz 7.056MHz 7.680MHz To Analog DAC Half Input Rate = From I2S 8/11.024/12kHz (QX): Input Rate = From I2S 16/22.05/24kHz (HX): Input Rate = 32/44.1/48kHz (1X): Input Rate = 64/88.2/96kHz (2X): 24 2X 22 2X 22 2X 22 2X 20 20X 1 57T FIR-A 8kHz 11.025kHz 12kHz 24 11T FIR-B 16kHz 22.05kHz 24kHz 22 7T FIR-C 32kHz 44.1kHz 48kHz 22 7T FIR-D 64kHz 88.2kHz 96kHz 20 SDM 128kHz 176.4kHz 192kHz 1 To Analog DAC 2.560MHz 3.528MHz 3.840MHz 2X 2X 2X 20X 57T FIR-A 16kHz 22.05kHz 24kHz 24 11T FIR-B 32kHz 44.1kHz 48kHz 22 7T FIR-C 64kHz 88.2kHz 96kHz 22 SDM 128kHz 176.4kHz 192kHz 1 To Analog DAC 2.560MHz 3.528MHz 3.840MHz 2X 2X 20X From I2S 32kHz 44.1kHz 48kHz 24 57T FIR-A 2X 64kHz 88.2kHz 96kHz 22 11T FIR-B 20X 128kHz 176.4kHz 192kHz 1 SDM 2.560MHz 3.528MHz 3.840MHz To Analog DAC From I2S 64kHz 88.2kHz 96kHz 57T FIR-A 128kHz 176.4kHz 192kHz SDM 2.560MHz 3.528MHz 3.840MHz To Analog DAC Figure 12. Interpolation and Filtering 30 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.14. Analog Outputs 3.14.1. Headphone Output The HPOut pins can drive a 16 or 32 headphone or alternately drive a line output. The signal volume of the headphone amplifier can be independently adjusted under software control by writing to HPVOL_L and HPVOL_R. Setting the volume to 0000000 will mute the output driver; the output remains at ground, so that no click noise is produced when muting or un-muting. Gains above 0dB run the risk of clipping large signals. To minimize artifacts such as clicks and zipper noise, the headphone outputs feature a volume fade function that smoothly changes volume from the current value to the target value. 3.14.1.1. Register Address Bit 7 Headphone Volume Control Registers Label RSVD Type R Default 0 Reserved Description R2 (00h) HPVOLL 6:0 HPVOL_L [6:0] RW Left Headphone Volume 1111111 = +6dB 1111110 = +5.25dB … 1110111 1110111 = 0dB (0dB) ... 0000001 = -88.5dB 0000000 = Analog mute Note: If HPVOLU is set, this setting will take effect after the next write to the Right Input Volume register. 0 Reserved Right Headphone Volume 1111111 = +6dB 1111110 = +5.25dB … 1110111 1110111 = 0dB ... 0000001 = -88.5dB 0000000 = Analog mute 7 RSVD R R3 (01h) HPVOLR 6:0 HPVOL_R [6:0] RW Table 37. HPVOL L/R Registers 31 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.15. Other Output Capabilities Each audio analog output can be separately enabled. Disabling outputs serves to reduce power consumption, and is the default state of the device. 3.15.1. Audio Output Control See Power management section. The output enable bits are also power management bits and the outputs will be turned off when disabled. Register Address Bit 7 6 5 4 3 2 1 0 Label D2S HPOutL HPOutR RSVD RSVD INSELL INSELR VREF Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 1 Description Analog in D2S AMP Enable Left Headphone Output Enable Right Headphone Output Enable Reserved Reserved Analog in Select Mux Left Enable Analog in Select Mux Right Enable Voltage reference R27 (1Bh) Power Management (2) Note: A value of “1” indicates the output is enabled; a value of ‘0’ disables the output. Table 38. Power Management 2 Register 3.15.2. Headphone Switch The HPDETECT pin is used to detect connection of a headphone. When headphone insertion is detected, the codec can automatically disable/enable the headphone outputs. Control bits determine the meaning and polarity of the input. In addition to enabling and disabling outputs, the EQ may also be controlled using the HP_DET pin. The 2 EQ filters may be configured so that one EQ is active when the Headphone output is active and the other EQ is active when the Speaker output is active (independent HP and Speaker EQ). One EQ may be enabled only when the Speaker is active and the other EQ may be on when either of the outputs are active (Speaker compensation and USER EQ) or other combinations are possible. Note that the EQ coefficients must be programmed and the EQs must be enabled using their control registers. The HP_DET logic can only disable the EQ filters. 32 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.15.2.1. Register Address Bit 7 Headphone Switch Register Label HPSWEN Type RW Default 0 Description Headphone Switch Enable 0: Headphone switch disabled 1: Headphone switch enabled Headphone Switch Polarity 0: HPDETECT high = headphone 1: HPDETECT high = reserved EQ2 behavior due to headphone output state EQ1 behavior due to headphone output state Reserved Zero Cross Time-out Enable 0: Time-out Disabled 1: Time-out Enabled - volumes updated if no zero cross event has occurred before time-out 6 R29 (1Ch) Additional Control (CTL) 5:4 3:2 1 0 HPSWPOL EQ2SW[1:0] EQ1SW[1:0] RSVD TOEN RW RW RW RW RW 0 00 00 0 0 Table 39. Additional Control Register 3.15.3. Headphone Operation HPSWEN 0 0 0 0 1 1 1 1 1 1 1 1 HPSWPOL X X X X 0 0 0 0 1 1 1 1 HP_DET Pin state X X X X 0 0 1 1 0 0 1 1 HPOut1 0 0 1 1 X X 0 1 0 1 X X Headphone Enabled no no yes yes no no no yes no yes no no 1.HPOut = Logical OR of the HPL and HPR enable (power state) bits Table 40. Headphone Operation 3.15.4. EQ Operation EQnSW0 0 1 0 1 EQ Behavior1 EQ is not disabled due to Headphone logic EQ is disabled when Headphone output is active Reserved Reserved Table 41. EQ Operation 0 0 1 1 EQnSW1 1.EQ must be enabled. EQ behavior is dependent on HP_DET and Output power state programming. 33 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4. INPUT AUDIO PROCESSING 1Ah Mic Bias AGND Vref + MIC Bias ADC Power Management 08h 09h Zero Cross Detect 06h ADC Leftt Digital Volume -71.25 to +24 dB In 0.375 dB steps ADC Output Configuration 1Ah 08h Left input volume -17.25 to +30dB in 0.75dB steps 0Ch Left Boost +0/+10/+20/+30 dB 0Ch Left Input Select LIN1 MUX LIN2 LIN3 D2S mute VOL SRC HPF ADCL PGA Boost Automatic Level Control 18h Mono Mix MUX MUX mute VOL SRC HPF ADCR MUX 1 bit 1 bit S RIN1 RIN2 RIN3 D2S PGA Boost -17.25 to +30dB in 0.75dB steps +0/+10/+20/+30 dB -71.25 to +24 dB In 0.375 dB steps 14h ADC Data Select 16h ADC Polarity 16h HPF enable 09h Right input volume 0Eh ALC Control 0 0Dh Right Boost 0Dh Right Input Select 07h ADC Right Digital Volume MUX 0Fh ALC Control 1 10h 11h 12h ALC Control 2 ALC Control 3 Noise Gate Control + D2S D2S LIN1 LIN2 RIN1 RIN2 0Bh D2S Input Select Figure 13. Input Audio Processing 4.1. Analog Inputs The ACS522D01 provides multiple high impedance, low capacitance AC-coupled analog inputs with an input signal path to the stereo ADCs. Prior to the ADC, there is a multiplexor that allows the system to select which input is in use. Following the mux, there is a programmable gain amplifier and also an optional microphone gain boost. The gain of the PGA can be controlled either by the system, or by the on-chip level control function. The stereo record path can also operate with the two channels mixed to mono either in the analog or digital domains. Signal inputs are biased internally to AVSS but AC coupling capacitors are required when connecting microphones (due to the 2.5V microphone bias) or when offsets would cause unacceptable “zipper noise” or pops when changing PGA or boost gain settings. To avoid audio artifacts, the line inputs are kept biased to analog ground when they are muted or the device is placed into standby mode. 34 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. MUX - V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.1.1. Input Registers Bit Label Type Default Description Left Channel Input Select 00 = LINPUT1 01 = LINPUT2 10 = LINPUT3 11 = D2S Left Channel Microphone Gain Boost 00 = Boost off (bypassed) 01 = 10dB boost 10 = 20dB boost 11 = 30dB boost Reserved Right Channel Input Select 00 = RINPUT1 01 = RINPUT2 10 = RINPUT3 11 = D2S Right Channel Microphone Gain Boost 00 = Boost off (bypassed) 01 = 10dB boost 10 = 20dB boost 11 = 30dB boost Reserved Register Address 7:6 R12 (0Ch) ADC Signal Path Control Left (INSELL) INSEL_L RW 00 5:4 MICBST_L RW 00 3:0 RSVD R 0000 7:6 R13 (0Dh) ADC Signal Path Control Right (INSELR) INSEL_R RW 00 5:4 MICBST_R RW 00 3:0 RSVD R 0000 Table 42. Input Software Control Register 4.2. Mono Mixing and Output Configuration The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono. Mixing can occur either in the input path (analog, before ADC) or after the ADC. MONOMIX determines whether to mix to mono, and where. For analog mono mix, either the left or right channel ADC can be used for the audio stream. The other ADC may be powered off to conserve power. A differential input amplifier may be selected as a mono source to either ADC input. This D2S amplifier can select either Input 1 or Input 2 using the DS bit. The system also has the flexibility to select the data output. ADCDSEL configures the interface, assigning the source of the left and right ADC independently. 35 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.2.1. ADC Registers 4.2.1.1. ADC D2S Input Mode Register Label RSVD DS Type R RW Default 0h 0 Description Reserved Differential Input Select 0: LIN1 - RIN1 1: LIN2 - RIN2 Register Address R11 (0Bh) ADC Input mode (INMODE) Bit 7:1 0 Table 43. INMODE Register 4.2.1.2. Register Address Bit 7 ADC Mono, Filter and Inversion Register Label ADCPOLR Type RW Default 0 Description ADC Right Channel Polarity 0 = normal 1 = inverted ADC Left Channel Polarity 0 = normal 1 = inverted ADC mono mix 00: Stereo 01: Analog Mono Mix (using left ADC) 10: Analog Mono Mix (using right ADC) 11: Digital Mono Mix (ADCL/2 + ADCR/2 on both Left and Right ADC outputs) 1 = Mute ADC High Pass Offset Result 0 = discard offset when HPF disabled 1 = store and use last calculated offset when HPF disabled ADC High Pass Filter Disable (Right) ADC High Pass Filter Disable (Right) 6 ADCPOLL RW 0 R22 (16h) ADC Control (CNVRTR0) 5:4 AMONOMIX [1:0] RW 00 3 2 1 0 ADCMU HPOR ADCHPDR ADCHPDL RW RW RW RW 1 0 0 0 Table 44. CNVRTR0 Register 4.2.1.3. Register Address Bit 7:6 R20 (14h) Audio Interface Control 2 (AIC2) ADC Data Output Configuration Register Label DACDSEL[1:0] Type RW Default 00 Description 00: left DAC = left I2S data; right DAC = right I2S data 01: left DAC = left I2S data; right DAC = left I2S data 10: left DAC = right I2S data; right DAC = right I2S data 11: left DAC = right I2S data; right DAC = left I2S data 00: left I2S data = left ADC; right I2S data = right ADC 01: left I2S data = left ADC; right I2S data = left ADC 10: left I2S data = right ADC; right I2S data = right ADC 11: left I2S data = right ADC; right I2S data = left ADC Interface Tri-state (See Section 9.2.4) Bitclock and LRClock mode (See Section 9.2.4) 5:4 3 2:0 ADCDSEL[1:0] TRI BLRCM RW RW RW 00 0 0 Table 45. AIC2 Register 36 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.3. Microphone Bias The MICBIAS output is used to bias electric type microphones. It provides a low noise reference voltage used for an external resistor biasing network. The MICB control bit is used to enable the output. The MICBIAS can source up to 3mA of current; therefore, the external resistors must be large enough to conform to this limit. 4.3.1. Microphone Bias Control Register Bit 1 Label MICB Type RW Default 0 Description Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Register Address R26 (1Ah) Power Management (1) Table 46. Power Management 1 Register - Mic Bias Enable Internal Mic Voltage + - MICB MICBIAS 2.5V Internal Resistor Internal Resistor AGND Figure 14. Mic Bias 4.4. Programmable Gain Control The Programmable Gain Amplifier (PGA) enables the input signal level to be matched to the ADC input range. Amplifier gain is adjustable across the range +30dB to –17.25dB (using 0.75dB steps). The PGA can be controlled directly by the system software using the Input Volume Control registers (INVOLL and INVOLR), or alternately the Automatic Level Control (ALC) function can automatically control the gain. If the ALC function is used, writing to the Input Volume Control registers has no effect. Left and right input gains are independently adjustable. By controlling the update bit (INVOLU), the left and right gain settings can be simultaneously updated. To eliminate zipper noise, LZCEN and RZCEN bits enable a zero-cross detector to insure changes only occur when the signal is at zero. A time-out for zero-cross is also provided, using TOEN in register R29 (1Dh). Software can also mute the inputs in the analog domain. 37 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.4.1. Input PGA Software Control Register. Bit Label Type Default Description Register Address 7 RSVD RW 0 Left Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Note: If INVOLU is set, this setting will take effect after the next write to the Right Input Volume register. Left Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB .. 0.75dB steps down to 000000 = -17.25dB Note: If INVOLU is set, this setting will take effect after the next write to the Right Input Volume register. Right Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Right Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB .. 0.75dB steps down to 000000 = -17.25dB Zero Cross Time-out Enable 0: Time-out Disabled 1: Time-out Enabled - volumes updated if no zero cross event has occurred before time-out 6 R8 (08h) Left Input Volume (INVOLL) 5:0 IZCL RW 0 INVOL_L [5:0] RW 010111 (0dB) 7 R9 (09h) Right Input Volume (INVOLR) 6 RSVD IZCR RW RW 0 0 5:0 INVOL_R [5:0] RW 010111 (0dB) R28 (1Ch) Additional Control (CTL) 0 TOEN RW 0 Table 47. INVOL L&R Registers 4.5. ADC Digital Filter To provide the correct sampling frequency on the digital audio outputs, ADC filters perform true 24-bit signal processing and convert the raw multi-bit oversampled data from the ADC using the digital filter path illustrated below. Figure 15. ADC Filter Data path 38 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC AUTO Output Rate = From Analog ADC 8/11.025/12kHz (QX): Output Rate = 16/22.05/24kHz (HX): Output Rate = 32/44.1/48kHz (1X): Output Rate = 64/88.2/96kHz (2X): 1 1/80X 17 1/2X 22 1/2X 22 1/2X 24 CIC 5.120MHz 7.056MHz 7.68MHz 1 7T FIR-C 64kHz 88.2kHz 96kHz 17 11T FIR-B 32kHz 44.1kHz 48kHz 22 57T FIR-A 16kHz 22.05kHz 24kHz 24 To I2S 8kHz 11.025kHz 12kHz 1/80X 1/2X 1/2X From Analog ADC 5.120MHz 7.056MHz 7.68MHz 1 CIC 1/80X 64kHz 88.2kHz 96kHz 17 11T FIR-B 1/2X 32kHz 44.1kHz 48kHz 22 57T FIR-A 1/2X 16kHz 22.05kHz 24kHz 24 To I2S From Analog ADC 10.240MHz 14.112MHz 15.360MHz 1 CIC 1/80X 128kHz 176.4kHz 192kHz 17 11T FIR-B 1/2X 64kHz 88.2kHz 96kHz 24 57T FIR-A 32kHz 44.1kHz 48kHz To I2S From Analog ADC 10.240MHz 14.112MHz 15.360MHz CIC 128kHz 176.4kHz 192kHz 57T FIR-A 64kHz 88.2kHz 96kHz To I2S Full Output Rate = From Analog ADC 8/11.025/12kHz (QX): Output Rate = 16/22.05/24kHz (HX): Output Rate = 32/44.1/48kHz (1X): Output Rate = 64/88.2/96kHz (2X): 1 1/80X 17 1/2X 22 1/2X 22 1/2X 22 1/2X 24 CIC 10.240MHz 14.112MHz 15.360MHz 1 7T FIR-D 128kHz 176.4kHz 192kHz 17 7T FIR-C 64kHz 88.2kHz 96kHz 22 11T FIR-B 32kHz 44.1kHz 48kHz 22 57T FIR-A 16kHz 22.05kHz 24kHz 24 To I2S 8kHz 11.025kHz 12kHz 1/80X 1/2X 1/2X 1/2X From Analog ADC 10.240MHz 14.112MHz 15.360MHz 1 CIC 1/80X 128kHz 176.4kHz 192kHz 17 7T FIR-C 1/2X 64kHz 88.2kHz 96kHz 22 11T FIR-B 1/2X 32kHz 44.1kHz 48kHz 24 57T FIR-A 16kHz 22.05kHz 24kHz To I2S From Analog ADC 10.240MHz 14.112MHz 15.360MHz 1 CIC 1/80X 128kHz 176.4kHz 192kHz 17 11T FIR-B 1/2X 64kHz 88.2kHz 96kHz 24 57T FIR-A 32kHz 44.1kHz 48kHz To I2S From Analog ADC 10.240MHz 14.112MHz 15.360MHz CIC 128kHz 176.4kHz 192kHz 57T FIR-A 64kHz 88.2kHz 96kHz To I2S Half Output Rate = From Analog ADC 8/11.025/12kHz (QX): Output Rate = 16/22.05/24kHz (HX): Output Rate = 32/44.1/48kHz (1X): Output Rate = 64/88.2/96kHz (2X): 1 1/80X 17 1/2X 22 1/2X 22 1/2X 24 CIC 5.120MHz 7.056MHz 7.68MHz 1 7T FIR-C 64kHz 88.2kHz 96kHz 17 11T FIR-B 32kHz 44.1kHz 48kHz 22 57T FIR-A 16kHz 22.05kHz 24kHz 24 To I2S 8kHz 11.025kHz 12kHz 1/80X 1/2X 1/2X From Analog ADC 5.120MHz 7.056MHz 7.68MHz 1 CIC 1/80X 64kHz 88.2kHz 96kHz 17 11T FIR-B 1/2X 32kHz 44.1kHz 48kHz 24 57T FIR-A 16kHz 22.05kHz 24kHz To I2S From Analog ADC 5.120MHz 7.056MHz 7.68MHz 1 CIC 1/80X 64kHz 88.2kHz 96kHz 17 57T FIR-A 32kHz 44.1kHz 48kHz To I2S From Analog ADC 5.120MHz 7.056MHz 7.68MHz CIC 64kHz 88.2kHz 96kHz To I2S Figure 16. ADC Input processing The ADC digital filters contain a software-selectable digital high pass filter. When the high-pass filter is enabled, the dc offset is continuously calculated and subtracted from the input signal. The HPOR bit enables the last calculated DC offset value to be stored when the high-pass filter is disabled; this value will then continue to be subtracted from the input signal. To provide support for calibration, the stored and subtracted value will not change unless the high-pass filter is enabled even if the DC value is changed. The high pass filter may be enabled separately for each of the left and right channels. The output data format can be programmed by the system. This allows stereo or mono recording streams at both inputs. Software can change the polarity of the output signal. 39 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.5.1. ADC Signal Path Control Register Bit Label Type Default Description Register Address 7 6 ADCPOLR ADCPOLL RW RW 0 0 0 = Right polarity not inverted 1 = Right polarity inverted 0 = Left polarity not inverted 1 = Left polarity inverted ADC mono mix 00: Stereo 01: Analog Mono Mix (using left ADC) 10: Analog Mono Mix (using right ADC) 11: Digital Mono Mix 1 = Mute ADC High Pass Offset Result 0 = discard offset when HPF disabled 1 = store and use last calculated offset when HPF disabled ADC High Pass Filter Disable (Right) ADC High Pass Filter Disable (Right) R22 (16h) ADC Control (CNVRTR0) 5:4 AMONOMIX [1:0] ADCMU HPOR ADCHPDR ADCHPDL RW 00 3 2 1 0 RW RW RW RW 1 0 0 0 Table 48. CNVRTR0 Register 4.5.2. ADCHPDR ADC High Pass Filter Enable modes ADCHPDL High Pass Mode 0 0 1 1 0 1 0 1 High-pass filter enabled on left and right channels High-pass filter disabled on left channel, enabled on right channel High-pass filter enabled on left channel, disabled on right channel High-pass filter disabled on left and right channels Table 49. ADC HPF Enable 4.6. Digital ADC Volume Control The ADC volume can be controlled digitally, across a gain and attenuation range of -71.25dB to +24dB (0.375dB steps). The level of attenuation is specified by an eight-bit code ‘ADCVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates mute; other values describe the number of 0.375dB steps above -71.25dB. The ADCVOLU bit controls the updating of digital volume control data. When ADCVOLU is written as ‘0’, the ADC digital volume is immediately updated with the ADCVOL_L data when the Left ADC Digital Volume register is written. When ADCVOLU is set to ‘1’, the ADCVOL_L data is held in an internal holding register until the Right ADC Digital Volume Register is written. 40 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.6.1. ADC Digital Registers Bit Label Type Default Description Register Address R6 (06h) Left ADC Digital Volume 7:0 ADCVOL_L [7:0] RW Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -71.25dB 10111111 0000 0010 = -70.875dB (0dB) ... 0.375dB steps up to 1111 1111 = +24dB Note: If ADCVOLU is set, this setting will take effect after the next write to the Right Input Volume register. Right ADC Digital Volume Control 0000 0000 = Digital Mute 10111111 0000 0001 = -71.25dB (0dB) 0000 0010 = -70.875dB ... 0.375dB steps up to 1111 1111 = +24dB R7 (07h) Right ADC Digital Volume 7:0 ADCVOL_R [7:0] RW Table 50. L/R ADC Digital Volume Registers 4.7. Automatic Level Control (ALC) The ACS522D01 has an automatic level control to achieve recording volume across a range of input signal levels. The device uses a digital peak detector to monitor and adjusts the PGA gain to provide a signal level at the ADC input. A range of adjustment between –6dB and –28.5dB (relative to ADC full scale) can be selected. The device provides programmable attack, hold, and decay times to smooth adjustments. The level control also features a peak limiter to prevent clipping when the ADC input exceeds a threshold. Note that if the ALC is enabled, the input volume controls are ignored. 4.7.1. ALC Operation Figure 17. ALC Operation When ALC is enabled, the recording volume target can be programmed between –6dB and –28.5dB (relative to ADC full scale). The ALC will attempt to keep the ADC input level to within +/-0.5dB of the target level. An upper limit for the PGA gain can also be imposed, using the MAXGAIN control bits. 41 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Hold time specifies the delay between detecting a peak level being below target, and the PGA gain beginning to ramp up. It is specified as 2n*2.67mS, enabling a range between 0mS and over 40s.; ramp-down begins immediately if the signal level is above the target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA to ramp up across 90% of its range. The time is 2n*24mS. The time required for the recording level to return to its target value therefore depends on the decay time and on the gain adjustment required. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA to ramp down across 90% of its range. Time is specified as 2n*24mS. The time required for the recording level to return to its target value depends on both the attack time and on the gain adjustment required. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and both PGAs use the same gain setting, to preserve the stereo image. If the ALC function is only enabled on one channel, only one PGA is controlled by the ALC mechanism, and the other channel runs independently using the PGA gain set through the control registers. If one ADC channel is unused, the peak detector will ignore that channel. The ALC function can operate when the two ADC outputs are mixed to mono in the digital domain or in the analog domain. 42 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.7.2. ALC Registers Bit Label Type Default Description Register Address 7:3 2 R14 (0Eh) ALC Control 0 RSVD ALC MODE R RW 00000 0 Reserved 0: ALC Mode 1: Limiter mode ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) Note: ensure that LINVOL and RINVOL settings (reg. 0 and 1) are the same before entering this mode. Reserved 1:0 ALCSEL [1:0] RW 00 (OFF) 7 RSVD R 0 6:4 R15 (0Fh) ALC Control 1 MAXGAIN [2:0] RW Set Maximum Gain of PGA 111: +30dB 111 110: +24dB (+30dB) ….(-6dB steps) 001: -6dB 000: -12dB ALC target – sets signal level at ADC input 0000 = -28.5dB fs 0001 = -27.0dB fs … (1.5dB steps) 1110 = -7.5dB fs 1111 = -6dB fs Sets the minimum gain of the PGA 000 = -17.25db 001 = -11.25 ... 110 = +18.75dB 111 = +24.75db where each value represents a 6dB step. ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 3:0 ALCL [3:0] RW 1011 (-12dB) 7 RSVD RW 0 6:4 R16 (10h) ALC Control 2 MINGAIN RW 000 3:0 HLD [3:0] RW 0000 (0ms) 7:4 R17 (11h) ALC Control 3 3:0 DCY [3:0] RW ALC decay (gain ramp-up) time 0000 = 24ms 0011 0001 = 48ms (192ms) 0010 = 96ms … (time doubles with every step) 1010 or higher = 24.58s ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s ATK [3:0] RW 0010 (24ms) Table 51. ALC Control Registers 43 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.7.3. Peak Limiter To prevent clipping, the ALC circuit also includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate, until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. 4.7.4. Input Threshold To avoid hissing during quiet periods, the ACS522D01 has an input threshold noise gate function that compares the signal level at the inputs to a noise gate threshold. Below the threshold, the programmable gain can be held , or the ADC output can be muted. The threshold can be adjusted in increments of 1.5dB. The noise gate activates when the signal-level at the input pin is less than the Noise Gate Threshold (NGTH) setting. The ADC output can be muted. Alternatively, the PGA gain can be held . The threshold is adjusted in 1.5dB steps. The noise gate only works in conjunction with the ALC, and always operates on the same channel(s) as the ALC. 4.7.4.1. Register Address Bit Noise Gate Control Register Label Type Default Description 7:3 R12 (12h) Noise Gate Control (NGATE) 2:1 NGTH [4:0] RW 00000 Noise gate threshold (compared to ADC full-scale range) 00000 -76.5dBfs 00001 -75dBfs … 1.5 dB steps 11110 -31.5dBfs 11111 -30dBfs Noise gate type X0 = PGA gain held 01 = mute ADC output 11 = reserved (do not use this setting) Noise gate function enable 1 = enable 0 = disable NGG [1:0] RW 00 0 NGAT RW 0 Table 52. NGATE Register 4.8. Digital Microphone Support Line Input 3 may be an analog line (mic) or digital microphone input depending on the part option. The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the DMIC_DAT, and DMIC_CLK 2-pin interface. DMIC_DAT is an input that carries individual channels of digital microphone data to the ADC. In the event that a single microphone is used, the data is ported to both ADC channels. This mode is selected using a control bit and the left time slot is copied to the ADC left and right inputs. The DMIC_CLK output is synchronous to the internal master (DSP) clock and is adjustable in 4 steps. Each step provides a clock that is a multiple of the chosen ADC base rate and modulator rate.The default frequency is 320/3 times the ADC base rate for 32KHz, and 80 times the base rate for 44.1KHz and 48KHz base rates. 44 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SDM Rate DMRate [1:0] Base Rate DSPCLK DMIC_CLK divisor DMIC_CLK 32 KHz 00 44.1 KHz 48 KHz 32 KHz 01 Full 10 44.1 KHz 48 KHz 32 KHz 44.1 KHz 48 KHz 32 KHz 11 44.1 KHz 48 KHz 32 KHz 00 44.1 KHz 48 KHz 32 KHz 01 Half 10 44.1 KHz 48 KHz 32 KHz 44.1 KHz 48 KHz 32 KHz 11 44.1 KHz 48 KHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 40.960 MHz 56.448 MHz 61.440 MHz 12 16 16 16 20 20 20 24 24 24 32 32 16 16 16 24 24 24 32 32 32 40 40 40 3.413333 MHz 3.528 MHz 3.84 MHz 2.56 Mhz 2.8224 MHz 3.072 MHz 2.048 Mhz 2.352 MHz 2.56 MHz 1.706667 Mhz 1.764 MHz 1.92 MHz 2.56 MHz 3.528 MHz 3.84 MHz 1.706667 MHz 2.352 MHz 2.56 MHz 1.28 MHz 1.764 MHz 1.92 MHz 1.024 MHz 1.4112 MHz 1.536 MHz Table 53. DMIC Clock The two DMIC data inputs are shown connected to the ADCs through the same multiplexors as the analog ports. Although the internal implementation is different between the analog ports and the digital microphones, the functionality is the same. In most cases, the default values for the DMIC clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digital microphones exactly like an analog microphone. If the ADC path is powered down, the DMIC_CLK output will be driven low to place the DMIC element into a low power state. (Many digital microphones will enter a low power state if the clock input is held at a DC level or toggled at a slow rate.) 45 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The codec supports the following digital microphone configurations: Digital Mics Data Sample Notes 0 1 N/A Single Edge No Digital Microphones When using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone for “Left” and select mono operation. “Left” D-mic data is used for ADC left and right channels. External logic required to support sampling on a single Digital Mic pin channel on rising edge and second Digital Mic right channel on falling edge of DMIC_CLK for those digital microphones that don’t support alternative clock edge (multiplexed output) capability. 2 Double Edge Table 54. Valid Digital Mic Configurations Off-Chip Digital Microphone On-Chip Single Line In DMIC_DAT Pin DMIC_CLK Pin On-Chip Multiplexer STEREO ADC PCM Stereo Channels Output Single Microphone not supporting multiplexed output. DMIC_DAT Valid Data Right Channel Left Channel Valid Data Valid Data MUX DMIC_CLK Single “Left” Microphone, DMIC input set to mono input mode. DMIC_DAT Valid Data Valid Data Valid Data Valid Data Left & Right Channel DMIC_CLK Figure 18. Single Digital Microphone (data is ported to both left and right channels) 46 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Off-Chip External Multiplexer DMIC_DAT MUX On-Chip Digital Microphones On-Chip Multiplexer Stereo Channels Output Pin STEREO ADC PCM MUX DMIC_CLK Pin DMIC_DAT Valid Data R Valid Data L Valid Data R Valid Data L Valid Data R Right Channel Left Channel DMIC_CLK Figure 19. Stereo Digital Microphone Configuration 4.8.1. DMIC Register Bit Label Type Default Description Register Address 7 6:5 R36 (24h) D-Mic Control (DMICCTL) 4 DMicEn RSVD DMono RW R RW 0 00 0 Digital Microphone Enable 0 = DMIC interface is disabled (DMIC_CLK low, DMIC muted) 1 = DMIC interface is enabled Reserved 0 = stereo operation, 1 = mono operation (left channel duplicated on right) Selects when the D-Mic data is latched relative to the DMIC_CLK. 00 = Left data rising edge / right data falling edge 01 = Left data center of high / right data center of low 10 = Left data falling edge / right data rising edge 11 = Left data center of low / right data center of high Selects the DMIC clock rate: See table in text 3:2 DMPhAdj[1:0] RW 00 1:0 DMRate[1:0] RW 00 Table 55. DMICCTL Register 47 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5. DIGITAL AUDIO AND CONTROL INTERFACES 5.1. Data Interface For digital audio data, the ACS522D01 uses five pins to input and output digital audio data. • ADCDOUT: ADC data output • ADCLRCK: ADC data alignment clock • ADCBCLK: Bit clock, for synchronization • DACDIN: DAC data input • DACLRCK: DAC data alignment clock • DACBCLK: Bit clock, for synchronization The clock signals ADCBCLK, ADCLRCK, DACBCLK, and DACLRCK are outputs when the ACS522D01 operates as a master; they are inputs when it is a slave. Three different data formats are supported: • Left justified • Right justified • I2S All of these modes are MSB first. 5.2. Master and Slave Mode Operation The ACS522D01 can be used as either a master or slave device, selected by the MS Bit. When operating as a master, the ACS522D01 generates ADCBCLK, ADCLRCLK, DACBCLK and DACLRCLK and controls sequencing of the data transfer the data pins. In slave mode, the ACS522D01 provides data aligned to clocks it receives. CODEC ADCBCLK ADCLRCLK ADCDOUT DACBCLK DACLRCLK DACDIN DSP ENCODER/ DECODER Figure 20. Master mode CODEC ADCBCLK ADCLRCLK ADCDOUT DACBCLK DACLRCLK DACDIN DSP ENCODER/ DECODER Figure 21. Slave mode 48 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.3. Audio Data Formats The ACS522D01 supports 3 common audio interface formats and programmable clocking that provides broad compatibility with DSPs, Consumer Audio and Video SOCs, FPGAs, handset chipsets, and many other products. In all modes, depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. If the converter word length is smaller than the number of clocks per sample in the frame then the DAC will ignore (truncate) the extra bits while the ADC will zero pad the output data. If the converter word length chosen is larger than the number of clocks available per sample in the frame, the ADC data will be truncated to fit the frame and the DAC data will be zero padded. 5.4. Left Justified Audio Interface In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits are then transmitted in order. The LRCLK signal is high when left channel data is present and low when right channel data is present. Left Justified 1/fs Left Channel Right Channel LRCLK BCLK SDI / SDO 1 MSB Word Length (WL) 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 22. Left Justified Audio Interface (assuming n-bit word length) 5.5. Right Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted in order. The LRCLK signal is high when left channel data is present and low when right channel data is present. Right Justified 1/fs Left Channel Right Channel LRCLK BCLK SDI / SDO 1 MSB Word Length (WL) 2 3 n-2 n-1 n LSB 1 MSB 2 3 n-2 n-1 n LSB Figure 23. Right Justified Audio Interface (assuming n-bit word length) 49 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.6. I2S Format Audio Interface In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. I2S 1/fs Left Channel Right Channel LRCLK BCLK 1 BCLK 1 BCLK 3 n-2 n-1 n LSB Word Length (WL) 1 MSB 2 3 n-2 n-1 n LSB SDI / SDO 1 MSB 2 Figure 24. I2S Justified Audio Interface (assuming n-bit word length) 5.7. Data Interface Registers 5.7.1. Audio Data Format Control Register Bit Label Type Default Description Register Address 7 6 RSVD BCLKINV R RW 0 0 Reserved BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Right, left and I2S modes – LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity Audio Data Word Length 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits Audio Data Format Select 11 = Reserved 10 = I2S Format 01 = Left justified 00 = Right justified 5 MS RW 0 R19 (13h) Digital Audio Interface Format (AIC1) 4 LRP RW 0 3:2 WL[1:0] RW 10 1:0 FORMAT[1:0] RW 10 Table 56. AIC1 Register 50 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.7.2. Audio Interface Output Tri-state TRI is used to tri-state the ADCDOUT, ADCLRCK, DACLRCK, ADCBCLK, and DACBCLK pins. In Slave mode (MASTER=0) only ADCDOUT will be tri-stated since the other pins are configured as inputs. The Tri-stated pins are pulled low with an internal pull-down resistor unless that resistor is disabled. Register Address Bit Label Type Default Description 7:6 DACDSEL[1:0] RW 00 00: left DAC = left I2S data; right DAC = right I2S data 01: left DAC = left I2S data; right DAC = left I2S data 10: left DAC = right I2S data; right DAC = right I2S data 11: left DAC = right I2S data; right DAC = left I2S data 00: left I2S data = left ADC; right I2S data = right ADC 01: left I2S data = left ADC; right I2S data = left ADC 10: left I2S data = right ADC; right I2S data = right ADC 11: left I2S data = right ADC; right I2S data = left ADC Tri-states ADCDOUT, ADCLRCLK, DACLRCLK, ADCBCLK, and DACBCLK pins. 0 = ADCDOUT is an output, ADCLRCK, DACLRCLK, ADCBCLK, and DACBCLK are inputs (slave mode) or outputs (master mode) 1 = ADCDOUT, ADCLRCK, DACLRCLK, ADCBCLK, and DACBCLK are high impedance Bitclock and LRClock mode. See Table Below R20 (14h) Audio Interface Control 2 (AIC2) 5:4 ADCDSEL[1:0] RW 00 3 TRI RW 0 2:0 BLRCM[2:0] RW 000 Table 57. AIC2 Register 5.7.3. Audio Interface Bit Clock and LR Clock configuration Although the DAC and ADC interfaces implement separate Bit Clock and LR Clock pins, it is also possible to share one or both of the clocks. the following restrictions must be observed when the BCLK from one path (DAC or ADC) is combined with the LRCLK from the other path (ADC or DAC) as described by the Bit Clock and LR Clock Mode Selection table below: 1. Both the DAC and ADC must be programmed for the same sample rate 2. Both the DAC and ADC must be programmed for the same number of clocks per frame 3. When in slave mode, the DAC and ADC data must be aligned relative to the provided BCLK and LRCLK (this is guaranteed in master mode) 4. The DAC and ADC must be powered down when changing the BLRCM mode 5. If sharing the BCLK from one path (DAC or ADC) and the LRCLK from the other path (ADC or DAC), shut down both the DAC and ADC before programming the sample rate and clocks per frame for either. (Again, both must match.) 51 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.7.4. MS BLRCM [2:0] Bit Clock and LR Clock Mode Selection DAC BCLK ADC BCLK DAC LRCLK ADC LRCLK MODE1 0 0 0 0 000 001 010 011 Independent Independent Shared BCLK (DAC) Shared BCLK & LRCLK (DAC) Shared BCLK (DAC) & LRCLK (ADC) Shared BCLK (ADC) Shared BCLK (ADC) & LRCLK (DAC) Shared BCLK & LRCLK (ADC) Independent (off if converter off) Input for playback path Input for playback path Input for playback and record Input for playback and record Input for playback and record unused input for record path input for record path unused unused Input for playback path Input for playback path Input for playback path Input for playback and record input for record path input for record path input for record path unused 0 100 unused Input for playback and record Input for playback and record Input for playback and record Output for record path (Off when ADC off)3 Output for record path (off when DACs and ADCs off) unused (off) unused Input for playback and record input for record path 0 101 Input for playback path Input for playback and record 0 110 unused unused 0 111 unused Output for playback path (off when DACs off)2 unused Output for playback path (off when DACs off) Output for playback path (off when DACs and ADCs off) Output for playback path (Off if DAC is off) Output for playback and record (stays on if either DAC or ADC on) unused (off) Output for playback path (Off if DAC is off) Output for playback and record (stays on if either DAC or ADC on) unused (off) Input for playback and record Output for record path (off when ADCs off) Output for record path (off when DACs and ADCs off) Output for record path (off when ADCs off) unused (off) Output for playback and record (stays on if either DAC or ADC on) Output for record path (off when ADCs off) unused (off) Output for playback and record (stays on if either DAC or ADC on) 1 000 1 001 Independent Output for playback path (off if all (off when DACs and converters off) ADCs off) Shared BCLK (DAC) Shared BCLK & LRCLK (DAC) Shared BCLK(DAC)& LRCLK(ADC) Shared BCLK (ADC) Shared BCLK(ADC)& LRCLK(DAC) Shared BCLK & LRCLK(ADC) Output for playback and record (stays on if either DAC or ADC on) Output for playback and record (stays on if either DAC or ADC on) Output for playback and record (stays on if either DAC or ADC on) unused (off) 1 010 1 011 unused (off) 1 100 unused (off) Output for playback and record (stays on if either DAC or ADC on) Output for playback and record (stays on if either DAC or ADC on) Output for playback and record (stays on if either DAC or ADC on) 1 101 1 110 unused (off) 1 111 unused (off) Table 58. Bit Clock and LR Clock Mode Selection 1.When sharing both the BCLK and LRCLK between the DAC and ADC interfaces, both the DAC and ADC must be programmed for the same rate, the same number of clocks per frame, and data must be aligned the same with respect to LRCLK. Disable all converters before changing modes. 2.DAC (playback path) is off when HPL, HPR, SPKL, and SPKR power states are off. 52 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.ADC (record path) is off when ADCL, and ADCR power states are off (PGA, D2S, Boost power states are not considered.) 5.7.5. ADC Output Pin State Record Path Power State ADC Data Out Pull-down (ADOPDD) ADC Data Out State Tri-state (TRI) Off 0 Off On 1 NA NA 0 1 NA 0 1 Off, pulled-low Off, floating Active Off, pulled-low Off, floating Table 59. ADC Data Output pin state 5.7.6. Audio Interface Control 3 Register Bit Label Type Default Description Register Address 7:6 5 RSVD ADOPDD R RW 0 0 4 R21 (15h) Audio Interface Control 3 (AIC3) ALRPDD RW 0 Reserved ADCDOUT Pull-Down Disable 0 = Pull-Down active when tri-stated or the ADC path is powered down. 1 = Pull-Down always disabled ADCLRCLK Pull-Down Disable 0 = Pull-Down active when configured as input 1 = Pull-Down always disabled ADCBCLK Pull-Down Disable 0 = Pull-Down active when configured as input 1 = Pull-Down always disabled DACDIN Pull-Down Disable 0 = Pull-Down active 1 = Pull-Down always disabled DACLRCLK Pull-Down Disable 0 = Pull-Down active when configured as input 1 = Pull-Down always disabled DACBCLK Pull-Down Disable 0 = Pull-Down active when configured as input 1 = Pull-Down always disabled 3 ABCPDD RW 0 2 DDIPDD RW 0 1 DLRPDD RW 0 0 DBCPDD RW 0 Table 60. AIC3 Register 5.8. Bit Clock Mode The default master mode bit clock generator automatically produces a bit clock frequency based on the sample rate and word length. When enabled by setting the appropriate BCM bits, the bit clock mode (BCM) function overrides the default master mode bit clock generator to produce the bit clock frequency shown below: Note that selecting a word length of 24-bits in Auto mode generates 64 clocks per frame (64fs) 53 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC . Register Address Bit Label Type Default Description R23/R25 (17h/19h ADC/DAC Sample Rate Control 7:6 ABCM[1:0] DBCM[1:0] RW 00 BCLK Frequency 00 = Auto 01 = 32 x fs 10 = 40 x fs 11 = 64 x fs Table 61. Master Mode BCLK Frequency Control Register The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample. LRCLK Fs x 64 Fs x 40 Fs x 32 Figure 25. Bit Clock mode Note: The clock cycles are evenly distributed throughout the frame (true multiple of LRCLK not a gated clock.) 5.9. Control Interface The registers are accessed through a serial control interface using a multi-word protocol comprised of 8-bit words. The first 8 bits provide the device address and Read/Write flag. In a write cycle, the next 8 bits provide the register address; all subsequent words contain the data, corresponding to the 8 bits in each control register.The control interface operates using a standard 2-wire interface, as a slave device only. 5.9.1. Register Write Cycle The controller indicates the start of data transfer with a high to low transition on SDA while SCL remains high, signalling that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the ACS522D01 and the R/W bit is ‘0’, indicating a write, then the ACS522D01 responds by pulling SDA low on the next clock pulse (ACK); otherwise, the ACS522D01 returns to the idle condition to wait for a new start condition and valid address. Once the ACS522D01 has acknowledged a correct device address, the controller sends the ACS522D01 register address. The ACS522D01 acknowledges the register address by pulling SDA low for one clock pulse (ACK). The controller then sends a byte of data (B7 to B0), and the ACS522D01 acknowledges again by pulling SDA low. When there is a low to high transition on SDA while SCL is high, the transfer is complete. After receiving a complete address and data sequence the ACS522D01 returns to the idle state. If a start or stop condition is detected out of sequence, the device returns to the idle condition. 54 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SCL SDA START Device Address DA[6:0] nW ACK Register Address RA[7:0] ACK Register Data RD[7:0] ACK STOP Figure 26. 2-Wire Serial Control Interface The ACS522D01 has device address D2. 5.9.2. Multiple Write Cycle The controller may write more than one register within a single write cycle. To write additional registers, the controller will not generate a stop or start (repeated start) command after receiving the acknowledge for the second byte of information (register address and data). Instead the controller will continue to send bytes of data. After each byte of data is received, the register address is incremented. SCL SDA START Device Address DA[6:0] nW ACK Register Address RA[7:0] ACK Register Data RD[7:0] ACK Register Data RD[7:0] @RA[7:0]+1 ACK Register Data RD[7:0] @RA[7:0]+n ACK STOP Register Write 1 Register Write 2 ... Register Write n Figure 27. Multiple Write Cycle 5.9.3. Register Read Cycle The controller indicates the start of data transfer with a high to low transition on SDA while SCL remains high, signalling that a device address and data will follow. If the device address received matches the address of the ACS522D01 and the R/W bit is ‘0’, indicating a write, then the ACS522D01 responds by pulling SDA low on the next clock pulse (ACK); otherwise, the ACS522D01 returns to the idle condition to wait for a new start condition and valid address. Once the ACS522D01 has acknowledged a correct address, the controller sends a restart command (high to low transition on SDA while SCL remains high). The controller then re-sends the devices address with the R/W bit set to ‘1’ to indicate a read cycle.The ACS522D01 acknowledges by pulling SDA low for one clock pulse. The controller then receives a byte of register data (B7 to B0). For a single byte transfer, the host controller will not acknowledge (high on data line) the data byte and generate a low to high transition on SDA while SCL is high, completing the transfer. If a start or stop condition is detected out of sequence, the device returns to the idle condition. 55 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SCL SDA START Device Address DA[6:0] nW ACK Register Address RA[7:0] ACK Device Address DA[6:0] R ACK Register Data RD[7:0] nACK RESTART STOP Figure 28. Read Cycle The ACS522D01 has device address D2. 5.9.4. Multiple Read Cycle The controller may read more than one register within a single read cycle. To read additional registers, the controller will not generate a stop or start (repeated start) command after sending the acknowledge for the byte of data. Instead the controller will continue to provide clocks and acknowledge after each byte of received data. The codec will automatically increment the internal register address after each register has had its data successfully read (ACK from host) but will not increment the register address if the data is not received correctly by the host (nACK from host) or if the bus cycle is terminated unexpectedly (however the EQ/Filter address will be incremented even if the register address is not incremented when performing EQ/Filter RAM reads). By automatically incrementing the internal register address after each byte is read, all the internal registers of the codec may be read in a single read cycle. S DA[6:0] nW ACK RA[7:0] ACK Sr DA[6:0] R ACK RD[7:0] ACK RD[7:0] ACK RD[7:0] nACK P Set Register Address Read Register @ RA[7:0] Read Register @ RA[7:0] + 1 Read Register @ RA[7:0] + n Figure 29. Multiple Read Cycle 5.9.5. Device Addressing and Identification The ACS522D01 has a default slave address of D2. However, it is sometimes necessary to use a different address. The ACS522D01 has a device address register for this purpose. The part itself has an 8-bit Identification register and an 8-bit revision register that provide device specific information for software. In addition, an 8-bit programmable subsystem ID register can allow firmware to provide a descriptive code to higher level software such as an operating system driver or application software. 5.9.5.1. • Device Address Register Register Address Bit Device Registers Label Type Default Description R124 (7Ch) DEVADR 7:1 0 ADDR[7:1] RSVD RW R 1101001 7-bit slave address 0 Not used - this bit is the R/nW bit in the 2-wire protocol. Table 62. DEVADRl Register 56 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Device Identification Registers Register Address Bit Label Type Default Description R126 (7Eh) DEVIDH R125 (7Dh) DEVIDL 7:0 7:0 DID[15:8] DID[7:0] R R xxh xxh 16-bit device identification number. The ACS522D01 has programmable clocking that will drive different device IDs for each configuration. Contact IDT. Table 63. DEVID H&L Registers • Device Revision Register Register Address Bit Label Type Default Description R127 (7Fh) REVID 7:4 3:0 MAJ[3:0] MNR[3:0] R R xh xh 4-bit major revision number. Contact IDT. 4-bit minor revision number. Contact IDT. Table 64. REVID Register Note: Contact IDT for device and revision information. 5.9.5.2. Register Reset The ACS522D01 registers may be reset to their default values using the reset register. Writing a special, non-zero value to this register causes all other registers to assume their default states. Device status bits will not necessarily change their values depending on the state of the device. Register Address Bit Label Type Default Description R128 (80h) RESET 7:0 Reset[7:0] RW 00h Reset register Writing a value of 85h will cause registers to assume their default values. Reading this register returns 00h Table 65. RESET Register 57 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 6. AUDIO CLOCK GENERATION 6.1. Internal Clock Generation (ACLK) In addition to providing external clocks, the PLL block will also provide two clocks for the audio portion of the device. They are • 122.880 MHz (2560 x 48 KHz) • 112.896 (2560 x 44.1 KHz) It is important that the crystal oscillator and needed PLLs remain on until all audio functions, including jack detection, are disabled. 6.2. ACLK Clocking and Sample Rates The ACS522D01 utilizes internal PLLs to generate the audio master clock (ACLK) at 56.448MHz (22.5792MHz *2.5) and 61.44MHz (24.576 *2.5). It then generates audio sample rates directly from the master clock. The ADC and DAC do not need to run at the same sample rate unless they are sharing BCLK and LRCLK pins. Disable the appropriate converters before programming the mode or rate, especially if the DAC and ADC are programmed to share the same BCLK and LRCLK. After changing rate, a delay of up to 5mS may be needed for the part to properly lock PLLs, flush filters, etc. Register Address Bit Label Type Default Description 7:6 ABCM[1:0] RW 00 ADC Bit Clock Mode (for data interface ADCBCLK generation in master mode) 00 = Auto 01 = 32x fs 10 = 40x fs 11 = 64x fs Reserved ADC Base Rate 00 = 32KHz 01 = 44.1KHz 10 = 48KHz 11 = Reserved ADC Base Rate Multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = Reserved 5 R23 (17h) ADC Sample Rate Control (ADCSR) RSVD R 0 4:3 ABR[1:0] RW 10 2:0 ABM[2:0] RW 010 Table 66. ADCSR Register 58 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Register Address Bit Label Type Default Description 7:6 DBCM[1:0] RW 00 DAC Bit Clock Mode (for data interface DACBCLK generation in master mode) 00 = Auto 01 = 32x fs 10 = 40x fs 11 = 64x fs Reserved DAC Base Rate 00 = 32KHz 01 = 44.1KHz 10 = 48KHz 11 = Reserved DAC Base Rate Multiplier 000 = 0.25x 001 = 0.50x 010 = 1x 011 = 2x 100-111 = Reserved 5 R25 (19h) DAC Sample Rate Control (DACSR) RSVD R 0 4:3 DBR[1:0] RW 10 2:0 DBM[2:0] RW 010 Table 67. DACSR Register The clocking of the ACS522D01 is controlled using the BR[1:0] and BM[2:0] control bits. Each value of BR[1:0] + BM[2:0]selects one combination of ACLK division ratios and hence one combination of sample rates The BR[1:0] and BM[2:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master and slave mode. BR [1:0] BM [2:0] ACLK SAMPLE RATE 000 001 00 010 011 100-111 000 001 01 010 011 100-111 000 001 10 010 011 100-111 11 000-111 - 8 kHz (MCLK/5120) 16 kHz (MCLK/2560) 40.96 MHz 32 kHz (MCLK/1280) Reserved Reserved 11.025 kHz (MCLK/5120) 22.05 kHz (MCLK/2560) 56.448MHz 44.1 kHz (MCLK/1280) 88.2 kHz (MCLK/640) Reserved 12 kHz (MCLK/5120) 24 kHz (MCLK/2560) 61.44 MHz 48 kHz (MCLK/1280) 96 kHz (MCLK/640) Reserved Reserved Table 68. ACLK and Sample Rates 6.3. DAC/ADC Modulator Rate Control The power consumption and audio quality may be adjusted by changing the converter modulator rate. By default the 59 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC DAC and ADC Sigma-Delta modulators run at a high rate for the best audio quality. The modulator rates for the converters may be forced to run at half their nominal rate to conserve power. A third option allows the modulator rate to automatically drop to half rate when low sampling rates are chosen (1/2 or 1/4 the base rate.) The DACs and ADCs are independently controlled. Register Address Bit Label Type Default Description 7:6 ASDM[1:0] RW 10h ADC Modulator Rate 00 = Reserved 01 = Half 10 = Full 11 = Auto DAC Modulator Rate 00 = Reserved 01 = Half 10 = Full 11 = Auto Reserved for future use. 1 = bypass DC removal filter (WARNING DC content can damage speakers) 1 = supply detect forced on. 0 = supply detect on when needed (COP, UVLO enabled). R31 (1Fh) CONFIG0 5:4 DSDM[1:0] RW 10h 3:2 1 0 RSVD dc_bypass sd_force_on R RW R 0h 0 0 Table 69. CONFIG0 Register DSDM[1:0] ASDM[1:0] BM [2:0] Modulator Rate 00 NA 000 (1/4x) 001 (1/2x) 010 (1x) 011 (2x) 000 (1/4x) 001 (1/2x) 010 (1x) 011 (2x) 000 (1/4x) Reserved 01 Half 10 Full Auto (Half) Auto (Half) Auto (Full) Auto (Full) 11 001 (1/2x) 010 (1x) 011 (2x) Table 70. SDM Rates 60 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 7. CHARACTERISTICS 7.1. Electrical Specifications 7.1.1. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ACS522D01. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Maximum Rating Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature MICBias Output Current Amplifier Maximum Supply Voltage Audio Maximum Supply Voltage Digital I/O Maximum Supply Voltage Digital Core Maximum Supply Voltage Vss - 0.3V TO Vdd + 0.3V 0 oC TO 70 oC -55 oC TO +125 oC 260 oC 3mA 6 Volts = PVDD 3 Volts = AVDD/CPVDD 3.6 Volts = DVDD_IO 2.0 Volts = DVDD Table 71. Electrical Specification: Maximum Ratings 7.1.2. Power Supplies Recommended Operating Conditions Min. Typ. Max. Units Parameter DVDD_Core DVDD_IO AVDD/CPVDD PVDD 1.4 1.4 1.7 3.0 0 25 2.0 3.5 2.0 5.25 70 90 V V oC oC Ambient Operating Temperature Case Temperature Analog - 5 V Tcase Table 72. Recommended Operating Conditions ESD: The ACS522D01 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the ACS522D01 implements internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or performance. 61 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 7.2. Device Characteristics Parameter Symbol Test Conditions Min Typ Max Unit (Tambient = 25 ºC, DVDD_CORE=DVDD_IO=AVDD=1.9V, PVDD=3.6V, 997Hz signal, fs=48KHz, Input Gain=0dB, 24-bit audio) Analog Inputs (LIN1, LIN2, LIN3, RIN1, RIN2, RIN3) L/RIN1,2,3 Single Ended Full Scale Input Voltage Input Impedance Input Capacitance Analog Input Boost Amplifier VFSIV L/RIN1,2,3 Differential Mic 0.5 -6 0.5 -6 50 10 0.0 30.0 10.0 -17.25 30.0 Vrms dBV Vrms dBV Kohm pF dB dB dB dB dB dB dB dB dB dB dB dB % dB dB % dB 2 % dB dB dB dB Vrms Vrms mW (ave) dB Programmable Gain Min Programmable Gain Max Programmable Gain Step Size Analog Input PGA Programmable Gain Min Programmable Gain Max Programmable Gain Step Size Digital Volume Control Amplifier Guaranteed Monotonic 0.75 -97 30.0 Programmable Gain Min Programmable Gain Max Programmable Gain Step Size Mute Attenuation Analog Inputs (LIN1/RIN1, LIN2/RIN2 Differential) to ADC Guaranteed Monotonic 0.5 -999 Signal To Noise Ratio Total Harmonic Distortion + Noise Signal To Noise Ratio Total Harmonic Distortion + Noise ADC channel Separation Channel Matching Signal to Noise Ratio1 Total Harmonic Distortion +Noise2 Channel Separation Mute attenuation SNR THD+N A-weighted 20-20KHz -1dBFS input 90 -80 0.01 90 -80 0.01 70 Analog Inputs (LIN1, LIN2, LIN3, RIN1, RIN2, RIN3 Single Ended) to ADC SNR THD+N A-weighted 20-20KHz -1dBFS input 997Hz full scale signal 997Hz signal DAC to Line-Out (HPL, HPR with 10K / 50pF load) SNR THD+N A-weighted 997Hz full scale signal 997Hz full scale signal 102 -84 70 -999 Headphone Outputs (HPL, HPR) Full Scale Output Level Output Power Signal to Noise Ratio VFSOV PO SNR RL = 10Kohm RL = 16ohm 997Hz full scale signal, RL = 16ohm A-weighted, RL = 16ohm Table 73. Device Characteristics 1.0 0.75 35 102 62 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. V1.0 1/12 ACS522D01 ACS522D01 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Parameter Symbol Test Conditions Min Typ Max Unit Total Harmonic Distortion +Noise THD+N RL = 16ohms, -3dBFS RL = 32ohms, -3dBFS -5% -76 -78 -AVDD +100mV 2.5 80 40 30 32 0.7x 1022 dB dB Analog Voltage Reference Levels Charge Pump Output Microphone Bias V- +5% V Bias Voltage BIAS current Source Power Supply Rejection Ratio Digital Input/Output VMICBIAS 3.3V