CS853014BGLFT

LOW SKEW, 1-TO-5, DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER ICS853014 Features • • • • • • • • • • • Five differential LVPECL/ECL outputs Two selectable differential LVPECL clock inputs PCLKx, PCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Maximum output frequency: > 2GHz Output skew: 13ps (typical) Part-to-part skew: 60ps (typical) Propagation delay: 460ps (typical) LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages General Description ICS HiPerClockS™ The ICS853014 is a low skew, high performance 1-to-5, 2.5V/3.3V Differential-to-LVPECL/ECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS853014 has two selectable clock inputs. Guaranteed output and part-to-part skew characteristics make the ICS853014 ideal for those applications demanding well defined performance and repeatability. Block Diagram EN Pulldown PCLK0 Pulldown PCLK0 Pullup/Pulldown PCLK1 Pulldown PCLK1 Pullup/Pulldown CLK_SEL Pulldown VBB 1 0 D Q LE Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Pin Assignment Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC EN VCC PCLK1 PCLK1 VBB PCLK0 PCLK0 CLK_SEL VEE ICS853014 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 1 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number 1, 2 3, 4 5, 6 7, 8 9, 10 11 12 13 14 15 16 17 18, 20 19 Name Q0, Q0 Q1, Q1 Q2, Q2 Q3, Q3 Q4, Q4 VEE CLK_SEL PCLK0 PCLK0 VBB PCLK1 PCLK1 VCC EN Output Output Output Output Output Power Input Input Input Output Input Input Power Input Pulldown Pulldown Pullup/ Pulldown Pulldown Pulldown Pullup/ Pulldown Type Description Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Negative supply pin. Clock select input. When HIGH, selects PCLK1/PCLK1 inputs. When LOW, selects PCLK0/PCLK0 inputs. LVTTL / LVCMOS interface levels. Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. VCC/2 default when left floating. Positive supply pins. Synchronizing clock enable. When LOW, clock outputs follow clock input. When HIGH, Qx outputs are forced low, Qx outputs are forced high. LVTTL/LVCMOS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units kΩ kΩ IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 2 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs EN 1 1 0 0 CLK_SEL 0 1 0 1 Selected Source PCLK0, PCLK0 PCLK1, PCLK1 PCLK2, PCLK2 PCLK3, PCLK3 Q0:Q4 Disabled; Low Disabled; Low Enabled Enabled Outputs Q0:Q4 Disabled; High Disabled; High Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the PCLK0/PCLK0 and PCLK1/PCLK1 inputs as described in Table 3B. Disabled Enabled PCLK0, PCLK1 PCLK0, PCLK1 EN Q0:Q4 Q0:Q4 Figure 1. EN Timing Diagram Table 3B. Clock Input Function Table Inputs PCLK0 or PCLK1 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 PCLK0 or PCLK1 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs Q0:Q4 LOW HIGH LOW HIGH HIGH LOW Q0:Q4 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential Single-Ended to Differential Polarity Non-Inverting Non-Inverting Non-Inverting Non-Inverting Inverting Inverting IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuos Current Surge Current VBB Sink//Source, IBB Operating Temperature Range, TA Package Thermal Impedance, θJA Storage Temperature, TSTG Rating 4.6V (LVPECL mode, VEE = 0V) -4.6V (ECL mode, VCC = 0V) -0.5V to VCC + 0.5V 0.5V to VEE – 0.5V 50mA 100mA ± 0.5mA -40°C to +85°C 73.2°C/W (0 lfpm) -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.8 85 Units V mA IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C -40°C Symbol VOH VOL VIH VIL VBB VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-ended) Input Low Voltage (Single-ended) 25°C Max 2.38 1.68 2.36 1.765 1.98 3.3 150 Min 2.225 1.425 2.075 1.43 1.86 1.2 Typ 2.295 1.52 Max 2.375 1.615 2.36 1.765 1.98 3.3 150 -10 -150 -10 -150 Min 2.22 1.44 2.075 1.43 1.86 1.2 80°C Typ 2.295 1.535 Max 2.365 1.63 2.36 1.765 1.98 3.3 150 Units V V V V V V µA µA µA Min 2.175 1.405 2.075 1.43 1.86 1.2 Typ 2.275 1.545 Output Voltage Reference; NOTE 2 Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current Input Low Current PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 -10 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V .Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C -40°C Symbol VOH VOL VIH VIL VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-ended) Input Low Voltage (Single-ended) 25°C Max 1.58 0.88 1.56 0.965 2.5 150 Min 1.425 0.625 1.275 0.63 1.2 Typ 1.495 0.72 Max 1.57 0.815 1.56 0.965 2.5 150 -10 -150 -10 -150 Min 1.42 0.64 1.275 0.63 1.2 80°C Typ 1.495 0.735 Max 1.565 0.83 1.56 0.965 2.5 150 Units V V V V V µA µA µA Min 1.375 0.605 1.275 0.63 1.2 Typ 1.475 0.745 Input High Voltage Common Mode Range; NOTE 2, 3 Input High Current Input Low Current PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 -10 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V. IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C -40°C Symbol VOH VOL VIH VIL VBB VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-ended) Input Low Voltage (Single-ended) 25°C Max -0.92 -1.62 -0.94 -1.535 -1.32 0 150 Min -1.075 -1.875 -1.225 -1.87 -1.44 VEE+1.2 Typ -1.005 -1.78 Max -0.93 -1.685 -0.94 -1.535 -1.32 0 150 -10 -150 -10 -150 Min -1.08 -1.86 -1.225 -1.87 -1.44 VEE+1.2 80°C Typ -1.005 -1.765 Max -0.935 -1.67 -0.94 -1.535 -1.32 0 150 Units V V V V V V µA µA µA Min -1.125 -1.895 -1.225 -1.87 -1.44 VEE+1.2 Typ -1.025 -1.755 Output Voltage Reference; NOTE 2 Input High Voltage Common Mode Range; NOTE 3, 4 Input High Current Input Low Current PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 PCLK0, PCLK1 -10 -150 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 6 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics, VCC = -3.8V to -2.375V or , VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C -40°C Symbol fMAX tPD tsk(o) tsk(pp) VPP tR / tF tS tH Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Part-to-Part Skew; NOTE 3, 5 Peak-to-Peak Input Voltage; NOTE 4 Output Rise/Fall Time 20% to 80% 150 90 100 200 800 150 50 140 355 Min Typ >2 440 13 525 25 105 1800 210 150 90 100 200 800 150 50 140 376 Max Min 25°C Typ >2 460 13 550 25 105 1800 210 150 90 100 200 800 150 50 140 400 Max Min 80°C Typ >2 500 13 595 25 130 1800 210 Max Units GHz ps ps ps mV ps ps ps Clock Enable Setup Time Clock Enable Hold Time All parameters are measured at f ≤ 1GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 7 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Parameter Measurement Information 2V VCC VCC Qx SCOPE PCLKx V PP Cross Points V CMR PCLKx LVPECL nQx VEE VEE -1.8V to -0.375V - LVPECL Output Load AC Test Circuit Differential Input Level Par t 1 Qx Qx Qx Qx Qy Qy Par t 2 Qy Qy t sk(pp) t sk(o) Part-to-Part Skew Output Skew PCLKx 80% Clock Outputs 80% VSW I N G PCLKx Q0:Q4 Q0:Q4 20% tR tF 20% tPD Output Rise/Fall Time Propagation Delay IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Parameter Measurement Information, continued PCLKx PCLKx EN t HOLD t SET-UP Setup and Hold Time Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLKx V_REF nPCLKx C1 0.1u R2 1K Figure 2. Single-Ended Signal Driving Differential Input IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 9 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER LVPECL Clock Input Interface The PCLK/PCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/PCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50Ω PCLK Zo = 50Ω nPCLK Zo = 50Ω R1 100 nPCLK R2 50 3.3V Zo = 50Ω PCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup HiPerClockS PCLK/nPCLK Figure 3A. HiPerClockS PCLK/PCLK Input Driven by an Open Collector CML Driver Figure 3B. HiPerClockS PCLK/PCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V Zo = 50Ω PCLK Zo = 50Ω nPCLK Zo = 50Ω C2 R3 125 R4 125 3.3V 3.3V 3.3V R3 84 Zo = 50Ω C1 PCLK R4 84 3.3V LVPECL nPCLK LVPECL R1 84 R2 84 HiPerClockS Input R5 100 - 200 R6 100 - 200 R1 125 R2 125 HiPerClockS PCLK/nPCLK Figure 3C. HiPerClockS PCLK/PCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. HiPerClockS PCLK/PCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 2.5V Zo = 60Ω PCLK Zo = 60Ω nPCLK R5 100 Zo = 50Ω C2 R3 120 R4 120 3.3V Zo = 50Ω C1 3.3V 3.3V R3 1k R4 1k PCLK nPCLK R1 1k R2 1k SSTL R1 120 R2 120 HiPerClockS PCLK/nPCLK LVDS HiPerClockS PCLK/nPCLK Figure 3E. HiPerClockS PCLK/PCLK Input Driven by an SSTL Driver Figure 3F. HiPerClockS PCLK/PCLK Input Driven by a 3.3V LVDS Driver IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 10 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Recommendations for Unused Output Pins Inputs: PCLK/PCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and PCLK pins can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from PCLK to ground. For applications Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and FOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω FOUT Zo = 50Ω 50Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o 50Ω VCC - 2V RTT Zo = 50Ω 84Ω 84Ω FIN 125Ω Zo = 50Ω FOUT FIN 125Ω RTT = Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50Ω + 50Ω – 50Ω – R3 250 50Ω + VCC = 2.5V 2.5V LVPECL Driver R1 50 R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 5C. 2.5V LVPECL Driver Termination Example IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 12 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Schematic Example This application note provides general design guide using ICS853014 LVPECL buffer. Figure 6 shows a schematic example of the ICS853014 LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK1/PCLK1 input. Zo = 50 + Zo = 50 R2 50 R1 50 3.3V R12 3.3V Zo = 50 3.3V Zo = 50 C2 0.1u 1K 11 12 13 14 15 16 17 18 19 3.3V 20 C1 0.1u U1 10 9 8 7 6 5 4 3 2 1 VEE CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VCC nEN VCC nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 R3 50 C3 0.1u Zo = 50 + Zo = 50 LVPECL Driv er R9 50 R10 50 ICS853014 R5 50 R4 50 - C5 0.1u R7 50 R11 1K R6 50 C4 0.1u Figure 6. ICS853014 Example LVPECL Clock Output Buffer Schematic IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 13 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS853014. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.94mW = 154.7mW Total Power_MAX (3.8V, with all outputs switching) = 323mW + 154.7mW = 477.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.478W * 66.6°C/W = 116.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5°C/W 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 14 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.935V (VCC_MAX – VOH_MAX) = 0.935V For logic low, VOUT = VOL_MAX = VCC_MAX – 1.67V (VCC_MAX – VOL_MAX) = 1.67V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.935V)/50Ω] * 0.935V = 19.92mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.67V)/50Ω] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 15 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA vs. Air Flow Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 114.5°C/W 73.2°C/W 200 98.0°C/W 66.6°C/W 500 88.0°C/W 63.5°C/W Transistor Count The transistor count for ICS853014 is: 373 Pin compatible with MC100LVEP14 and SY100EP14U Package Outline and Package Dimension Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.90 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 16 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number ICS853014BG ICS853014BGT ICS853014BGLF CS853014BGLFT Marking ICS853014BG ICS853014BG ICS853014BGL ICS853014BGL Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 17 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Revision History Sheet Rev Table T4B T4C B T4D Page 4 5 5 8 10 T4B - T4D C 4-5 6 1 16 4 Description of Change 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and 2.295V typical from 2.295V min. and 2.33V typical. Revised LVPECL Output Termination drawings. Revised Figure 5D. LVPECL & ECL tables - deleted VPP row. AC Table - added VPP row and changed max. value from 1200mV to 1800mV. Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free part number. Power Supply DC Characteristics Table - changed IEE from 75mA max. to 85mA max. Updated format throughout the datasheet. Corrected block diagram. 3/18/04 Date 9/10/03 C T9 4A 5/13/05 D d 1 7/6/07 11/12/07 IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 18 ICS853014BG REV. DNOVEMBER 12, 2007 ICS853014 LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 www.IDT.com © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA