IDT54FCT646TLB

IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL TRANSCEIVER/ REGISTER (3-STATE) FEATURES: • • • • IDT54/74FCT646T/AT/CT DESCRIPTION: • • • • • Std., A, and C grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: – Industrial: SOIC, SSOP, QSOP, TSSOP – Military: CERDIP, LCC The FCT646T consists of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT646T utilizes the enable control (G) and direction (DIR) pins to control the transceiver functions. SAB and SBA control pins are provided to select either real- time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data and a high selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flipflops by low-to-high transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. FUNCTIONAL BLOCK DIAGRAM G DIR CPB A SBA CPA B SAB B REG ONE OF EIGHT CHANNELS 1D C1 A1 A REG 1D C1 B1 TO SEVE N OTHER CHANN ELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES 1 JUNE 2002 DSC-5505/3 © 2002 Integrated Device Technology, Inc. IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION CPAB CPBA 27 SAB DIR SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 CPBA SBA G B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 NC A4 A5 A6 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 26 25 24 23 22 21 20 19 NC INDEX Vcc CPAB 1 24 VCC SBA G B1 B2 NC B3 B4 B5 A8 GND NC A7 B8 B7 CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +120 Unit V V °C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current PIN DESCRIPTION Pin Names A1 - A8 B1 - B8 CPAB, CPBA SAB, SBA DIR, G Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF NOTE: 1. This parameter is measured at characterization but not tested. 2 B6 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE(1) Inputs G H H L L L L DIR X X L L H H CPAB H or L ↑ X X X H or L CPBA H or L ↑ X H or L X X SAB X X X X L H SBA X X L H X X Input Output Output Input A1 - A8 Input Data I/O(2) B1 - B8 Input Isolation Store A and B Data Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Operation or Function NOTES: 1. H = HIGH L = LOW X = Don't Care ↑ = LOW-to-HIGH transition. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. 2. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 3. A in B Register. 4. B in A Register. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10% Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA — VCC = Max., VIN = GND or VCC Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 — — — — — — — — — Typ.(2) — — — — — — — –0.7 200 0.01 Max. — 0.8 ±1 ±1 ±1 ±1 ±1 –1.2 — 1 µA V mV µA Unit V V µA µA µA OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC = Min VIN = VIH or VIL Test Conditions(1) IOH = –6mA MIL IOH = –8mA IND IOH = –12mA MIL IOH = –15mA IND IOL = 48mA MIL IOL = 64mA IND Min. 2.4 2 — –60 — Typ.(2) 3.3 3 0.3 –120 — Max. — — 0.55 –225 ±1 V mA µA Unit V VOL IOS IOFF Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Max., VO = GND(3) VCC = 0V, VIN or VO ≤ 4.5V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 5. This parameter is guaranteed but not tested. 3 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES BUS A BUS B BUS A BUS B DIR L G L CPAB X CPBA X SAB X SBA L DIR H G L CPAB X CPBA X SAB L SBA X Real-Time Transfer Bus B to A Real-Time Transfer Bus A to B BUS A BUS B BUS A BUS B DIR H L X G L L H CPAB ↑ CPBA X ↑ ↑ SAB X X X SBA X X X X ↑ DIR L H G L L CPAB X H or L CPBA H or L X SAB X H SBA H X Storage From A and/or B Transfer Stores (1) Data to A and/or B NOTE: 1. Cannot transfer data to A bus and B bus simultaneously. 4 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open G = DIR = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle G = DIR = GND One Bit Toggling at fi = 5MHz VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle G = DIR = GND Eight Bits Toggling at fi = 2.5MHz VIN = 3.4V VIN = GND — 6 16.3(5) VIN = VCC VIN = GND Test Conditions(1) Min. — — Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz IC Total Power Supply Current(6) VIN = VCC VIN = GND — 1.5 3.5 mA VIN = 3.4V VIN = GND VIN = VCC VIN = GND — 2 5.5 — 3.8 7.3(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 5 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW Parameter Propagation Delay, Bus to Bus Output Enable Time, G, DIR to Bus Output Disable Time, G, DIR to Bus Propagation Delay, Clock to Bus Propagation Delay, SBA or SAB to Bus Set-up Time HIGH or LOW, Bus to Clock Hold Time HIGH or LOW, Bus to Clock Clock Pulse Width, HIGH or LOW Condition(1) CL = 50pF RL = 500Ω 54FCT646T Mil. (2) Min. Max. 2 11 2 2 2 2 4.5 2 6 15 11 10 12 — — — 54/74FCT646AT Ind. Mil. (2) (2) Min. Max. Min. Max. 2 6.3 2 7.7 2 2 2 2 2 1.5 5 9.8 6.3 6.3 7.7 — — — 2 2 2 2 2 1.5 5 10.5 7.7 7 8.4 — — — 54/74FCT646CT Ind. Mil. (2) (2) Min. Max. Min. Max. Unit 1.5 5.4 1.5 6 ns 1.5 1.5 1.5 1.5 2 1.5 5 7.8 6.3 5.7 6.2 — — — 1.5 1.5 1.5 1.5 2 1.5 5 8.9 7.7 6.3 7 — — — ns ns ns ns ns ns ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 6 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC 500Ω VIN Pulse Generator RT D.U.T . V OUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open 50pF CL 500Ω DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal link Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH tREM 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V Octal link LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE Octal link 1.5V 1.5V tSU tH Pulse Width Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V Octal link DISABLE 3V 1.5V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ 0V 3.5V 0.3V VOL VOH 0V Octal link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 7 IDT54/74FCT646T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX IDT XX FCT Device Type Temp. Range XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package Thin Shrink Small Outline Package Military Options CERDIP Leadless Chip Carrier SO PY Q PG D L 646T 646AT 646CT 54 74 Fast CMOS Octal Transceiver/Register (3-State) – 55°C to +125°C – 40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 8