IDT54FCT821A

IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER FEATURES: DESCRIPTION: IDT54/74FCT821A/B • Equivalent to AMD’s Am29821-25 bipolar registers in pinout/ function, speed and output drive over full temperature and voltage supply extremes • IDT54/74FCT821A equivalent to FAST™ speed • IDT54/74FCT821B 25% faster than FAST • IOL = 48mA (commercial) and 32mA (military) • Clamp diodes on all inputs for ringing suppression • CMOS power levels (1mW typ. static) • TTL input and output compatibility • CMOS output level compatible • Substantially lower input current levels than AMD’s bipolar Am29800 series (5µA max.) • Military product compliant to MIL-STD-883, Class B • Available in the following packages: – Commercial: SOIC – Military: CERDIP, LCC The FCT821 series is built using an advanced dual metal CMOS technology. The FCT821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The 74FCT821 is a buffered, 10-bit wide version of the popular FCT374 function. The FCT821 high-performance interface family is designed for highcapacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAM OE CP C1 D0 1D Q 23 Y TO NINE OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1 JUNE 2002 DSC-5427/2 © 2002 Integrated Device Technology, Inc. IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION OE D1 D0 NC Y1 2 6 25 24 23 22 21 20 1 3 1 4 1 5 1 6 1 7 1 8 1 9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP D2 D3 D4 NC D5 D6 D7 5 6 7 8 9 10 11 12 4 3 2 1 2 8 2 7 Y0 INDEX VCC OE 1 24 VCC Y2 Y3 Y4 NC Y5 Y6 Y7 GND NC D8 D9 Y9 CERDIP/ SOIC TOP VIEW LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) VTERM(3) TA TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current 0 to +70 –55 to +125 –55 to +125 0.5 120 –55 to +125 –65 to +135 –65 to +150 0.5 120 °C °C °C W mA –0.5 to VCC –0.5 to VCC V Commercial –0.5 to +7 Military –0.5 to +7 Unit V LOGIC SYMBOL 10 D D Q CP CP OE 10 Y NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Outputs and I/O terminals only. PIN DESCRIPTION Pin Name Dx CP I/O I I O I Description D Flip-Flop Data Inputs Clock Pulse for the Register. Enters data into the register on the LOW-to-HIGH transition Register 3-State Outputs Output Control. When the OE input is HIGH, the Yx outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Yx outputs. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF Yx OE NOTE: 1. This parameter is measured at characterization but not tested. 2 CP Y8 IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE(1) OE H H H L H L H H L L Inputs Dx L H X X X X L H L H CP ↑ ↑ X X X X ↑ ↑ ↑ ↑ Outputs Yx Z Z Z L Z NC Z Z L H Function High Z Clear Hold Load NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance NC = No Change ↑ = LOW-to-HIGH transition DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10% Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VOH Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Min., IIN = –18mA VCC = Max., VO = VCC = 3V, VIN = VLC or VHC, IOH = –32µA VCC = Min IOH = –300µA VIN = VIH or VIL IOH = –15mA MIL IOH = –24mA COM VCC = 3V, VIN = VLC or VHC, IOL = 300µA VCC = Min IOL = 300µA VIN = VIH or VIL IOL = 32mA MIL IOL = 48mA COM GND(3) Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Off State (High Impedance) Output Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND VO = VCC VO = 2.7V VO = 0.5V VO = GND Min. 2 — — — — — — — — — — –75 VHC VHC 2.4 2.4 — — — — Typ.(2) — — — — — — — — — — –0.7 –120 VCC VCC 4.3 4.3 GND GND 0.3 0.3 Max. — 0.8 5 5(4) –5(4) –5 10 10(4) –10(4) –10 –1.2 — — — — — VLC VLC(4) 0.5 0.5 Unit V V µA µA µA V mA V VOL Output LOW Voltage V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed, but not tested. 3 IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS VLC = 0.2V, VHC = VCC - 0.2V Symbol ICC ∆ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN ≥ VHC; VIN ≤ VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle VIN ≥ VHC VIN ≤ VLC Min. — — — Typ.(2) 0.2 0.5 0.15 Max. 1.5 2 0.25 Unit mA mA mA/ MHz IC Total Power Supply Current(6) VIN ≥ VHC VIN ≤ VLC VIN = 3.4V VIN = GND — 1.7 4 mA — 2.2 6 VIN ≥ VHC VIN ≤ VLC VIN = 3.4V VIN = GND — 4 7.8(5) — 6.2 16.8(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE IDT54/74FCT821A Com’l. Parameter Description tPLH tPHL Propagation Delay CP to Yx (OE = LOW) Conditions(1) CL = 50pF RL = 500Ω CL = 300pF(3) RL = 500Ω tSU tH tW tPZH tPZL Set-up Time HIGH or LOW, Dx to CP Hold Time HIGH or LOW, Dx to CP CP Pulse Width, HIGH or LOW Output Enable Time OE to Yx CL = 50pF RL = 500Ω CL = 50pF RL = 500Ω CL = 300pF(3) RL = 500Ω tPHZ tPLZ Output Disable Time OE to Yx CL = 5pF(3) RL = 500Ω CL = 50pF RL = 500Ω NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. IDT54/74FCT821B Mil. Com’l. Max. 11.5 20 — — — 13 25 8 9 Min.(2) — — 3 1.5 6 — — — — Max. 7.5 15 — — — 8 15 6.5 7.5 — — 3 1.5 6 — — — — Mil. Min.(2) Max. 8.5 16 — — — 9 16 7 8 ns ns ns Unit Min.(2) — — 4 2 7 — — — — Max. 10 20 — — — 12 23 7 8 Min.(2) — — 4 2 7 — — — — ns 5 IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC 500Ω VIN Pulse Generator RT D.U.T . V OUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low Switch Closed Open 50pF CL 500Ω All Other Tests DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal link Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH tREM 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V Octal link LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE Octal link 1.5V 1.5V tSU tH Pulse Width Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V Octal link DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V Octal link CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ VOL Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT54/74FCT821/A/B HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX FCT IDT XX Temp. Range Device Type XX Package X Process Blank B Commercial MIL-STD-883, Class B Commercial Options Small Outline IC Military Options CERDIP Leadless Chip Carrier SO D L 821A 821B High Performance CMOS Bus Interface Register, 10-Bit 54 74 – 55°C to +125°C 0°C to +70°C DATA SHEET DOCUMENT HISTORY 6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: logichelp@idt.com (408) 654-6459