IDT5P49EE502

DATASHEET VERSACLOCK® LOW POWER CLOCK GENERATOR Description The IDT5P49EE502 is a programmable clock generator intended for low power, battery operated consumer applications. There are four internal PLLs, each individually programmable, allowing for up to five differrent output frequencies. The frequencies are generated from a single reference clock. The reference clock can come from either a TCXO or fundamental mode crystal. The IDT5P49EE502 can be programmed through the use of the I2C interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation is supported on one of the PLLs. Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise. It also may operate in standard spread sepctrum mode. There are total four 8-bit output dividers. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed. IDT5P49EE502 Features • Four internal PLLs • Internal non-volatile EEPROM • Internal I2C EEPROM master interface • FAST (400kHz) mode I2C serial interfaces • Input Frequencies – TCXO: 10 MHz to 40 MHz – Crystal: 8 MHz to 30 MHz • Output Frequency Ranges: kHz to 120 MHz • Each PLL has an 8-bit reference divider and a 11-bit feedback-divider • 8-bit output-divider blocks • One of the PLLs support Spread Spectrum generation capable of configuration to pixel rate, with adjustable modulation rate and amplitude to support video clock with no visible artifacts • I/O Standards: – Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS • • • • • • 2 independent adjustable VDDO groups. Programmable Slew Rate Control Programmable Loop Bandwidth Settings Programmable output inversion to reduce bimodal jitter Individual output enable/disable Power-down/Sleep mode – 10μA max in power down mode • 1.8V VDD Core Voltage • Available in 20pin 3x3mm QFN packages • -40 to +85 C Industrial Temp operation Target Applications • • • • • • Smart Mobile Handset Personal Navigation Device (PND) Camcorder DSC Portable Game Console Personal Media Player IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 1 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Functional Block Diagram VDD VDDO1 VDDO2 S R C 0 XIN/ REF PLLA S R C 1 S R C 2 S R C 3 S R C 4 PLLD / DIV0 OUT0 XOUT /DIV1 OUT1 /DIV2 OUT2 PLLB(SS) SDA SCL SEL Control Logic /DIV3 OUT3 PLLC /DIV4 OUT4 GND IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 2 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Pin Assignment GND VDD VDDO2 SDA XOUT XIN/REF GND OUT3 SEL0 11 6 OUT4 16 1 OUT0 SCLK GND SEL1 OUT1 VDD VDDx VDDO1 GND 20- pin QFN Pin Descriptions Pin Name XOUT XIN/ REF GND OUT3 SEL0 VDD VDDx VDDO1 Pin # 1 2 3 4 5 6 7 8 I/O O I Pin Type LVTTL LVTTL Power OUT2 Pin Description MHz CRYSTAL_OUT -- Reference crystal feedback. MHz CRYSTAL_IN -- Reference crystal input or external reference clock input. Connect to Ground. Buffered reference clock output. Single-ended output voltage levels are register controlled by either VDDO1 or VDDO2. Configuration select pin. Weak internal pull down resistor. Device power supply. Connect to 1.8V. Device power supply. Connect to 1.8V. Device power supply. Connect to 1.8 to 3.3V. VDDO1 must be the highest voltage on the device. Using register settings, select output voltage levels for OUT0-OUT3. Connect to Ground. Configurable clock output 2. Single-ended output voltage levels are register controlled by either VDDO1 or VDDO2. Configurable clock output 1. Single-ended output voltage levels are register controlled by either VDDO1 or VDDO2. Configuration select pin. Weak internal pull down resistor. Connect to Ground. I2C clock. O I OUTPUT LVTTL Power Power Power GND OUT2 OUT1 SEL1 GND SCLK 9 10 11 12 13 14 I O O I Power Adjustable Adjustable LVTTL Power LVTTL IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 3 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR OUT0 OUT4 SDA VDDO2 VDD GND 15 16 17 18 19 20 O O I/O Adjustable Adjustable Configurable clock output 0. Single-ended output voltage levels are register controlled by either VDDO1 or VDDO2. Configurable clock output 8. Single-ended output voltage levels controlled by VDDO2. Open Drain Bidirectional I2C data. Power Power Power Device power supply. Connect to 1.8 to 3.3V. Using register settings, select output voltage levels for OUT0-OUT4. Device power supply. Connect to 1.8V. Connect to Ground. Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above. Alway completely power up VDD and VDDx prior to applying VDDO power. Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 4 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR PLL Features and Descriptions 8-bit D VCO 1-bit 11-bit A M PLL Block Diagram Ref-Divider (D) Values Feedback Pre-Divider (XDIV) Values 1 or 41 4 1 or 8 bit divide2 1 or 41 Feedback (M) Values Programmable Spread Spectrum Loop Bandwidth Generation Capability PLLA PLLB PLLC PLLD 1 - 255 1 - 255 1 - 255 1 - 255 6 - 2047 6 - 2047 6 - 2047 6 - 2047 Yes Yes Yes Yes No Yes No No 1.XDIVA or XDIVD=0, A=1. XDIVA or XDIVD=1, A=4. 2.XDIVC =0, A=1. XDIVC=1 turns on 8 bit predivide multiplier, A=FBC2[7:0]. Total feedback divide equals FBC[10:0] *FBC2[7:0]. Crystal Input (XIN/REF) The crystal oscillators should be fundamental mode quartz crystals; overtone crystals are not suitable. Crystal frequency should be specified for parallel resonance with 50Ω maximum equivalent series resonance. Reference Pre-Divider, Reference Divider, Feedback-Divider and Post-Divider Each PLL incorporates an 8-bit reference-scaler and a 11-bit feedback divider which allows the user to generate four unique non-integer-related frequencies. PLLA and PLLD each have a feedback pre-divider that provides additional multiplication for kHz reference clock applications. Each output divider supports 8-bit post-divider. The following equation governs how the output frequency is calculated. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The crystal cpacitors are internal to the device and have an effective value of 8pF. FOUT = FIN * ( A*M ) D ODIV (Eq. 2) Where FIN is the reference frequency, A is the feedback pre-divider value, M is the feedback-divider value, D is the reference divider value, ODIV is the total post-divider value, and FOUT is the resulting output frequency. Programming any of the dividers may cause glitches on the outputs. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 5 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR SPREAD SPECTRUM GENERATION (PLLB) PLLB has spread spectrum generation capability, which users have the option of turning on and off. Spread spectrum profile, frequency, and spread are fully programmable (within limits). The programmable spread spectrum generation parameters are NC[10:0], MOD[12:0], and NSS[10:0] bits. To enable spread spectrum, set SSENB_B=0. The spread spectrum circuitry was specifically developed to accommodate video display applications. The spread modulation frequency can be defined to exactly equal the horizontal line frequency (HSYNC) Modulation frequency: FMOD = FMID / NC (Eq. 11) Video Example FREF = 27 MHz, FOUT = 27 MHz, 640 pixels per line, center spread of ±1%. Using FVCO=432MHz, find the necessary spread spectrum register settings. FMID = FVCO/8 NC = 640 (integer number of spread periods/screen) MOD = (25MHz * 640)/(2 * 54MHz) = 160 NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz = 321. FMOD = 27MHz/640 = 11.8kHz. NC[10:0] These bits are used to determine the number of pulses per spread spectrum cycle. For video applications, NC is the number of pixels on the horizontal display row (or integer multiple of displayed pixels in a row). By matching the spread period to the screen, no tearing or “shimmer” will be apparent. NC must be an even number to insure that the upward spread transition has the same number of steps as the downward spread transition. For non-video applications, this can also be seen as the number of clock cycles for a complete spread spectrum period. Non-Video Example FREF = 25MHz, FOUT = 27 MHz, 31.25kHz modulation rate, center spread of ±1%. Find the necessary spread spectrum register settings. FMID = FVCO/ 8 FMOD = 31.25kHz = 50.625MHz/NC. NC = 1620 MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400 MOD[12:0] These bits relate the VCO frequency to the target average spread output frequency (FMID). FMID = (FVCO) / 8 FMAX = FMID + (SS% * FMID) FMIN = FMID - (SS% * FMID) MOD = (FREF* NC) / (2 * FMID) NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz = 814. NSS[10:0] These bits control the amplitude of the spread modulation. NSS = (NC / 2) + (NC / 8) * (FMAX - FMIN) / FMID IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 6 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship VSYNC HSYNC Integer multiple of HSYNC periods DOT_CLK Modulation Rate X/2 X/2 X X = Number of cycles of DOT_CLK per HSYNC period. X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls. X Zero capacitor (Cz) = 280pF LOOP FILTER The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide loop bandwidth is best for low jitter generation. The specific loop filter components that can be programmed are the resistor via the RZ[4:0] bits, zero capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0] bits, and the charge pump current via the IP#[2:0] bits. The following equations govern how the loop filter is set: Pole capacitor (Cp) = 30pF Charge pump (Ip) = IP#[2:0] uA VCO gain (KVCO) = 350MHz/V * 2π IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 7 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Example Fc = 150KHz is the desired loop bandwidth. The total A*M value is 160. The ζ(damping factor) target should be 0.7, meaning the loop is critically damped. Given Fc and A*M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain loop stability. Choose a mid-range charge pump from register table Icp= 11.9uA. Kφ * KVCO = 300MHz/V * 40uA = 12000A/Vs PLL Loop Bandwidth: Charge pump gain (Kφ⎞) = Ip / 2π VCO gain (KVCO) = 950MHz/V * 2π M = Total multiplier value (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail) ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp)) Fc = ωc / 2π Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce your phase margin thus compromising loop stability. To determine if the loop is stable, the phase margin (φm) would need to be calculated as follows. ωc = 2π * Fc = 9.42x105 s-1 ωp = (Cz + Cp)/(Rz * Cz * Cp) = ωz (1 + Cz / Cp) Solving for Rz, the best possible value Rz=30kOhms (RZ[1:0]=10) gives ζ= 1.2 Solving back for the PLL loop bandwidth, Fc=149kHz. The phase margin must be checked for loop stability. φm = (360 / 2π) * [tan-1 (9.42x105 s-1 / 1.19x105s-1) - tan-1(9.42x105 s-1/ 1.23x106 s-1)] = 45° The phase margin would be acceptable with a fairly stable loop. Phase Margin: ωz = 1 / (Rz * Cz) ωp = (Cz + Cp)/(Rz * Cz * Cp) φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)] To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 8 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR SEL[1:0] Function The IDT5P49EE502 can support up to three unique configurations. Users may pre-programmed all these configurations, and select the configurations using SEL[1:0] pins. Alternatively, users may use I2C interface to configure these registers on- the-fly. SEL1 0 0 1 1 Always power with SEL1=1 and/or SEL0=1. Power Down/Sleep Mode is selected by the No_PD bit. No_PD=0 enables Power Down mode with no outputs. No_PD=1 enables sleep mode with 32kHz output on OUT4. SEL0 0 1 0 1 Select CONFIG0 Select CONFIG1 Select CONFIG2 Configuration Selections Power Down/Sleep Mode Configuration OUTx IO Standard Users can configure the individual output IO standard from a single 1.8V power supply. Each output can support 1.8V/ 2.5V or 3.3V LVCMOS. VDDO1 must have the highest voltage of any pin on the device. VDDO2 may have any value between 1.8V and VDDO1. Programming the Device I2C may be used to program the IDT5P49EE502. – Device (slave) address = 7'b1101010 The frame formats are shown in the following illustration. I2C Programming The IDT5P49EE502 is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read. Framing First Byte Transmitted on I2C Bus IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 9 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR External I2C Interface Condition EEPROM Interface The IDT5P49EE502 can store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore). To initiate a save or restore using I C, only two bytes are transferred. The Device Address is issued with the read/write bit set to “0”, followed by the appropriate command code. The save or restore instruction executes 2 after the STOP condition is issued by the Master, during which time the IDT5P49EE502 will not generate Acknowledge bits. The IDT5P49EE502 will acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted as busy by all other users of the bus. On power-up of the IDT5P49EE502, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The IDT5P49EE502 will be ready to accept a programming instruction once it acknowledges its 7-bit I2C address. Progwrite Progwrite Command Frame Writes can continue as long as a Stop condition is not sent and each byte will increment the register address. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 10 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Progread Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known “read” register address prior to a read operation by issuing the following command: Prior to Progread Command Set Register Address The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by the Progread command): Progread Command Frame Progsave Note: PROGWRITE is for writing to the IDT5P49EE502 registers. PROGREAD is for reading the IDT5P49EE502 registers. PROGSAVE is for saving all the contents of the IDT5P49EE502 registers to the EEPROM. PROGRESTORE is for loading the entire EEPROM contents to the IDT5P49EE502 registers. Progrestore During PROGRESTORE, outputs will be turned off to ensure that no improper voltage levels are experienced before initialization. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 11 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR I2C Bus DC Characteristics Symbol VIH VIL VHYS IIN VOL Parameter Input HIGH Level Input LOW Level Hysteresis of Inputs Input Leakage Current Output LOW Voltage Conditions Min 0.7xVDD 0.05xVDD Typ Max 5.5 0.3xVDD Unit V V V µA V VDD = 0V IOL = 3 mA ±1.0 0.4 I2C Bus AC Characteristics for Standard Mode1 Symbol FSCLK tBUF tSU:START tHD:START tSU:DATA tHD:DATA tOVD CB tR tF tHIGH tLOW tSU:STOP Parameter Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, START Hold Time, START Setup Time, data input (SDA) Hold Time, data input (SDA)2 Output data valid from clock Capacitive Load for Each Bus Line Rise Time, data and clock (SDA, SCLK) Fall Time, data and clock (SDA, SCLK) HIGH Time, clock (SCLK) LOW Time, clock (SCLK) Setup Time, STOP Min 0 4.7 4.7 4 250 0 Typ Max 100 Unit kHz µs µs µs ns µs 3.45 400 1000 300 4 4.7 4 µs pF ns ns µs µs µs 1) No activity is allowed on I2C lines until VDD>1.62V. 2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge of SCLK. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 12 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR I2C Bus AC Characteristics for Fast Mode1 Symbol FSCLK tBUF tSU:START tHD:START tSU:DATA tHD:DATA tOVD CB tR tF tHIGH tLOW tSU:STOP Parameter Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, START Hold Time, START Setup Time, data input (SDA) Hold Time, data input (SDA) Output data valid from clock Capacitive Load for Each Bus Line Rise Time, data and clock (SDA, SCL) Fall Time, data and clock (SDA, SCL) HIGH Time, clock (SCL) LOW Time, clock (SCL) Setup Time, STOP 1 Min 0 1.3 0.6 0.6 100 0 Typ Max 400 Unit kHz µs µs µs ns µs 0.9 400 20 + 0.1xCB 20 + 0.1xCB 0.6 1.3 0.6 300 300 µs pF ns ns µs µs µs 1) No activity is allowed on I2C lines until VDD>1.62V. 2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 13 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5P49EE502. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Symbol VDD VI VO TJ TSTG Input Voltage Description Internal Power Supply Voltage Output Voltage (not to exceed 4.6 V) Junction Temperature Storage Temperature Max -0.5 to +4.6 -0.5 to +4.6 -0.5 to VDD+0.5 150 -65 to +150 Unit V V V °C °C Recommended Operation Conditions Symbol VDD TA Parameter Power supply voltage for VDD Operating temperature, ambient Min 1.62 -40 Typ 1.8 Max 1.98 +85 15 8 Unit V °C pF pF MHz ms CLOAD_OUT Maximum load capacitance (3.3V LVTTL only) CLOAD_OUT Maximum load capacitance (1.8V or 2.5V LVTTL only) FIN tPU External reference crystal External reference clock CLKIN Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 8 1 0.05 30 40 5 Capacitance (TA = +25 °C, f = 1 MHz, VIN = 0V) Symbol CIN XTAL_FREQ XTAL_MIN XTAL_MAX XTAL_VPP Input Capacitance Crystal frequency Minimum crystal load capacitance Maximum crystal load capacitance Voltage swing (peak-to-peak, nominal) 1.5 8 TBD 35.4 2.3 3.2 Crystal Specifications 30 MHz pF pF V Parameter Min Typ 3 Max Unit pF IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 14 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR DC Electrical Characteristics for 3.3 Volt LVTTL 1 Symbol VOH VOL VIH VIL IOZDD Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions IOH = 33mA IOH = 33mA Min 2.4 2 Typ Max VDDO 0.4 0.8 5 Unit V V V V µA Output Leakage Current 3-state outputs DC Electrical Characteristics for 2.5Volt LVTTL 1 Symbol VOH VOL IOZDD Parameter Output HIGH Voltage Output LOW Voltage Test Conditions IOH = 25mA IOH = 25mA Min 2.1 Typ Max VDDO 0.4 5 Unit V V µA Output Leakage Current 3-state outputs DC Electrical Characteristics for 1.8Volt LVTTL 1 Symbol VOH VOL IOZDD Parameter Output HIGH Voltage Output LOW Voltage Test Conditions VDD = 1.71V to 1.89V Min 0.65*VDDO Typ Max VDDO 0.35*VDDO 5 Unit V V µA Output Leakage Current 3-state outputs Power Supply Characteristics for LVTTL Outputs Symbol ITOT Parameter Total Power VDD Supply Current Test Conditions FREFERENCE CLOCK = 25 MHz, CL = 7 pF Typ TBD Max Unit mA 1: See “Recommended Operating Conditions” table. Alway completely power up VDD and VDDx prior to applying VDDO power. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 15 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR AC Timing Electrical Characteristics (Spread Spectrum Generation = OFF) Symbol fIN 1 / t1 Parameter Input Frequency Output Frequency Test Conditions Input Frequency Limit (CLKIN) Single Ended Clock output limit (LVTTL) 3.3V Single Ended Clock output limit (LVTTL) 2.5V Single Ended Clock output limit (LVTTL) 1.8V Min. 11 0.001 Typ. Max. 40 120 110 100 Units MHz MHz MHz MHz MHz MHz % % V/ns fVCO fPFD t2 t3 t4 VCO Frequency PFD Frequency Input Duty Cycle Output Duty Cycle Slew Rate, SLEWx(bits) = 00 VCO operating Frequency Range PFD operating Frequency Range Duty Cycle for Input Measured at VDD/2 Single-Ended 3.3V LVCMOS Output clock rise and fall time, 20% to 80% of VDD (Output Load = 7 pF) Single-Ended 3.3V LVCMOS Output clock rise and fall time, 20% to 80% of VDD (Output Load = 7 pF) Single-Ended 3.3V LVCMOS Output clock rise and fall time, 20% to 80% of VDD (Output Load = 7 pF) Single-Ended 3.3V LVCMOS Output clock rise and fall time, 20% to 80% of VDD (Output Load = 7 pF) Peak-to-peak period jitter, CLK outputs measured at VDD/2; fPFD >= 10 MHz Single output frequency only. Peak-to-peak period jitter, CLK outputs measured at VDD/2; fPFD >= 10 MHz Multiple output frequencies switching. 100 0.5 40 45 3.5 1 475 20 60 55 Slew Rate, SLEWx(bits) = 01 2.75 Slew Rate, SLEWx(bits) = 10 2 Slew Rate, SLEWx(bits) = 11 1.25 t5 Clock Jitter 100 ps 200 ps t6 t7 Output Skew Lock Time Skew between any output (Same freq and IO type, FOUT >10MHz) PLL Lock Time from Power-up (using MHz reference clock)2 PLL Lock time from shutdown mode 5 200 20 5 ps ms ms 1.Input clock (square wave) may be used at 1 MHz. 2.Time from supply voltage crosses VDD=1.62V to PLLs are locked. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 16 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Spread Spectrum Generation Specifications Symbol fIN fMOD fSPREAD Parameter Input Frequency Input Frequency Limit Mod Frequency Spread Value Modulation Frequency Description Min 11 32 Typ Max 40 120 Unit MHz kHz %fOUT Amount of Spread Value (programmable) - Down Spread Amount of Spread Value (programmable) - Center Spread Programmable Programmable 1) Practical lower frequency is determined by loop filter settings. Test Circuits and Conditions 1 Test Circuits for DC Outputs Other Termination Scheme (Block Diagram) LVTTL Output Load: ~7pF for each output IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 17 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Programming Registers Table Default Register Addr Hex Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Reserved INV[4] SLEW4[0:1] Reserved Reserved Reserved Reserved REFA[7:0] Configuration0 REFA[7:0] - Reference Divide PLLA FBA[10:0] - Feedback Divide PLLA FBA[2:0) IPA[2:0] Reserved XDIVA - FB predivide PLLA; 0 - /1; 1 - /4 RZA[1:0] - Zero Resistor PLLA 00 - 5kOhm 01 - 10kOhm 10 - 30kOhm 11 - 80kOhm IPA[2:0] - charge Pump Current PLLA 100 - 6.3uA 101 -11.9 uA 110 - 17.7 uA 111 - 22.7uA REFB[7:0] - Reference Divide PLLB FBB[10:0] - Feedback Divide PLLB FBB[2:0] MOD[12:5] NC[10:3] NSS[4:0] NSS[12:5] Reserved Reserved IPB[2:0] RZB[1:0] SSENB_B RZB[1:0] - Zero Resistor PLLB 00 - 5kOhm 01 - 10kOhm 10 - 30kOhm 11 - 80kOhm IPB[2:0] - charge Pump Current PLLB 000 - 0.37uA, 100 - 6.3uA 001 - 1.1uA, 101 - 11.9uA 010 - 1.8 uA, 110 - 17.7uA 011 - 3.4uA, 111 - 22.7uA REFC[7:0] - Reference Divide PLLC FBC[10:0] - Feedback Divide PLLC FBC[2:0] FBC2[7:0] FBC2 - Feedback Predivide PLLC Turn on using XDIVC=1 NC[2:0] PLLB Spread Parameters MOD[12:0] NC[10:0] NSS[12:0] INV[1] INV[2] INV[3] SLEW1[0:1] SLEW2[0:1] SLEW3[0:1] Bit # 7 ONXTALB INV[0] SLEW1[0:1] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PS1[2:1] PS2[2:1] PS3[2:1] Reserved Reserved Reserved 6 5 4 3 Reserved PS0[2:1] 2 1 0 Description ONXTALB - MHz Crystal active low Reserved INV[#] - Invert output# SLEW#[0:1] - output# slew setting 0 0 - 5.1V/ns 0 1 - 4.4V/ns 1 0 - 2.8V/ns 1 1 - 1.8V/ns PS#[2:1] -Power Select 00 - Reserved 01 - OUT# connects to VDDO1 10 - OUT# connects to VDDO2 11 - Reserved CLK4 is tied to VDD02 0x0F 0x10 0x11 00 00 00 Reserved XDIVA Reserved RZA[1:0] FBA[10:3) 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 00 00 00 00 00 00 00 20 00 MOD[4:0] REFB[7:0] FBB[10:3] 0x1B 0x1C 0x1D 0x1E 00 00 00 00 Reserved REFC[7:0] FBC[10:3] IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 18 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Default Register Addr Hex Value 0x1F 00 Bit # 7 6 IPC[2:0] 5 4 RZC[1:0] 3 2 Reserved 1 XDIVC 0 Reserved Description RZC[1:0] - Zero Resistor PLLC 00 - 5kOhm 01 - 10kOhm 10 - 30kOhm 11 - 80kOhm IPC[2:0] - charge Pump Current PLLC 100 - 6.3uA 101 -11.9 uA 110 - 17.7 uA 111 - 22.7uA REFD[7:0] - Reference Divide PLLD FBD[10:0] - Feedback Divide PLLD 0x20 0x21 0x22 0x23 00 00 00 00 XDIVD Reserved RZD[1:0] REFD[7:0] FBD[10:3] FBD[2:0] IPD[2:0] Reserved XDIVD - FB predivide PLLD; 0 - /1; 1 - /4 RZD[1:0] - Zero Resistor PLLD 00 - 5kOhm 01 - 10kOhm 10 - 30kOhm 11 - 80kOhm IPD[2:0] - charge Pump Current PLLD 100 - 6.3uA 101 -11.9 uA 110 - 17.7 uA 111 - 22.7uA 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 00 00 00 00 00 00 00 00 00 00 SCR4[1:0] OD0[7:0] Reserved Reserved OD1[7:0] OD2[7:0] OD3[7:0] Reserved Reserved OD4[7:0] Reserved SCR3[1:0] SRC3[1:0] - OD4 source 00 - off; 10 - PLLA 01 - Reference; 11 - PLLD SRC4[1:0] - OD4 source 00 - off; 10 - PLLC 01 - PLLA; 11 - Reference SRC1[1:0] - OD1 source 00 - off; 10 - PLLB 01 - PLLA; 11 - PLLD SRC2[1:0] - OD2 source 00 - off; 10 - PLLC 01 - PLLA; 11 - PLLD SRC0[1:0] - OD0 source 00 - off; 10 - PLLC 01 - PLLB; 11 - PLLD Reserved OE[1] PDB[1] Reserved Reserved OE[0] PDB[0] PDB[4:0] - Powerdown OUT#. PDB#=0, OUT# driven low OE[4:0] - Output enable OUT#. OE#=0, OUT# tri-stated. If PDB#=OE#=0, OUT# driven low 0x2E 00 SCR2[1:0] SCR1[1:0] Reserved 0x2F 0x30 0x31 0x32 0x33 00 00 00 00 00 SCR0[1:0] Reserved PDB[4] Reserved Reserved Reserved OE[3] PDB[3] OE[4] OE[2] PDB[2] Reserved IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 19 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Default Register Addr Hex Value 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Bit # 7 6 5 4 REFA[7:0] FBA[10:3) Reserved Reserved XDIVA RZA[1:0] REFB[7:0] FBB[10:3] MOD[4:0] MOD[12:5] NC[10:3] NSS[4:0] NSS[12:5] Reserved Reserved REFC[7:0] FBC[10:3] Reserved FBC2[7:0] IPC[2:0] RZC[1:0] REFD[7:0] FBD[10:3] Reserved XDIVD RZD[1:0] IPD[2:0] OD0[7:0] Reserved Reserved OD1[7:0] OD2[7:0] OD3[7:0] Reserved Reserved OD4[7:0] SCR4[1:0] SCR2[1:0] SCR0[1:0] Reserved PDB[4] Reserved Reserved Reserved OE[3] PDB[3] OE[4] OE[2] PDB[2] OE[1] PDB[1] Reserved Reserved Reserved OE[0] PDB[0] SCR1[1:0] Reserved Reserved Reserved SCR3[1:0] FBD[2:0] Reserved Reserved XDIV Reserved FBC[2:0] IPB[2:0] Reserved RZB[1:0] SSENB_B NC[2:0] FBB[2:0] IPA[2:0] FBA[2:0) Reserved 3 2 1 0 Description Configuration1 (See definitions from Configuration0 above) IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 20 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Default Register Addr Hex Value 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Bit # 7 6 5 4 REFA[7:0] FBA[10:3) Reserved Reserved XDIVA RZA[1:0] REFB[7:0] FBB[10:3] MOD[4:0] MOD[12:5] NC[10:3] NSS[4:0] NSS[12:5] Reserved Reserved REFC[7:0] FBC[10:3] Reserved FBC2[7:0] IPC[2:0] RZC[1:0] REFD[7:0] FBD[10:3] Reserved XDIVD RZD[1:0] IPD[2:0] OD0[7:0] Reserved Reserved OD17:0] OD2[7:0] OD3[7:0] Reserved Reserved OD4[7:0] SCR4[1:0] SCR2[1:0] SCR0[1:0] Reserved PDB[4] Reserved Reserved Reserved OE[3] PDB[3] OE[4] OE[2] PDB[2] OE[1] PDB[1] Reserved Reserved Reserved OE[0] PDB[0] SCR1[1:0] Reserved Reserved Reserved SCR3[1:0] FBD[2:0] Reserved Reserved XDIV Reserved FBC[2:0] IPB[2:0] Reserved RZB[1:0] SSENB_B NC[2:0] FBB[2:0] IPA[2:0] FBA[2:0) Reserved 3 2 1 0 Description Configuration2 (See definitions from Configuration0 above) IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 21 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Marking Diagram (ND20) YYWW 2DGI Notes: 1. “Z” is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “$” is the assembly mark code. 4. “G” after the two-letter package code designates RoHS compliant package. 5. “I” at the end of part number indicates industrial temperature range. 6. Bottom marking: country of origin if not USA. Thermal Characteristics 20-pin VFQFPN Parameter Thermal Resistance Junction to Ambient Symbol θJA θJA θJA θJC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. Max. Units ° C/W ° C/W ° C/W ° C/W Thermal Resistance Junction to Case IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 22 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR 20-pin QFN Solder Mask ZDMAX = 3.26 mm D2 = 1.75 mm ZEMAX = 3.26 mm GEMIN = 2.05 mm AEMAX = 1.83 mm E2 = 1.75 mm ADMAX = 1.83 mm GDMIN = 2.05 mm Y = 0.61 mm X = 0.23 mm IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 23 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Package Outline and Package Dimensions (20-pin QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area N 1 2 A1 A3 (ND -1)x e (Ref) L N 1 Sawn Singulation Top View A E2 C0.35 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE -1)x e (Ref) 2 E E2 2 b D (Ref) ND & NE Odd e D2 2 D2 Thermal Base C 0.08 C Symbol Min Millimeters Max A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.25 Reference 0.15 0.23 0.40 BASIC 20 5 5 3.00 x 3.00 1.55 1.75 1.55 1.75 0.30 0.50 Ordering Information Part / Order Number 5P49EE502NDGI 5P49EE502NDGI8 Marking See page 22 See page 22 Shipping Packaging Tubes Tape and Reel Package 20pin VFQFPN 20pin VFQFPN Temperature -40 to +85° C -40 to +85° C Parts that are ordered with a “G” after the two-letter pacakage code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 24 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Revision History Rev. -A B C D Originator R.Willner R.Willner R.Willner R. Willner Date 10/27/09 11/10/09 3/25/10 6/11/10 07/26/10 Description of Change Initial Preliminary Datasheet Revised pinout. Typographical changes. Register corrections. Correct spread spectrum calculations. Default configuration. Clarification of OUT4 is tied to VDDO2. Updated thermal pad and dimensions on package drawing. IDT® VERSACLOCK® LOW POWER CLOCK GENERATOR 25 IDT5P49EE502 REV D 072610 IDT5P49EE502 VERSACLOCK® LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA