IDT5V49EE504

DATASHEET EEPROM PROGRAMMABLE CLOCK GENERATOR Description The IDT5V49EE504 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The IDT5V49EE504 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of four 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable. IDT5V49EE504 Features • • • • • • Four internal PLLs Internal non-volatile EEPROM Fast (400kHz) mode I2C serial interface Input frequency range: 1 MHz to 200 MHz Output frequency range: 4.9 kHz to 200 MHz Reference crystal input with programmable linear load capacitance – Crystal frequency range: 8 MHz to 50 MHz • Two independently controlled VDDO (1.8V - 3.3V) • Each PLL has a 7-bit reference divider and a 12-bit feedback-divider • 8-bit output-divider blocks • Fractional division capability on one PLL • Two of the PLLs support spread spectrum generation capability • I/O Standards: – Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS – Inputs - 3.3 V LVTTL/ LVCMOS • • • • • • • • • Programmable slew rate control Programmable loop bandwidth Programmable output inversion to reduce bimodal jitter Redundant clock inputs with glitchless auto and manual switchover options Individual output enable/disable Power-down mode 3.3V core VDD Available in VFQFPN package -40 to +85 C Industrial Temp operation IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 1 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Functional Block Diagram S R C 0 S R C 1 S R C 2 S1 OUT0 XIN/REF XOUT PLL0 (SS) /DIV1 OUT1 CLKIN PLL1 /DIV2 OUT2 CLKSEL PLL2 PLL3 (SS) S R C 3 S R C 6 S3 /DIV3 OUT3 SD/OE SDA SCL SEL[2:0] /DIV6 OUT6 Control Logic 1. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 2 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Pin Configuration OUT0 SD/OE SEL0 SEL1 GND SEL2 19 VDD XOUT XIN/REF VDDx CLKIN GND 1 VDDO3 OUT3 OUT6 GND AVDD 7 13 CLKSEL OUT2 VDDO1 OUT1 SDAT 24-pin QFN Pin Descriptions Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name VDD XOUT XIN / REF SCLK VDD I/O O I Pin Type Power LVTTL LVTTL Power Pin Description Device power supply. Connect to 3.3V. CRYSTAL_OUT -- Reference crystal feedback. CRYSTAL_IN -- Reference crystal input or external reference clock input. Crystal oscillator power supply. Connect to 3.3V. Use filtered analog power supply if available. Input clock. Weak internal pull down resistor. Connect to Ground. Configurable clock output 1. Output levels controlled by VDDO1. Configurable clock output 2. Output levels controlled by VDDO1. Device power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT1 and OUT2. Device power supply. Connect to 3.3V. Bidirectional I2C data. I2C clock. Input clock selector. Weak internal pull down resistor. Device analog power supply. Connect to 3.3V. Use filtered analog power supply if available. Connect to Ground. Configurable clock output 6. Output levels controlled by VDDO3. Configurable clock output 3. Output levels controlled by VDDO3. Device power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for OUT3 and OUT6. VDDx CLKIN GND OUT1 OUT2 O O I LVTTL Power LVTTL LVTTL Power Power VDDO1 VDD SDAT SCLK CLKSEL AVDD GND OUT6 OUT3 O O I/O I I LVTTL LVTTL LVTTL Power Power LVTTL LVTTL Power VDDO3 IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 3 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Pin# 19 20 21 22 Pin Name SEL2 SEL1 SEL0 SD/OE I/O I I I I Pin Type LVTTL LVTTL LVTTL LVTTL Pin Description Configuration select pin. Weak internal pull down resistor. Configuration select pin. Weak internal pull down resistor. Configuration select pin. Weak internal pull down resistor. Enables/disables the outputs or powers down the chip. The SP bit (0x02) controls the polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.) Weak internal pull down resistor. Configurable clock output 0. Connect to Ground. 23 24 OUT0 GND O LVTTL Power IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 4 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER PLL Features and Descriptions 7-bit D VCO 4-bit A 12-bit N Sigm a-Delta M odulator PLL0 Block Diagram 7-bit D VCO 12-bit N PLL1, PLL2 and PLL3 Block Diagram Pre-Divider (D)1 Values PLL0 PLL1 PLL2 PLL3 1 - 127 1 - 127 1 - 127 3 - 127 Multiplier (M)2 Values 10 - 8206 1 - 4095 1 - 4095 12 - 4095 Programmable Spread Spectrum Loop Bandwidth Generation Capability Yes Yes Yes Yes Yes No No Yes 1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use) 2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 5 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Reference Clock Input Pins and Selection The IDT5V49EE504 supports up to two clock inputs. One of the clock inputs (XIN/ REF) can be driven by either an external crystal or a reference clock. The second clock input (CLKIN) can only be driven from an external reference clock. The CLKSEL pin selects the input clock from either XTAL/REF or CLKIN. Either clock input can be set as the primary clock. The primary clock designation is to establish which is the main reference clock to the PLLs. The non-primary clock is designated as the secondary clock in case the primary clock goes absent and a backup is needed. The PRIMSRC bit (0xBE through 0xC3) determines which clock input will be selected as primary clock. When PRIMSRC bit is "0", XIN/REF is selected as the primary clock, and when "1", CLKIN as the primary clock. The two external reference clocks can be manually selected using the CLKSEL pin. The SM bits (0xBE through 0xC3) must be set to "0x" for manual switchover which is detailed in SWITCHOVER MODES section. internal load capacitance is set. XTAL load cap = 3.5 pF + XTAL[4:0] * 0.125 pF (Eq. 1) Parameter XTAL Bits 8 Step (pF) 0.125 Min (pF) 0 Max (pF) 4 When using an external reference clock instead of a crystal on the XTAL/REF pin, the input load capacitors may be completely bypassed. This allows for the input frequency to be up to 200 MHz. When using an external reference clock, the XOUT pin must be left floating, XTAL must be programmed to the default value of “00h”, and the crystal drive strength bit, XDRV (0x06), must be set to the default value of “11h”. Switchover Modes The IDT5V49EE504 features redundant clock inputs which supports both Automatic and Manual switchover mode. These two modes are determined by the configuration bits, SM (0xBE through 0xC3). The primary clock source can be programmed, via the PRIMSRC bit, to be either XIN/REF or CLKIN. The other clock input will be considered as the secondary source. Note that the switchover modes are asynchronous. If the reference clocks are directly routed to OUTx with no phase relationship, short pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is XIN/REF. Switchover modes are not supported for crystal input configurations. Crystal Input (XIN/REF) The crystal used should be a fundamental mode quartz crystal; overtone crystals should not be used. When the XIN/REF pin is driven by a crystal, it is important to set the internal inverter oscillator drive strength and tuning/load capacitor values correctly to achieve the best clock performance. These values are programmable through I2C interface to allow for maximum compatibility with crystals from various manufacturers, processes, performances, and qualities. The internal load capacitors are true parallel-plate capacitors for ultra-linear performance. Parallel-plate capacitors were chosen to reduce the frequency shift that occurs when non-linear load capacitance interacts with load, bias, supply, and temperature changes. External non-linear crystal load capacitors should not be used for applications that are sensitive to absolute frequency requirements. The value of the internal load capacitors are determined by XTAL[4:0] bits. The load capacitance can be set with a resolution of 0.125 pF for a total crystal load ranging from 3.5 pF to 7.5 pF. Check with the crystal vendor's load capacitance specification for the exact setting to tune the internal load capacitor. The following equation governs how the total Manual Switchover Mode When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLKSEL pin is used to switch between the primary and secondary clock sources. As previously mentioned, the primary and secondary clock source setting is determined by the PRIMSRC bit. During the switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and frequency relationship between the primary and secondary clocks. Automatic Switchover Mode The redundant inputs are in automatic switchover mode. Automatic switchover mode has revertive functionality. The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary clock cycles. If both reference IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 6 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER clocks are at different frequencies, the device will always remain on the primary clock unless it is absent for two secondary clock cycles. The secondary clock must always run at a frequency less than or equal to the primary clock frequency. Q[6:0] 111 1111 PM 0 1 Output Divider Disabled /1 /2 /((Q[6:0] + 2) * 2) Reference Divider, Feedback Divider, and '0' and set NSSC[2:0], SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M value) accordingly. To disable spread spectrum generation, set TSSC = '0'. Where FIN is the reference frequency, M is the total feedback-divider value, D is the reference divider value, ODIV is the total output-divider value, and FOUT is the resulting output frequency. For PLL0, M = 2 * N + A + 1 (for A>0) M = 2 * N (for A = 0) For PLL1, PLL2 and PLL3, M=N PM and Q[6:0] are the bits used to program the 8-bit output-dividers for outputs OUT1-6. OUT0 does not have any output divide along its path. The 8-bit output-dividers will bypass or divide down the output banks' frequency with even integer values ranging from 2 to 256. There is the option to choose between disabling the output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider by using the PM bit. If the output is disabled, it will be driven High, Low or High Impedance, depending on OEM[1:0]. Each bank, except for OUT0, has a PM bit. When disabled, no clocks will appear at the output of the divider, but will remain powered on. The output divides selection table is shown below. TSSC[3:0] These bits are used to determine the number of phase/frequency detector cycles per spread spectrum cycle (ssc) steps. The modulation frequency can be calculated with the TSSC bits in conjunction with the NSSC bits. Valid TSSC integer values for the modulation frequency range from 5 to 14. Values of 0 - 4 and 15 should not be used. NSSC[2:0] These bits are used to determine the number of delta-encoded samples used for a single quadrant of the spread spectrum waveform. All four quadrants of the spread spectrum waveform are mirror images of each other. The modulation frequency is also calculated based on the NSSC bits in conjunction with the TSSC bits. Valid NSSC integer values range from 1 to 6. Values of 0 and 7 should not be used. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 7 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER SS_OFFSET[5:0] These bits are used to program the fractional offset with respect to the nominal M integer value. For center spread, the SS_OFFSET is set to '0' so that the spread spectrum waveform is centered about the nominal M (Mnom) value. For down spread, the SS_OFFSET > '0' such the spread spectrum waveform is centered about the (Mideal -1 +SS_Offset) value. The downspread percentage can be thought of in terms of center spread. For example, a downspread of -1% can also be considered as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63. if 1 < Amplitude < 2, then set X2 bit to '1'. Modulation frequency: FPFD = FIN / D (Eq. 6) FVCO = FPFD * MNOM (Eq. 7) FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8) Spread: Σ∆ = SD0 + SD1 + SD2 + … SD11 + the number of samples used depends on the NSSC value Σ∆< 63 - SS_OFFSET ±Spread% = (Σ∆ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9) ±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1) SD[3:0] These bits are used to shape the profile of the spread spectrum waveform. These are delta-encoded samples of the waveform. There are twelve sets of SD samples. The NSSC bits determine how many of these samples are used for the waveform. The sum of these delta-encoded samples (sigma delta- encoded samples) determine the amount of spread and should not exceed (63 - SS_OFFSET). The maximum spread is inversely proportional to the nominal M integer value. DITH This bit is used for dithering the sigma-delta-encoded samples. This will randomize the least-significant bit of the input to the spread spectrum modulator. Set the bit to '1' to enable dithering. X2 This bit will double the total value of the sigma-delta-encoded-samples which will increase the amplitude of the spread spectrum waveform by a factor of two. When X2 is '0', the amplitude remains nominal but if set to '1', the amplitude is increased by x2. The following equations govern how the spread spectrum is set: TSSC = TSSC[3:0] + 2 (Eq. 2) NSSC = NSSC[2:0] * 2 (Eq. 3) SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4) where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12. Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2 (Eq. 5) IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 8 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Profile: Waveform starts with SS_OFFSET, SS_OFFSET + SDJ, SS_OFFSET + SDJ+1, etc. Spread Spectrum Using Sinusoidal Profile to enhance the profile of the spread spectrum waveform. Tssc = 14 + 2 = 16 Nssc = 6 * 2 = 12 Nssc * Tssc = 192 Use Eq.10 to determine the value of the sigma-delta-encoded samples. ±2% = (Σ∆ * 100)/(64 * 48) Σ∆ = 61.4 Either round up or down to the nearest integer value. Therefore, we end up with 61 or 62 for sigma-delta-encoded samples. Since the sigma-delta-encoded samples must not exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within the limits. It is the discretion of the user to define the shape of the profile that is better suited for the intended application. Using Eq. 9 again, the actual spread for the sigma-delta-encoded samples of 56 and 57 are ±1.99% and ±2.02%, respectively. Use Eq.10 to determine if the X2 bit needs to be set; Example FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings. Since the spread is center, the SS_OFFSET can be set to '0'. Solve for the nominal M value; keep in mind that the nominal M should be chosen to maximize the VCO. Start with D = 1, using Eq.6 and Eq.7. MNOM = 1200MHz / 25MHz = 48 Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.8. Nssc * Tssc = 25MHz / (33KHz * 4) = 190 However, using Eq. 2 and Eq.3, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1 Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user. The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 47. Note that the IDT5V49EE504 should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The PLL loop bandwidth must be at least 10x the modulation frequency along with higher damping (larger ωuz) to prevent the spread spectrum from being filtered and reduce extraneous noise. Refer to the LOOP FILTER section for more detail on ωuz. The A[3:0] must be used for spread spectrum, even if the total multiplier value is an even integer. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 9 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Spread Spectrum Generation (PLL3) PLL3 support spread spectrum generation capability, which users have the option of turning on and off. Spread spectrum profile, frequency, and spread are fully programmable (within limits). The technique is different from that used in PLL0. The programmable spread spectrum generation parameters are SS_D3[7:0], SSVCO[15:0], SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the memory address range of 0x4C to 0x85 for PLL3. The spread spectrum generation on PLL3 can be enabled/disabled using the SSENB bit. To enable spread spectrum, set SSENB = '1'. Zero capacitor (Cz) = 196 pF + CZ* 217 pF Pole capacitor (Cp) = 15 pF Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA VCO gain (KVCO) = 900 MHz/V * 2π The following equations govern how the loop filter is set for PLL3: For Non-Spread Spectrum Operation: For Spread Enabled: Spread spectrum is configured using SS_D3(spread spectrum reference divide) Resistor(Rz) = (12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3])) kOhms (Eq. 12) * RZ[0] + 6*(1 – RZ[0]) For Spread Spectrum Operation: SS_D3 = FIN 4*F MOD (Eq. 10) Resistor(Rz) = (62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3])) kOhms (Eq. 13) * RZ[0] + 6*(1 – RZ[0]) and SSVCO (spread spectrum loop feedback counter). SSVCO = [0.5 * FVCO F MOD Zero capacitor (Cz) = 250 pF * ( 1 + SS/400) + 5] (Eq. 11) Pole capacitor (Cp) = 15 pF For Non-Spread Spectrum Operation: SS is the total Spread Spectrum amount (I.e. center spread +0.5% has a total spread of 1.0% and down spread -0.5% has a total spread of 0.5%.) 24 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14) Charge = pump (Ip) 3 + (5 * IP[3]) + (11 * IP[4]) For Spread Spectrum Operation: Loop Filter The loop filter for each PLL can be programmed to optimize the jitter performance. The low-pass frequency response of the PLL is the mechanism that dictates the jitter transfer characteristics. The loop bandwidth can be extracted from the jitter transfer. A narrow loop bandwidth is good for jitter attenuation while a wide loop bandwidth is best for low-jitter frequency generation. The specific loop filter components that can be programmed are the resistor via the RZ[3:0] bits, zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and the charge pump current via the IP[2:0] bits (for PLL0, PLL1 and PLL2) or IP[3:0] (for PLL3). The following equations govern how the loop filter is set for PLL0 - PLL2: Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0 kOhm 12 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14) Charge = pump (Ip) 27 + (5 * IP[3]) + (11 * IP[4]) VCO gain (KVCO) = 900 MHz/V * 2π IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 10 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER PLL Loop Bandwidth: Charge pump gain (Kφ⎞) = Ip / 2π VCO gain (KVCO) = 900 MHz/V * 2π M = Total multiplier value (See the Reference Divider, Feedback Divider and Output Divider section for more detail) ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp)) Fc = ωc / 2π Note, the phase/frequency detector frequency (FPFD) is typically seven times the PLL closed-loop bandwidth (Fc) but too high of a ratio will reduce the phase margin thus compromising loop stability. To determine if the loop is stable, the phase margin (φm) needs to be calculated as follows. Phase Margin: ωz = 1 / (Rz * Cz) ωp = (Cz + Cp)/(Rz * Cz * Cp) φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)] To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 11 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER SEL[2:0] Function The IDT5V49EE504 can support up to six unique configurations. Users may pre-programmed all these configurations, and select the configurations using SEL[2:0] SEL2 0 0 0 0 1 1 1 1 pins. Alternatively, users may use I2C interface to configure these registers on-the-fly. SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Select CONFIG0 Select CONFIG1 Select CONFIG2 Select CONFIG3 Select CONFIG4 Select CONFIG5 Configuration Selections Reserved (Do not use) Reserved (Do not use) SD/OE Pin Function The polarity of the SD/OE signal pin can be programmed to be either active HIGH or LOW with the SP bit (0x02). When SP is “0” (default), the pin becomes active HIGH and when SP is “1”, the pin becomes active LOW. The SD/OE pin can be configured as either to shutdown the PLLs or to enable/disable the outputs. SP O E M ode1 S D /O E SH SD M ode2 I2C Programming The IDT5V49EE504 is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read. The frame formats are shown in the following illustration. 1 Assert to disable the outputs whose OE bits are set 2 Assert to shut down power, on the outputs and 3-level pins Configuration OUTx IO Standard Users can configure the individual output IO standard from a specified 1.8 to 3.3V power supplies. Each output can support 1.8 to 3.3V LVTTL. OUT0 can only be a 3.3V single-ended output. Framing Programming the Device I2C may be used to program the IDT5V49EE504. – Device (slave) address = 7'b1101010 IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 12 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Each frame starts with a “Start Condition” and ends with an “End Condition”. These are both generated by the Master device. MSB 1 1 0 1 0 1 0 R/W 7-bit slave address R/W 0 – Slave will be written by master 1 – Slave will be read by master ACK from Slave LSB The first byte transmitted by the Master is the Slave Address followed by the R/W bit. The Slave acknowledges by sending a “1” bit. First Byte Transmitted on I2C Bus External I2C Interface Condition KEY: From Master to Slave From Master to Slave, but can be omitted if followed by the correct sequence Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can generate a separate START condition, and address another Slave address without first generating a STOP condition. From Slave to Master SYMBOLS: ACK - Acknowledge (SDAT LOW) NACK – Not Acknowledge (SDAT HIGH) SR – Repeated Start Condition S – START Condition P – STOP Condition Progwrite S Address 7-bits R/W 0 ACK 1-bit Command Code 8-bits: xxxx xx00 ACK 1-bit Register 8-bits ACK 1-bit Data 8-bits ACK 1-bit P Progwrite Command Frame Writes can continue as long as a Stop condition is not sent and each byte will increment the register address. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 13 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Progread Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known “read” register address prior to a read operation by issuing the following command: S Address 7-bits R/W 0 ACK 1-bit Command Code 8-bits: xxxx xx00 ACK 1-bit Register 8-bits ACK 1-bit P Prior to Progread Command Set Register Address The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by the Progread command): S Address 7-bits R/W 1 ACK 1-bit ID Byte 8-bits ACK 1-bit Data_1 8-bits ACK 1-bit Data_2 8-bits ACK 1-bit Data_last NACK 8-bits 1-bit P Progread Command Frame Progsave S Address 7-bits R/W 0 ACK 1-bit Command Code 8-bits: xxxx xx01 ACK 1-bit P Note: PROGWRITE is for writing to the IDT5V49EE504 registers. PROGREAD is for reading the IDT5V49EE504 registers. PROGSAVE is for saving all the contents of the IDT5V49EE504 registers to the EEPROM. PROGRESTORE is for loading the entire EEPROM contents to the IDT5V49EE504 registers. Progrestore S Address 7-bits R/W 0 ACK 1-bit Command Code 8-bits: xxxx xx10 ACK 1-bit P EEPROM Interface The IDT5V49EE504 can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to the internal programming registers by issuing a restore instruction (ProgRestore). To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V49EE504 will not generate Acknowledge bits. The IDT5V49EE504 will acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted as busy by all other users of the bus. On power-up of the IDT5V49EE504, an automatic restore is performed to load the EEPROM contents into the internal programming registers. The IDT5V49EE504 will be ready to accept a programming instruction once it acknowledges its 7-bit I2C address. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 14 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER I2C Bus DC Characteristics Symbol VIH VIL VHYS IIN VOL Parameter Input HIGH Level Input LOW Level Hysteresis of Inputs Input Leakage Current Output LOW Voltage Conditions Min 0.7xVDD Typ Max 0.3xVDD Unit V V V µA V 0.05xVDD ±1.0 IOL = 3 mA 0.4 I2C Bus AC Characteristics for Standard Mode Symbol FSCLK tBUF tSU:START tHD:START tSU:DATA tHD:DATA tOVD CB tR tF tHIGH tLOW tSU:STOP Parameter Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, START Hold Time, START Setup Time, data input (SDA) Hold Time, data input (SDA) 1 Output data valid from clock Capacitive Load for Each Bus Line Rise Time, data and clock (SDAT, SCLK) Fall Time, data and clock (SDAT, SCLK) HIGH Time, clock (SCLK) LOW Time, clock (SCLK) Setup Time, STOP Min 0 4.7 4.7 4 250 0 Typ Max 100 Unit kHz µs µs µs ns µs 3.45 400 1000 300 4 4.7 4 µs pF ns ns µs µs µs Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the VIH(MIN) of the SCLK signal) to bridge the undefined region of the falling edge of SCLK. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 15 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER I2C Bus AC Characteristics for Fast Mode Symbol FSCLK tBUF tSU:START tHD:START tSU:DATA tHD:DATA tOVD CB tR tF tHIGH tLOW tSU:STOP Parameter Serial Clock Frequency (SCL) Bus free time between STOP and START Setup Time, START Hold Time, START Setup Time, data input (SDA) Hold Time, data input (SDA) Output data valid from clock Capacitive Load for Each Bus Line Rise Time, data and clock (SDA, SCL) Fall Time, data and clock (SDA, SCL) HIGH Time, clock (SCL) LOW Time, clock (SCL) Setup Time, STOP 1 Min 0 1.3 0.6 0.6 100 0 Typ Max 400 Unit kHz µs µs µs ns µs 0.9 400 20 + 0.1xCB 20 + 0.1xCB 0.6 1.3 0.6 300 300 µs pF ns ns µs µs µs Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 16 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V49EE504. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Symbol VDD VI VO TJ TSTG Input Voltage 1 Description Internal Power Supply Voltage Output Voltage (not to exceed 4.6 Junction Temperature Storage Temperature V)1 Min -0.5 -0.5 -0.5 -65 Max +4.6 +4.6 VDD+0.5 150 150 Unit V V V °C °C 1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed. Recommended Operation Conditions Symbol VDD VDDX AVDD VDDOX Parameter Power supply voltage for VDD pins supporting core and outputs Power supply voltage for crystal oscillator. Use filtered analog power supply if available. Analog power supply voltage. Use filtered analog power supply if available. 3.3V VDDO Range 2.5V VDDO Range for 2.5V LVTTL 1.8V VDDO Range for 1.8V LVTTL Min 3.135 3.135 3.135 3.0 2.25 1.7 -40 Typ 3.3 3.3 3.3 3.3 2.5 1.8 Max 3.465 3.465 3.465 3.6 2.75 1.9 +85 15 8 Unit V V V V V V °C pF pF MHz ms TA Operating temperature, ambient Maximum load capacitance (1.8V/2.5V LVTTL only) CLOAD_OUT Maximum load capacitance (3.3V LVTTL only) FIN tPU External reference crystal External reference clock CLKIN Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 8 1 0.05 50 200 5 IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 17 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Capacitance (TA = +25 °C) Symbol CIN Pull-down Resistor XTAL_FREQ XTAL_MIN XTAL_MAX XTAL_VPP Parameter Input Capacitance (CLKIN, CLKSEL, SD/OE, SDA, SCL, SEL[2:0]) CLKIN, CLKSEL, SD/OE, SEL[2:0] Min Typ 3 180 Max 7 Unit pF kΩ Crystal Specifications Crystal frequency Minimum crystal load capacitance Maximum crystal load capacitance Voltage swing (peak-to-peak, nominal) 1.5 2.3 8 3.5 35.5 3.2 50 MHz pF pF V DC Electrical Characteristics for 3.3-V LVTTL 1 Symbol VOH VOL VIH VIL IOZDD Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Test Conditions Min 2.4 2 Typ Max VDD 0.4 0.8 10 Unit V V V V µA Output Leakage Current 3-state outputs. VO = VDD or GND, VDD = 3.6V Note 1: See “Recommended Operating Conditions” table. Power Supply Characteristics for PLLs and Outputs Total Supply Current Vs PLL Frequency 80 Supply current Vs Output Frequency 70 Supply Current(mA ) 60 50 40 30 20 10 70 Total Supply Current(mA) 60 50 40 30 20 10 0 0 200 400 600 PLL Frequency(MHz) PLL0 ON IDD(mA) PLL0+PLL1+PLL2 on IDD(mA) PLL0+PLL1 On IDD(mA) All Plls ON IDD(mA) 800 1000 1200 0 0 25 50 No outputs 4 outputs on 75 100 125 2 outputs on 150 175 3 outputs on 200 Output Frequency(MHz) REF output on 5 outputs on IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 18 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER AC Timing Electrical Characteristics (Spread Spectrum Generation = OFF) Symbol fIN 1 Parameter Input Frequency Output Frequency VCO Frequency PFD Frequency Loop Bandwidth Input Duty Cycle Output Duty Cycle Test Conditions Input frequency limit (CLKIN) Input frequency limit (XIN/REF) Min. 1 8 0.001 100 0.5 1 0.01 40 45 40 Typ. Max. 200 100 200 1200 100 10 60 55 60 Units MHz MHz MHz MHz MHz MHz % % % V/ns 1 / t1 fVCO fPFD fBW t2 t3 Single ended clock output limit VCO operating frequency range PFD operating frequency range Based on loop filter resistor and capacitor values Duty Cycle for input Measured at VDD/2, all outputs except Reference output Measured at VDD/2, Reference output t4 2 Slew Rate, SLEW[1:0] = 00 Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to 80% of VDD (Output Load = 15 pF) Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to 80% of VDD (Output Load = 15 pF) Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to 80% of VDD (Output Load = 15 pF) Single-ended 3.3V LVCMOS output clock rise and fall time, 20% to 80% of VDD (Output Load = 15 pF) Peak-to-peak period jitter, 1PLL, multiple output frequencies switching Peak-to-peak period jitter, all 4 PLLs on3 3.5 Slew Rate, SLEW[1:0] = 01 2.75 Slew Rate, SLEW[1:0] = 10 2 Slew Rate, SLEW[1:0] = 11 1.25 t5 Clock Jitter 80 200 100 270 75 ps ps ps ms ms t6 t7 4 t8 5 Output Skew Lock Time Lock Time Skew between output to output on the same bank PLL lock time from power-up PLL lock time from shutdown mode 10 20 2 1.Practical lower frequency is determined by loop filter settings. 2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher. 3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz. 4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time. 5.Actual PLL lock time depends on the loop configuration. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 19 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Spread Spectrum Generation Specifications Symbol fIN 1 fMOD fSPREAD Parameter Input Frequency Input Frequency Limit Mod Frequency Spread Value Modulation Frequency Description Min 1 Typ 33 Max 400 Unit MHz kHz %fOUT Amount of Spread Value (programmable) - Down Spread Amount of Spread Value (programmable) - Center Spread Programmable Programmable 1.Practical lower frequency is determined by loop filter settings. Test Circuits and Conditions VDDOx VDD 0.1µF 0.1µF OUTx CLKOUT CL=5pF GND Test Circuits for DC Outputs IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 20 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Programming Registers Table Default Register Addr Hex Value 0x00 0x01 0x02 00 00 02 SP OE6 Reserved OE5 OE4 OE3 OE2 Bit # 7 6 5 4 Reserved SEL[2:0] OE1 OE0 3 2 1 0 HW/SW Description Hardware/Software Mode control HW/SW - 0=HW, 1=SW SEL[2:0] - selects configuration in SW mode OEx=Output Power Suspend function for OUTx (‘1’=OUTx will be suspended on SD/OE pin. Disable mode is defined by OEMx bits), ‘0’=outputs enabled and no association with OE pin (default). OS*[6:0] - output suspend, active low. Overwrites OE setting. 0x03 0x04 02 0F Reserved SH Reserved OS*[6:0] PLLS*[3:0] PLLS*[3:0] - PLL Suspend, active low SH - shutdown/OE configuration XTCLKSEL - crystal/clock select. 0=Crytal, 1=ICLK XTAL[4:0] - crystal cap 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 04 00 00 00 00 10 10 10 10 10 10 00 00 00 00 00 00 01 01 01 01 01 01 00 00 00 00 00 00 10 10 10 10 10 10 CZ1_CFG4 CZ1_CFG5 CZ1_CFG0 CZ1_CFG1 CZ1_CFG2 CZ1_CFG3 CZ0_CFG4 CZ0_CFG5 CZ0_CFG0 CZ0_CFG1 CZ0_CFG2 CZ0_CFG3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved XTCLKSEL Reserved Reserved Reserved Reserved Reserved IP0[2:0]_CFG4 IP0[2:0]_CFG5 IP0[2:0]_CFG0 IP0[2:0]_CFG1 IP0[2:0]_CFG2 IP0[2:0]_CFG3 D0[6:0]_CFG0 D0[6:0]_CFG1 D0[6:0]_CFG2 D0[6:0]_CFG3 D0[6:0]_CFG4 D0[6:0]_CFG5 N0[7:0]_CFG4 N0[7:0]_CFG5 N0[7:0]_CFG0 N0[7:0]_CFG1 N0[7:0]_CFG2 N0[7:0]_CFG3 A0[3:0]_CFG0 A0[3:0]_CFG1 A0[3:0]_CFG2 A0[3:0]_CFG3 A0[3:0]_CFG4 A0[3:0]_CFG5 IP1[2:0]_CFG4 IP1[2:0]_CFG5 IP1[2:0]_CFG0 IP1[2:0]_CFG1 IP1[2:0]_CFG2 IP1[2:0]_CFG3 XTAL[4:0] RZ0[3:0]_CFG4 RZ0[3:0]_CFG5 RZ0[3:0]_CFG0 RZ0[3:0]_CFG1 RZ0[3:0]_CFG2 RZ0[3:0]_CFG3 PLL0 loop parameter PLL0 input divider and input sel D0[6:0] - 127 step Ref Div D0 = 0 means power down. N - Feedback Divider 2 - 4095 (values of “0” and “1” are not allowed) Total feedback with A, using provided calculation N0[11:8]_CFG0 N0[11:8]_CFG1 N0[11:8]_CFG2 N0[11:8]_CFG3 N0[11:8]_CFG4 N0[11:8]_CFG5 RZ1[3:0]_CFG4 RZ1[3:0]_CFG5 RZ1[3:0]_CFG0 RZ1[3:0]_CFG1 RZ1[3:0]_CFG2 RZ1[3:0]_CFG3 PLL1 Loop Parameter IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 21 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Default Register Addr Hex Value 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 00 00 00 00 00 00 01 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 80 80 80 80 80 80 00 00 00 00 Bit # 7 Reserved Reserved Reserved Reserved Reserved Reserved 6 5 4 3 D1[6:0]_CFG0 D1[6:0]_CFG1 D1[6:0]_CFG2 D1[6:0]_CFG3 D1[6:0]_CFG4 D1[6:0]_CFG5 N1[7:0]_CFG4 N1[7:0]_CFG5 N1[7:0]_CFG0 N1[7:0]_CFG1 N1[7:0]_CFG2 N1[7:0]_CFG3 2 1 0 Description PLL1 input divider and input sel D1[6:0] - 127 step Ref Div D1 = 0 means power down. N - Feedback Divider 2 - 4095 (value of “0” is not allowed) Total feedback with A, using provided calculation N3[11:8]_CFG0 N3[11:8]_CFG1 N3[11:8]_CFG2 N3[11:8]_CFG3 N3[11:8]_CFG4 N3[11:8]_CFG5 CZ2_CFG4 CZ2_CFG5 CZ2_CFG0 CZ2_CFG1 CZ2_CFG2 CZ2_CFG3 Reserved Reserved Reserved Reserved Reserved Reserved IP2[2:0]_CFG4 IP2[2:0]_CFG5 IP2[2:0]_CFG0 IP2[2:0]_CFG1 IP2[2:0]_CFG2 IP2[2:0]_CFG3 D2[6:0]_CFG0 D2[6:0]_CFG1 D2[6:0]_CFG2 D2[6:0]_CFG3 D2[6:0]_CFG4 D2[6:0]_CFG5 N2[7:0]_CFG4 N2[7:0]_CFG5 N2[7:0]_CFG0 N2[7:0]_CFG1 N2[7:0]_CFG2 N2[7:0]_CFG3 SSENB_CFG0 SSENB_CFG1 SSENB_CFG2 SSENB_CFG3 SSENB_CFG4 SSENB_CFG5 0 0 0 0 0 0 0 0 0 0 0 0 IP3[4]_CFG0 IP3[4]_CFG1 IP3[4]_CFG2 IP3[4]_CFG3 IP3[4]_CFG4 IP3[4]_CFG5 Reserved Reserved Reserved Reserved N1[11:8]_CFG0 N1[11:8]_CFG1 N1[11:8]_CFG2 N1[11:8]_CFG3 N1[11:8]_CFG4 N1[11:8]_CFG5 RZ2[3:0]_CFG4 RZ2[3:0]_CFG5 RZ2[3:0]_CFG0 RZ2[3:0]_CFG1 RZ2[3:0]_CFG2 RZ2[3:0]_CFG3 PLL3 Feedback Divider PLL2 Loop Parameter PLL2 Reference Divide and Input Select D2[6:0] - 127 step Ref Div D2 = 0 means power down. N2[7:0] - PLL2 Feedback Divider 2 - 4095 (value of “0” is not allowed). (See Addr 0x4C:0x51 for N2[15:8]) N2[11:8]_CFG0 N2[11:8]_CFG1 N2[11:8]_CFG2 N2[11:8]_CFG3 N2[11:8]_CFG4 N2[11:8]_CFG5 N2[11:8] - PLL2 Feedback Divide PLL3 Spread Spectrum SSENB - Spread Spectrum Enable SSENB = 1 means ON IP3[4:0] - PLL3 Charge Pump Current. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 22 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Default Register Addr Hex Value 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 00 00 00 00 00 00 03 03 03 03 03 03 0C 0C 0C 0C 0C 0C 00 00 00 00 00 00 00 00 00 00 00 00 01 03 Bit # 7 6 IP3[3:0]_CFG4 IP3[3:0]_CFG5 IP3[3:0]_CFG0 IP3[3:0]_CFG1 IP3[3:0]_CFG2 IP3[3:0]_CFG3 Reserved Reserved Reserved Reserved Reserved Reserved D3[6:0]_CFG0 D3[6:0]_CFG1 D3[6:0]_CFG2 D3[6:0]_CFG3 D3[6:0]_CFG4 D3[6:0]_CFG5 N3[7:0]_CFG4 N3[7:0]_CFG5 N3[7:0]_CFG0 N3[7:0]_CFG1 N3[7:0]_CFG2 N3[7:0]_CFG3 SSVCO[7:0]_CFG0 SSVCO[7:0]_CFG1 SSVCO[7:0]_CFG2 SSVCO[7:0]_CFG3 SSVCO[7:0]_CFG4 SSVCO[7:0]_CFG5 SS_D3[7:0]_CFG4 SS_D3[7:0]_CFG5 SS_D3[7:0]_CFG0 SS_D3[7:0]_CFG1 SS_D3[7:0]_CFG2 SS_D3[7:0]_CFG3 Reserved OEM0[1:0] SLEW0[1:0] INV0 Reserved S1 S3 5 4 3 2 1 RZ3[3:0]_CFG4 RZ3[3:0]_CFG5 RZ3[3:0]_CFG0 RZ3[3:0]_CFG1 RZ3[3:0]_CFG2 RZ3[3:0]_CFG3 0 Description PLL3 Loop Parameter PLL3 Reference Divide and input sel D3[6:0] - 127 step Ref Div D3 = 0 means power down. N - Feedback Divider 12 - 4095 (values of “0” through “11” are not allowed) SSVCO[7:0] - PLL3 Spread Spectrum Loop Feedback Counter See Addr 0x80:0x85 for SSVCO[15:8] SS_D[7:0] - PLL3 Spread Spectrum Reference Divide Reserved Output Controls S1=1 - OUT1/OUT2 are from DIV1/DIV2 respectively S1=0 - Both from DIV2 S3 =1 - OUT3/OUT6 are from DIV3/DIV6 S3=0 - Both from DIV6 SLEW - see AC Timing OEM#–output enable mode x0 - tristated 01 - park low 11 - park high OEM0 controls OUT0 only Output Controls INV1 [CLK1, CLK2] [0] - normal [1] - invert clock OEM1 controls OUT1/OUT2 OEM3 controls OUT3 and OUT6 0x76 00 OEM1[1:0] SLEW1[1:0] INV1[1:0] Reserved 0x77 0x78 0x79 0x7A 0x7B 0x7C 00 00 00 00 00 00 Reserved OEM3[1:0] SLEW2[1:0] SLEW3[1:0] Reserved Reserved SLEW6[1:0] Reserved Reserved INV3[1:0] Reserved Reserved Reserved IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 23 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Default Register Addr Hex Value 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 00 00 00 00 00 00 00 00 00 00 00 FF FF FF FF FF FF 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F Bit # 7 6 5 4 Reserved Reserved Reserved SSVCO[15:8]_CFG0 SSVCO[15:8]_CFG1 SSVCO[15:8]_CFG2 SSVCO[15:8]_CFG3 SSVCO[15:8]_CFG4 SSVCO[15:8]_CFG5 Reserved Reserved PM1_CFG0 PM1_CFG1 PM1_CFG2 PM1_CFG3 PM1_CFG4 PM1_CFG5 PM2_CFG4 PM2_CFG5 PM2_CFG0 PM2_CFG1 PM2_CFG2 PM2_CFG3 PM3_CFG0 PM3_CFG1 PM3_CFG2 PM3_CFG3 PM3_CFG4 PM3_CFG5 PM4_CFG4 PM4_CFG5 PM4_CFG0 PM4_CFG1 PM4_CFG2 PM4_CFG3 PM5_CFG0 PM5_CFG1 PM5_CFG2 PM5_CFG3 PM5_CFG4 PM5_CFG5 PM6_CFG4 PM6_CFG5 PM6_CFG0 PM6_CFG1 PM6_CFG2 PM6_CFG3 Q1[6:0]_CFG0 Q1[6:0]_CFG1 Q1[6:0]_CFG2 Q1[6:0]_CFG3 Q1[6:0]_CFG4 Q1[6:0]_CFG5 Q2[6:0]_CFG4 Q2[6:0]_CFG5 Q2[6:0]_CFG0 Q2[6:0]_CFG1 Q2[6:0]_CFG2 Q2[6:0]_CFG3 Q3[6:0]_CFG0 Q3[6:0]_CFG1 Q3[6:0]_CFG2 Q3[6:0]_CFG3 Q3[6:0]_CFG4 Q3[6:0]_CFG5 Q4[6:0]_CFG4 Q4[6:0]_CFG5 Q4[6:0]_CFG0 Q4[6:0]_CFG1 Q4[6:0]_CFG2 Q4[6:0]_CFG3 Q5[6:0]_CFG0 Q5[6:0]_CFG1 Q5[6:0]_CFG2 Q5[6:0]_CFG3 Q5[6:0]_CFG4 Q5[6:0]_CFG5 Q6[6:0]_CFG4 Q6[6:0]_CFG5 Q6[6:0]_CFG0 Q6[6:0]_CFG1 Q6[6:0]_CFG2 Q6[6:0]_CFG3 3 2 1 0 Description PLL3 Spread Spectrum Feedback Counter Reserved Reserved Output Divides for Q111111, PM=0 - Divide by 2 PM=1, (Q+2)*2 for Q=1111111 PM=0, disable the output divider PM=1, bypass the output divide, (divide by 1) IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 24 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Default Register Addr Hex Value 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 00 00 00 00 00 00 00 00 00 00 00 00 11 11 11 11 11 11 AE AE Bit # 7 6 5 4 3 2 1 0 Description PLL0 Spread Spectrum Control TSSC[3:0]_CFG0 TSSC[3:0]_CFG1 TSSC[3:0]_CFG2 TSSC[3:0]_CFG3 TSSC[3:0]_CFG4 TSSC[3:0]_CFG5 DITH_CFG4 DITH_CFG5 DITH_CFG0 DITH_CFG1 DITH_CFG2 DITH_CFG3 X2_CFG4 X2_CFG5 X2_CFG0 X2_CFG1 X2_CFG2 X2_CFG3 SD1[3:0]_CFG0 SD1[3:0]_CFG1 SD1[3:0]_CFG2 SD1[3:0]_CFG3 SD1[3:0]_CFG4 SD1[3:0]_CFG5 SRC1[1:0]_CFG4 SRC1[1:0]_CFG5 SRC0[1:0]_CFG4 SRC0[1:0]_CFG5 PDPL3_CFG4 PDPL3_CFG5 NSSC[3:0]_CFG0 NSSC[3:0]_CFG1 NSSC[3:0]_CFG2 NSSC[3:0]_CFG3 NSSC[3:0]_CFG4 NSSC[3:0]_CFG5 SSOFFSET[5:0]_CFG4 SSOFFSET[5:0]_CFG5 SSOFFSET[5:0]_CFG0 SSOFFSET[5:0]_CFG1 SSOFFSET[5:0]_CFG2 SSOFFSET[5:0]_CFG3 SD0[3:0]_CFG0 SD0[3:0]_CFG1 SD0[3:0]_CFG2 SD0[3:0]_CFG3 SD0[3:0]_CFG4 SD0[3:0]_CFG5 SM[1:0]_CFG4 SM[1:0]_CFG5 PRIMSRC_CFG4 Output Divide Source Selection PRIMSRC_CFG5 PRIMSRC - primary source - crystal or ICLOCK 0 = crystal/REFIN 1 = CLKIN 0xC0 AE SRC1[1:0]_CFG0 SRC0[1:0]_CFG0 PDPL3_CFG0 SM[1:0]_CFG0 PRIMSRC_CFG0 SM = switch mode 0x = manual 10 = reserved 11 = auto-revertive 0xC1 AE SRC1[1:0]_CFG1 SRC0[1:0]_CFG1 PDPL3_CFG1 SM[1:0]_CFG1 PRIMSRC_CFG1 PDPL3 - PLL3 shutdown 0 = normal 1 = shut down 0xC2 AE SRC1[1:0]_CFG2 SRC0[1:0]_CFG2 PDPL3_CFG2 SM[1:0]_CFG2 PRIMSRC_CFG2 SRC = MUX control bit prior to DIV# SRC0[1:0] 00 - DIV1 01 - DIV3 10 - Reference input 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF AE 24 24 24 24 24 24 49 49 49 49 49 49 SRC1[1:0]_CFG3 SRC4[0]_CFG0 SRC4[0]_CFG1 SRC4[0]_CFG2 SRC4[0]_CFG3 SRC4[0]_CFG4 SRC4[0]_CFG5 SRC0[1:0]_CFG3 SRC3[2:0]_CFG0 SRC3[2:0]_CFG1 SRC3[2:0]_CFG2 SRC3[2:0]_CFG3 SRC3[2:0]_CFG4 SRC3[2:0]_CFG5 PDPL3_CFG3 SM[1:0]_CFG3 PRIMSRC_CFG3 SRC1[2]_CFG0 SRC1/SRC2/SRC3..SRC5 SRC1[2]_CFG1 000 - DIV1 SRC1[2]_CFG2 010 - Reference input SRC1[2]_CFG3 011 - Reserved SRC2[2:0]_CFG0 SRC2[2:0]_CFG1 SRC2[2:0]_CFG2 SRC2[2:0]_CFG3 SRC2[2:0]_CFG4 SRC2[2:0]_CFG5 SRC5[2:0]_CFG4 SRC5[2:0]_CFG5 SRC5[2:0]_CFG0 SRC5[2:0]_CFG1 SRC5[2:0]_CFG2 SRC5[2:0]_CFG3 001 - DIV3 100 - PLL0 101 - PLL1 SRC1[2]_CFG5 110 - PLL2 111 - PLL3 SRC1[2]_CFG4 SRC4[2:1]_CFG4 SRC4[2:1]_CFG5 SRC4[2:1]_CFG0 SRC4[2:1]_CFG1 SRC4[2:1]_CFG2 SRC4[2:1]_CFG3 SRC6[2:0]_CFG4 SRC6[2:0]_CFG5 SRC6[2:0]_CFG0 SRC6[2:0]_CFG1 SRC6[2:0]_CFG2 SRC6[2:0]_CFG3 SRC6 000 - Reserved 001 - Reserved 010 - Reference input 011 - Reserved 100 - Reserved 101 - PLL1 110 - Reserved 111 - Reserved Quiet MUX Default Configuration: OUT1 = Reference Clock output, all other outputs turned off. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 25 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Marking Diagram 4504LI #YYWW$ Notes: 1. “#” is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “$” is the assembly mark code. 4. “I” at the end of part number indicates industrial temperature range. 5. Bottom marking: country of origin if not USA. Thermal Characteristics for 24QFN Parameter Thermal Resistance Junction to Ambient Symbol θJA θJA θJA θJC Conditions Still air 1 m/s air flow 2.5 m/s air flow Min. Typ. 47.6 42.4 39.9 60.7 Max. Units ° C/W ° C/W ° C/W ° C/W Thermal Resistance Junction to Case IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 26 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Package Outline and Package Dimensions (24-pin 4mm x 4mm QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area N 1 2 A1 A3 (ND-1)x e (Ref) L N 1 2 Sawn Singulation Top View A E2 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE-1)x e (Ref) E E2 2 b e D2 2 D2 D (Ref) ND & NE Odd Thermal Base 0.08 C Symbol Min Millimeters Max C A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 24 6 6 4.00 x 4.00 2.3 2.55 2.3 2.55 0.30 0.50 Ordering Information Part / Order Number 5V49EE504NLGI 5V49EE504NLGI8 Marking See Page 26 See Page 26 Shipping Packaging Tubes Tape and Reel Package 24-pin QFN 24-pin QFN Temperature -40 to +85° C -40 to +85° C “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 27 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Revision History Rev. A B C D E F Originator R.Willner R.Willner R.Willner R.Willner R.Willner R.Willner Date 4/27/09 5/04/09 6/04/09 06/10/09 10/06/09 02/23/10 Description of Change Advance Information. Identified VDDX (crystal oscillator power) and AVDD (analog power) on device. Add default configurations, pull-down resistor values on input pins. Released Datasheet from Advanced Information. Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF in “Programming Registers” table. Changed IP3[3:0] to IP3[4:0}; updated “Programming Registers Table”. Updated Recommended Operation Conditions to inlcude Vddx and AVdd parameters. IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR 28 IDT5V49EE504 REV F 022310 IDT5V49EE504 EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA