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IDT5V926APGGI

IDT5V926APGGI

  • 厂商:

    IDT

  • 封装:

  • 描述:

    IDT5V926APGGI - Single Output Clock Generator - Integrated Device Technology

  • 详情介绍
  • 数据手册
  • 价格&库存
IDT5V926APGGI 数据手册
Single Output Clock Generator IDT5V926A DATA SHEET FEATURES: • 3V to 3.6V operating voltage • 48MHz to 160MHz output frequency range • Input from fundamental crystal oscillator or external source • Internal PLL feedback (loading the feedback output relative to the other outputs, will adjust the propagation delay between REF inputs and outputs) • Select inputs (S[1:0]) for FB divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) • Low jitter • PLL bypass for testing and power-down control (S1 = H, S0 = H, powers part down 125MHz QREF Output/Duty Cycle VT = VDDQ/2 FOUT = 106.25MHz tJ fOUT Cycle - Cycle Jitter FOUT = 125MHz FOUT = 155.52MHz Output Frequency INPUT TIMING REQUIREMENTS Symbol tR, tF tPWC DH fOSC fIN NOTES: 1. Where pulse width implied by DH is less than the tPWC limit, tPWC limit applies. 2. When using a clock input. Description(1) Maximum input rise and fall time, 0.8V to 2V(2) Input clock pulse, HIGH or LOW(2) Input duty cycle(2) XTAL oscillator frequency Input frequency(2) Min. — 2 10 10 48/N Max. 10 — 90 40 160/N Unit ns/V ns % MHz MHz DT5V926A REVISION A JUNE 11, 2009 4 ©2009 Integrated Device Technology, Inc. IDT5V926A Data Sheet SINGLE OUTPUT CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V±0.15V VDD, VDDQ SCOPE QOUT LVCMOS GND t cycle n ➤ t jit(cc) = |t cycle n – t cycle n+1| 1000 Cycles -1.65V±0.15V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER 2V 0.8V tR 2V 0.8V tF QREF, QOUT t PW t PERIOD QREF, QOUT odc = t PW t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DT5V926A REVISION A JUNE 11, 2009 5 ©2009 Integrated Device Technology, Inc. ➤ V DD ➤ Qx t cycle n+1 ➤ 2 x 100% IDT5V926A SINGLE OUTPUT CLOCK GENERATOR PRELIMINARY ORDERING INFORMATION IDT XXXX Device Type X Package X Process I PG PGG 5V926A -40°C to +85C° (Industrial) Thin Shrink Small Outline Package TSSOP - Green Single Output Clock Generator Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
IDT5V926APGGI
1. 物料型号:IDT5V926A,这是一个单一输出时钟生成器。

2. 器件简介: - IDT5V926A是一个低成本、低偏差、低抖动、高性能的时钟乘法器,可以从较低频率的晶体振荡器或外部时钟输入提供参考时钟。 - 特别设计用于与千兆以太网和快速以太网应用接口,通过提供25MHz输入的125MHz时钟。 - 可以编程提供48MHz至160MHz的输出频率,输入频率范围为6MHz至80MHz。

3. 引脚分配: - S[1:0]:选择分频模式的三个级别分频模式选择引脚。悬空至MID。 - OE:输出使能,当高时输出Qout和OREF处于高阻态。将OE设为低电平时,内部上拉正常工作。 - REFE:OREF使能输入,当高时OREF停止。设置REFE为低时,OREF被使能。 - X1/REF:晶体振荡器输入或时钟输入。 - X2:晶体振荡器输出。对于时钟输入,无需连接。 - QOUT:输出N'REF频率的输出。 - QREF:输出REF频率的输出。 - VDDQ:设备输出的电源供应。连接至PCB上的VDD。 - VDD:设备核心和输入的电源供应。连接至PCB上的VDD。 - GND:地线供应。

4. 参数特性: - 工作电压:3V至3.6V。 - 输出频率范围:48MHz至160MHz。 - 输入频率范围:6MHz至80MHz。 - 内部PLL反馈。 - 低抖动。 - PLL旁路,用于测试和电源关闭控制。

5. 功能详解: - IDT5V926A包含内部RC滤波器,提供优秀的抖动特性,并消除了外部组件的需求。 - 当使用可选的晶体输入时,设备接受10 - 40MHz的基本模式晶体,最大等效串联电阻为50Ω。

6. 应用信息: - 千兆以太网、路由器、网络交换机、SAN、仪器、光纤通道。

7. 封装信息: - 可用TSSOP封装。
IDT5V926APGGI 价格&库存

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