IDT65ALVCH16823PA

IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package IDT74ALVCH16823 FEATURES: DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH16823 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16823 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM 1 OE 2 2 OE 27 1 CLR 1 2 CLR 28 1 CLKEN 55 CE R 3 2 CLKEN 30 CE R 15 1 CLK 1D 1 56 54 C1 D1 1Q 1 2 CLK 2D 1 29 42 C1 D1 2Q 1 TO 8 OTHER CHANNELS TO 8 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1 © 2004 Integrated Device Technology, Inc. JANUARY 2004 DSC-4237/2 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 1CLR 1OE 1Q1 ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND –0.5 to +4.6 –0.5 to VCC+0.5 –65 to +150 –50 to +50 ±50 –50 ±100 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1CLK 1CLKEN 1D1 Unit V V °C mA mA mA mA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VTERM(3) TSTG IOUT IIK IOK ICC ISS GND 1Q2 1Q3 GND 1D2 1D3 VCC 1Q4 1Q5 1Q6 VCC 1D4 1D5 1D6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 1D7 1D8 1D9 2D1 2D2 2D3 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF GND 2Q4 2Q5 2Q6 GND 2D4 2D5 2D6 VCC 2Q7 2Q8 VCC 2D7 2D8 NOTE: 1. As applicable to the device type. GND 2Q9 2OE 2CLR GND 2D9 2CLKEN 2CLK FUNCTION TABLE (EACH 9-BIT FLIP-FLOP)(1) Inputs xOE L L L L L H xCLR L H H H H X xCLKEN X L L L H X xCLK X ↑ ↑ L X X xDx X H L X X X Output xQx L H L Q0(2) Q0(2) Z TSSOP TOP VIEW PIN DESCRIPTION Pin Names xDx xCLK xCLKEN xQx xOE xCLR Data Inputs(1) Clock Input Clock Enable Inputs 3-State Outputs 3-State Output Enable Inputs Clear Inputs Description NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ∆ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = –18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 — — — — — — — — — Typ.(1) — — — — — — — — –0.7 100 0.1 Max. — — 0.7 0.8 ±5 ±5 ±10 ±10 –1.2 — 40 V mV µA µA µA µA V Unit V Quiescent Power Supply Current Variation — — 750 µA NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V Min. – 75 75 – 45 45 — Typ.(2) — — — — — Max. — — — — ±500 Unit µA µA µA 3 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = – 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = – 0.1mA IOH = – 6mA IOH = – 12mA Min. VCC – 0.2 2 1.7 2.2 2.4 2 — — — — — Max. — — — — — — 0.2 0.4 0.7 0.4 0.55 V Unit V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C VCC = 2.5V ± 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 27 16 VCC = 3.3V ± 0.3V Typical 30 18 Unit pF 4 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW tW tSU tSU tSU tSU tH tH tH tSK(O) Propagation Delay xCLK to xQx Propagation Delay xCLR to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Pulse Duration, xCLR LOW Pulse Duration, xCLK HIGH or LOW Set-up Time, xCLR inactive Set-up Time, data LOW before xCLK↑ Set-up Time, data HIGH before xCLK↑ Set-up Time, xCLKEN LOW before xCLK↑ Hold Time, data LOW after xCLK↑ Hold Time, data HIGH after xCLK↑ Hold Time, xCLKEN LOW after CLK↑ Output Skew(2) 3.3 3.3 0.7 1.4 1.1 1.8 0.4 0.7 0.2 — — — — — — — — — — — 3.3 3.3 0.7 1.6 1.1 1.9 0.5 0.1 0.3 — — — — — — — — — — — 3.3 3.3 0.8 1.3 1 1.5 0.5 0.8 0.4 — — — — — — — — — — 500 ns ns ns ns ns ns ns ns ns ps 1.1 5.4 — 4.7 1.3 4.5 ns 1 6 — 5.7 1 4.8 ns 1 5.4 — 5.2 1.2 4.6 ns Parameter Min. 150 1 Max. — 5.8 VCC = 2.7V Min. 150 — Max. — 5.2 VCC = 3.3V ± 0.3V Min. 150 1 Max. — 4.5 Unit MHz ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V±0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link Propagation Delay VCC 500Ω Pulse Generator (1, 2) VLOAD Open GND CONTROL INPUT ENABLE DISABLE VIN D.U.T. RT VOUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V ALVC Link 500Ω CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Enable and Disable Times SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tSU tH tREM tSU tH VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link INPUT tPLH1 tPHL1 VIH VT 0V VOH VT VOL VOH VT VOL Set-up, Hold, and Release Times OUTPUT 1 LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT tSK (x) tSK (x) OUTPUT 2 tPLH2 tPHL2 VT ALVC Link Pulse Width ALVC Link tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ALVC X IDT XX Bus-Hold Temp. Range XXX Family XX XXX Device Type Package PA 823 16 H 74 Thin Shrink Small Outline Package 18-Bit Bus-Interface Flip-Flop with 3-State Outputs Double-Density, ±24mA Bus-Hold –40°C to +85°C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 7