IDT6P30006A

DATASHEET CLOCK DISTRIBUTION CIRCUIT Description The IDT6P30006A is a low-power, eight output clock distribution circuit. The device takes a TCXO or LVCMOS input and generates eight high-quality outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. The IDT6P30006A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space. IDT6P30006A Features • • • • • Packaged in 24-pin QFN LVCMOS or TCXO sine wave input +1.8 V operating voltage Glitch-free input switching Eight buffered square wave outputs at 1.8 V LVCMOS levels • Individual output enables controlled via I2C or OEx • Pb free, RoHS compliant package • Industrial temperature range (-40°C to +85°C) Block Diagram VDD 1.8 V 4 OE1 OUT1 SCLK SDATA OE2 OUT2 OE3 OUT3 OE4 OUT4 LVCMOS_INB OUT5 OUT6 TCXO_INA ±100mVpp MUX OUT7 OUT8 3 SEL GND IDT™ CLOCK DISTRIBUTION CIRCUIT 1 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Pin Assignment TCXO_INA GND OUT1 OUT2 SEL Pin Configuration Table SEL VDD Primary Input LVCMOS_INB TCXO_INA VDD 0 1 OUT3 OUT4 GND VDD LVCMOS_INB OE4 OE1 SCLK SDATA SEL GND 1 19 OE Pin Configuration Table OEx 0 1 OUTx Disabled Enabled 7 13 OE3 OUT7 Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OE4 OE1 SCLK SDATA SEL GND OE2 OUT8 VDD OUT7 OUT6 OUT5 OE3 LVCMOS_INB VDD GND OUT8 24- pin QFN OUT6 Pin Type Input Input Input I/O Input Power Input Output Power Output Output Output Input Input Power Power OUT5 VDD OE2 Pin Description Output enable control for OUT4. Internal pull-up resistor. See table above. Output enable control for OUT1. Internal pull-up resistor. See table above. I2C clock input. I2C data input. Select pin for primary inputs. See table above. Internal pull-up resistor. Connect to ground. Output enable control for OUT2. Internal pull-up resistor. See table above. Buffered output. Outputs tri-state with weak pull-down when disabled. Connect to +1.8 V. Buffered output. Outputs tri-state with weak pull-down when disabled. Buffered output. Outputs tri-state with weak pull-down when disabled. Buffered output. Outputs tri-state with weak pull-down when disabled. Output enable control for OUT3. Internal pull-up resistor. See table above. Connect to 13 MHz LVCMOS clock input. See table above. Connect to +1.8 V. Connect to ground. IDT™ CLOCK DISTRIBUTION CIRCUIT 2 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Pin Number 17 18 Pin Name OUT4 OUT3 OUT2 OUT1 VDD GND TCXO_INA VDD Pin Type Output Output Output Output Power Power Input Power Pin Description Buffered output. Outputs tri-state with weak pull-down when disabled. Buffered output. Outputs tri-state with weak pull-down when disabled. Buffered output. Outputs tri-state with weak pull-down when disabled. Buffered output. Outputs tri-state with weak pull-down when disabled. Connect to +1.8 V. Connect to ground. Connect to 13 MHz TCXO input. Connect to +1.8 V. 19 20 21 22 23 24 IDT™ CLOCK DISTRIBUTION CIRCUIT 3 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS General I2C Serial Interface How to Write: • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address D2(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X - 1 (see Note 2) IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: • • • • • • • • • • • • • • Controller (host) sends a start bit Controller (host) sends the write address D2(H) IDT clock will acknowledge Controller (host) sends the beginning byte location =N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address D3(H) IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock sends Byte N + X - 1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) T WR starTbit WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte = N O O O Byte N + X - 1 ACK P stoP bit . X B Y T E ACK O O O ACK . ACK O O O N P X B Y T E Beginning Byte N O O O Byte N + X - 1 Data Byte Count = X RT RD Slave Address D2(H) Beginning Byte = N ACK IDT (Slave/Receiver) Controller (Host) T WR starTbit Slave Address D2(H) WRite ACK IDT (Slave/Receiver) Repeat starT ReaD ACK Slave Address D3(H) Not acknowledge stoP bit IDT™ CLOCK DISTRIBUTION CIRCUIT 4 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS I2C Address The IDT6P30006A is a slave-only device that supports block read and block write protocol using a single 7 bit address and read/write bit. A block write (D2(H)) or block read (D3(H)) is made up of seven (7) bits and one (1) read/write bit. A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W# X In applications where the indexed block write and block read are used, the dummy byte (bit 11-18) functions as a register-offset (8 bits) pointer. Byte 0: Control Register Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved OE for clock output OE for clock output OE for clock output OE for clock output Type RW RW RW RW RW RW RW RW Power Up Condition Undefined Undefined Undefined Undefined 1 1 1 1 Output(s) Affected Not applicable Not applicable Not applicable Not applicable Notes Output_5 clock output Output_6 clock output Output_7 clock output Output_8 clock output 1=enabled 0=disabled 1=enabled 0=disabled 1=enabled 0=disabled 1=enabled 0=disabled IDT™ CLOCK DISTRIBUTION CIRCUIT 5 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Byte 1: Control Register Bit 7 to 0 Description Reserved Type RW Power Up Condition Undefined Output(s) Affected Not applicable Notes Byte 2: Control Register Bit 7 to 0 Description Reserved Type RW Power Up Condition Undefined Output(s) Affected Not applicable Notes Byte 3: Control Register Bit 7 to 0 Description Reserved Type RW Power Up Condition Undefined Output(s) Affected Not applicable Notes Byte 4 through 5: Control Register Bit 7 to 0 Description Reserved Type RW Power Up Condition Undefined Output(s) Affected Not applicable Notes Byte 6: Control Register Bit 7 6 5 4 3 2 1 0 Description Revision ID bit 3 Revision ID bit 2 Revision ID bit 1 Revision ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 Type RW RW RW RW RW RW RW RW Power Up 0 0 0 0 0 0 0 1 Output(s) Affected Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Notes IDT™ CLOCK DISTRIBUTION CIRCUIT 6 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Applications Information External Components A minimum number of external components are required for proper operation. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT6P30006A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Decoupling Capacitors Decoupling capacitors of 0.01 µF should be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into IDT pin. IDT™ CLOCK DISTRIBUTION CIRCUIT 7 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT6P30006A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Max Supply Voltage, VDD LVCMOS_INB, SCLK and SDATA Inputs All Other Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Peak Soldering Temperature 5V -0.5 V to +3.3 V Rating -0.5 V to VDD+0.5 V -40 to +85° C -65 to +150° C 125° C 260° C Recommended Operation Conditions Parameter Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Min. -40 1.62 Typ. +1.8 Max. +85 1.98 Units °C V DC Electrical Characteristics Unless otherwise specified, VDD=1.8 V ±10%, Ambient Temperature -40 to +85° C Parameter Operating Supply Voltage Input High Voltage Symbol VDD VIH Conditions SEL, OE pins, LVCMOS_INB, TCXO_INA SCLK and SDATA SEL, OE pins, LVCMOS_INB, TCXO_INA SCLK and SDATA IOH = -4 mA IOL = 4 mA No load, all outputs switching at 13 MHz All outputs disabled Single-ended clocks All clock outputs, OEx=1 Min. 1.62 0.75xVDD 0.7xVDD Typ. 1.8 Max. 1.98 Units V V Input Low Voltage VIL 0.35xVDD 0.3xVDD VDD-0.4 0.4 4 500 ±70 15 6 V High-Level Output Voltage Low-Level Output Voltage Operating Supply Current VOH VOL IDD V V mA µA mA Ω Short Circuit Current Output Impedance IOS ZO IDT™ CLOCK DISTRIBUTION CIRCUIT 8 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Parameter Internal Pull-Up Resistor Internal Pull-Down Resistor Input Capacitance Symbol RPU RPD CIN Conditions SEL, OEx All clock outputs, OEx=0 All input pins Min. Typ. 500 250 6 Max. Units kΩ kΩ pF AC Electrical Characteristics - Single-Ended Outputs Unless otherwise stated, VDD = 1.8 V ±10%, Ambient Temperature -40 to +85° C Parameter Input Frequency TCXO Input Swing Variance Input Frequencies Time Switch Clock Inputs Output Frequency Error Output Rise Time Output Fall Time Output Clock Duty Cycle Clock Stabilization Time from Power Up Symbol FIN Conditions Min. 12.6 ±100 Typ. 13 Max. 13.4 ±900 0.4 Units MHz mV MHz µs ppm LVCMOS_INB, TCXO_INA, Note 2 LVCMOS_INB, TCXO_INA, Note 3 tOR tOF 20% to 80%, Note 1 80% to 20%, Note 1 Measured at VDD/2, Note 1 Power up, output within 1% of final frequency 45 80 0 1 1 50 3 1.5 1.5 55 10 ns ns % ms Note 1: CL = 5 pF. Note 2: Delta from 13 MHz. Note 3: By removing primary input and then bringing back primary input. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol θJA θJA θJA θJC Conditions Still air 1 m/s air flow 2.5 m/s air flow Min. Typ. 29.1 22.8 21.0 41.8 Max. Units ° C/W ° C/W ° C/W ° C/W Thermal Resistance Junction to Case IDT™ CLOCK DISTRIBUTION CIRCUIT 9 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Marking Diagram TBD Notes: 1. “Z” is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “$” is the assembly mark code. 4. “G” after the two-letter package code designates RoHS compliant package. 5. “I” at the end of part number indicates industrial temperature range. 6. Bottom marking: country of origin if not USA. IDT™ CLOCK DISTRIBUTION CIRCUIT 10 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Package Outline and Package Dimensions (24-pin QFN) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area N 1 2 A1 A3 (ND-1)x e (Ref) L N 1 2 Sawn Singulation Top View A E2 (Ref) ND & NE Even e (Typ) If ND & NE 2 are Even (NE-1)x e (Ref) E E2 2 b e D2 2 D2 D (Ref) ND & NE Odd Thermal Base 0.08 C Symbol Min Millimeters Max C A A1 A3 b e N ND NE D x E BASIC D2 E2 L 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC 24 6 6 4.00 x 4.00 2.3 2.55 2.3 2.55 0.30 0.50 Ordering Information Part / Order Number 6P30006ANLGI 6P30006ANLGI8 Marking TBD Shipping Packaging Tubes Tape and Reel Package 24-pin QFN 24-pin QFN Temperature -40 to +85° C -40 to +85° C “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ CLOCK DISTRIBUTION CIRCUIT 11 IDT6P30006A REV C 111009 IDT6P30006A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA