IDT7009L15PF

HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM Features x x x IDT7009L x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20ns (max.) Low-power operation – IDT7009L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device x x x x x x x M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in a 100-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL CE0L CE1L OEL R/WR CE0R CE1R OE R I/O0-7L I/O Control I/O Control I/O0-7R BUSYL A16L A0L (1,2) BUSYR 128Kx8 MEMORY ARRAY 7009 17 17 (1,2) Address Decoder Address Decoder A16R A0R CE0L CE1L OEL R/W L SEML (2) INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0R CE1R OER R/WR SEMR (2) INT R 4839 drw 01 M/S (1) NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). JANUARY 2001 DSC-4839/2 1 ©2000 Integrated Device Technology, Inc. IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT7009 is a high-speed 128K x 8 Dual-Port Static RAM. The IDT7009 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-ormore word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only1W of power. The IDT7009 is packaged in a 100-pin Thin Quad Flatpack (TQFP). Pin Configurations(1,2,3) Index NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L Vcc NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 NC NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC IDT7009PF PN100-1(4) 100-Pin TQFP Top View(5) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC 4839 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC 2 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A16L I/O0L - I/O7L SEML INTL BUSYL Right Port CE0R, CE1R R/WR OER A0R - A16R I/O0R - I/O7R SEMR INTR BUSYR M/S VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground 4839 tbl 01 Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V Recommended DC Operating Conditions Symbol VCC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 ____ Max. 5.5 0 6.0(2) 0.8 Unit V V V V 4839 tbl 04 TBIAS TSTG IOUT -55 to +125 -65 to +150 50 -65 to +135 -65 to +150 50 o GND C VIH o C VIL ____ mA 4839 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. Capacitance Sym bol C IN (TA = +25°C, f = 1.0MHz) (TQFP Only) Param eter (1) Inp ut Cap acitanc e Outp ut Cap acitanc e Conditions (2) V IN = 3 d V V OUT = 3 d V Max. 9 10 Unit pF pF 4839 tbl 05 Maximum Operating Temperature and Supply Voltage(1) Grade Military Commercial Industrial Ambient Temperature(2) -55 C to +125 C 0 C to +70 C -40OC to +85OC O O O O C OUT GND 0V 0V 0V Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10% 4839 tbl 03 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. NOTES: 1. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature. 3 6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I: Chip Enable(1,2) CE CE0 VIL L < 0.2V VIH X H > VCC -0.2V X CE1 VIH > VCC -0.2V X VIL X V CC - 0.2V. Truth Table II: Non-Contention Read/Write Control Inputs(1) CE (2) Outputs SEM H H H X I/O0-7 High-Z DATAIN DATA OUT High-Z Deselected: Power-Down Write to memory Read memory Outputs Disabled 4839 drw 07 R/W X L H X OE X X L H Mode H L L X NOTES: 1. A0L – A16L ≠ A0R – A16R. 2. Refer to Chip Enable Truth Table. Truth Table III: Semaphore Read/Write Control(1) Inputs CE (2) Outputs SEM L L L I/O0-7 DATA OUT DATA IN ______ R/ W H OE L X X Mode Read Semaphore Flag Data Out Write I/O0 into Semaphore Flag Not Allowed 4839 tbl 08 H H L ↑ X NOTES: 1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2. 2. Refer to Chip Enable Truth Table. 4 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%) 7009L Symbol |ILI| |ILO | VOL VOH Parameter Input Leakage Current (1) Test Conditions VCC = 5.5V, VIN = 0V to V CC CE = VIH, VOUT = 0V to V CC IOL = 4mA IOH = -4mA Min. ___ Max. 5 5 0.4 ___ Unit µA µA V V 4839 tbl 09 Output Leakage Current Output Low Voltage Output High Voltage ___ ___ 2.4 NOTES: 1. At Vcc < 2.0V, input leakages are undefined. 2. Refer to Chip Enable Truth Table. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6,7) (VCC = 5.0V ± 10%) Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(2) CEL = C ER = VIH SEMR = SEML = VIH f = fMAX(2) CE"A" = VIL and C E"B" = VIH(4) Active Port Outputs Disabled, f=fMAX(2) , SEMR = SEML = VIH Both Ports C EL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(4) , SEMR = SEML > VCC - 0.2V, VIN > VCC - 0.2V or V IN < 0.2V, Active Port Outputs Disabled , f = fMAX(2) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND L L L L L L L L L L 7009L15 Com'l Only Typ. (1) Max 220 ____ 7009L20 Com'l Only Typ.(1) Max 200 ____ Unit mA 340 ____ 300 ____ ISB1 65 ____ 100 ____ 50 ____ 75 ____ mA ISB2 145 ____ 225 ____ 130 ____ 195 ____ mA ISB3 0.2 ____ 3.0 ____ 0.2 ____ 3.0 ____ mA ISB4 135 ____ 220 ____ 120 ____ 190 ____ mA NOTES: 1. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 3. f = 0 means no address or control lines change. 4. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5. Refer to Chip Enable Truth Table. 6. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 4839 tbl 10 5 6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 5V 5V 893Ω DATAOUT BUSY INT DATAOUT 347Ω 30pF 347Ω 5pF* 893Ω AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2 4839 tbl 11 4839 drw 03 4839 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ , tHZ, tWZ, tOW) * Including scope and jig. Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE OE (4) (4) CE(6) R/W tLZ DATAOUT (1) tOH VALID DATA (4) (2) tHZ BUSYOUT tBDD (3,4) 4839 drw 05 Timing of Power-Up Power-Down CE ICC ISB 4839 drw 06 . (6) tPU 50% tPD 50% NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD . 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. 6 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) 7009L15 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time (4) 7009L20 Com'l Only Min. Max. Unit Parameter Min. Max. 15 ____ ____ 20 ____ ____ ns ns ns ns ns ns ns ns ns ns ns 4839 tbl 12 15 15 10 ____ 20 20 12 ____ ____ ____ Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) Output High-Z Time (1,2) (2) (2) ____ ____ 3 3 ____ 3 3 ____ ____ ____ 10 ____ 10 ____ Chip Enable to Power Up Time 0 ____ 0 ____ Chip Disable to Power Down Time 15 ____ 20 ____ Semaphore Flag Update Pulse (OE o r SEM) Semaphore Address Access Time 10 ____ 10 ____ 15 20 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7009L15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) 7009L20 Com'l Only Min. Max. Unit Parameter Min. Max. 15 12 12 0 12 0 10 ____ ____ 20 15 15 0 15 0 15 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 4839 tbl 13 ____ ____ ____ ____ Address Valid to End-of-Write Address Set-up Time (3) Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) (1,2) (1,2) ____ ____ ____ ____ ____ ____ ____ ____ 10 ____ 10 ____ 0 ____ 0 ____ Write Enable to Output in High-Z Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window 10 ____ 10 ____ (1,2,4) 0 5 5 0 5 5 ____ ____ ____ ____ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 7 6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ OE tAW CE or SEM (9,10) (7) tAS(6) R/W tWZ DATAOUT (4) (7) tWP (2) tWR (3) tOW (4) tDW DATAIN tDH 4839 drw 07 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM(9,10) tAS R/W tDW DATAIN 4839 drw 08 (6) tEW (2) tWR (3) tDH NOTES: 1. R/W or CE = V IH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = V IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/ W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. 8 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW SEM tEW tDW DATA0 tAS R/W tSWRD OE Write Cycle tOH VALID ADDRESS tACE tWR tSOP DATAOUT VALID(2) DATAIN VALID tWP tDH tAOE tSOP Read Cycle 4839 drw 09 NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O7) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" MATCH SIDE (2) "B" R/W"B" SEM"B" 4839 drw 10 NOTES: 1. DOR = DOL = VIL, CEL = CE R = VIH (Refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 9 6.42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7009L15 Com'l Only Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Acce ss Time from Chip Enable Low BUSY Acce ss Time from Chip Enable High Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data Write Hold After BUSY (5) (3) ____ 7009L20 Com'l Only Min. Max. Unit Parameter Min. Max. 15 15 15 15 ____ ____ 20 20 20 17 ____ ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ 5 ____ 5 ____ 15 ____ 17 ____ 12 15 BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY(5) 0 12 ____ 0 15 ____ ns ns ____ ____ PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ____ 30 25 ____ 45 30 ns ns 4839 tbl 14 ____ ____ NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 10 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" (1) tDH VALID MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" tDDD (3) 4839 drw 11 VALID NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL, refer to Chip Enable Truth Table. 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE), BUSY is an input. Then for this example BUSY "A" = VIH and BUSY "B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B" (2) NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the 'Slave' version. 4839 drw 12 . 611 .42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3) ADDR"A" and "B" CE"A" tAPS CE"B" tBAC BUSY"B" 4839 drw 13 (2) ADDRESSES MATCH tBDC Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDR"A" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA BUSY"B" tBDA 4839 drw 14 ADDRESS "N" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. Refer to Chip Enable Truth Table. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 7009L15 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ 7009L20 Com'l Only Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ns ns ns ns 4839 tbl 15 ____ ____ 15 15 20 20 ____ ____ NOTES: 1. Industrial Temperature: for specific speeds, packages and powers contact your sales office. 12 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1,5) tWC ADDR"A" tAS CE"A" (3) INTERRUPT SET ADDRESS (2) (4) tWR R/W"A" tINS (3) INT"B" 4839 drw 15 tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS (3) CE"B" (2) OE"B" tINR (3) INT"B" 4839 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/ W) is de-asserted first. 5. Refer to Chip Enable Truth Table. Truth Table IV — Interrupt Flag(1,4,5) Left Port R/WL L X X X CEL L X X L OEL X X X L A16L-A0L 1FFFF X X 1FFFE INTL X X L (3) (2) Right Port R/ WR X X L X CER X L L X OER X L X X A16R-A0R X 1FFFF 1FFFE X INTR L(2) H (3) Function Set Rig ht INTR F lag Rese t Rig ht INTR F lag Set Left INTL F lag Re se t Left INTL F lag 4839 tbl 16 X X H NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 5. Refer to Chip Enable Truth Table. 613 .42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table V —Address BUSY Arbitration(4) Inputs CEL X H X L CER X X H L A OL-A16L AOR -A16R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 4839 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7009 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSY R = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Chip Enable Truth Table. Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D7 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 4839 tbl 18 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7009. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description The IDT7009 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7009 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFFE (HEX), where a write is defined as CER = R/WR = VIL per Truth Table IV. The left port clears the interrupt through access of address location 1FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFFF. The message (8 bits) at 1FFFE or 1FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFFE and 1FFFF are not used as mail boxes, but as part of the random access memory. Refer to Table IV for the interrupt operation. 14 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7009 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. A17 CE0 MASTER Dual Port RAM BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7009 is an extremely fast Dual-Port 128K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the DualPort RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM are both HIGH. Systems which can best use the IDT7009 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7009s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7009 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. CE1 MASTER Dual Port RAM BUSYL BUSYR CE1 SLAVE Dual Port RAM BUSYL BUSYR 4839 drw 17 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7009 RAMs. Width Expansion Busy Logic Master/Slave Arrays When expanding an IDT7009 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7009 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform 615 .42 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7009 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table VI). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table VI). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ Figure 4. IDT7009 Semaphore Logic SEMAPHORE READ 4839 drw 18 over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 16 IDT7009L High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +70°C PF 100-pin TQFP (PN100-1) 15 20 Commercial Only Commercial Only Speed in nanoseconds L 7009 Low Power 1024K (128K x 8) Dual-Port RAM 4839 drw 19 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. Datasheet Document History 9/30/99: 11/10/99: 1/5/01: Initial Public Release Replaced IDT logo Page 3 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Page 14 Added IV to Truth Table in Interrupts paragraph Changed ±200mV to 0mV in notes Removed Preliminary specification CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 617 .42