IDT70121S55JGI

HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT Features ✵ ◆ ◆ IDT70121S/L IDT70125S/L ◆ High-speed access – Commercial: 25/35/45/55ns (max.) – Industrial: 35ns (max.) Low-power operation – IDT70121/70125S Active: 675mW (typ.) Standby: 5mW (typ.) – IDT70121/70125L Active: 675mW (typ.) Standby: 1mW (typ.) ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Fully asychronous operation from either port MASTER IDT70121 easily expands data bus width to 18 bits or more using SLAVE IDT70125 chip On-chip port arbitration logic (IDT70121 only) BUSY output flag on Master; BUSY input on Slave INT flag for port-to-port communication Battery backup operation—2V data retention TTL-compatible, signal 5V (±10%) power supply Available in 52-pin PLCC Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram OEL CEL R/WL OER CER R/WR I/O0L- I/O8L I/O Control BUSYL A10L A0L (1,2) I/O0R-I/O8R I/O Control BUSYR Address Decoder 11 (1,2) MEMORY ARRAY 11 Address Decoder A10R A0R CEL OEL R/WL ARBITRATION INTERRUPT LOGIC CER OER R/WR INTL (2) INTR 2654 drw 01 (2) NOTES: 1. 70121 (MASTER): BUSY is non-tri-stated push-pull output. 70125 (SLAVE): BUSY is input. 2. INT is non-tri-stated push-pull output. APRIL 2006 1 ©2006 Integrated Device Technology, Inc. DSC 2654/10 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Description The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit DualPort RAM or as a “MASTER” Dual-Port RAM together with the IDT70125 “SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power-down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for Data/Control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 675mW of power. Low-power (L) versions offer battery backup data retention capability with each port typically consuming 200µW from a 2V battery. The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. Pin Configurations(1,2,3) A0L OEL A10L INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR A10R 51 52 50 7 6 5 49 48 47 3 4 2 46 45 44 43 05/27/04 INDEX 21 22 23 24 25 26 27 28 29 30 31 32 33 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 IDT70121/125J J52-1(4) 52-Pin PLCC Top View(5) 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O8R I/O7R . I/O 4L I/O 5L I/O 6L I/O 7L I/O 8L GND I/O 0R I/O 1R I/O 2R I/O 3R I/O 4R I/O 5R I/O 6R NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 1 2654 drw 02 2 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V Recommended DC Operating Conditions Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 ____ Max. 5.5 0 6.0 (2) Unit V V V V 2654 tbl 03 TBIAS TSTG IOUT -55 to +125 -65 to +150 50 o C C VIH VIL ____ o 0.8 mA 2654 tbl 01 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(1) V IN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF 2654 tbl 04 Maximum Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40 C to +85 C O O NOTE: 1. This parameter is determined by device characterization but is not production tested. GND 0V 0V Vcc 5.0V + 10% 5.0V + 10% 2654 tbl 02 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 70121S 70125S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) 70121L 70125L Max. 10 10 0.4 ___ Test Conditions V CC = 5.5V, VIN = 0V to V CC V CC = 5.5V, CE = VIH, VOUT = 0V to V CC IOL = +4mA IOH = -4mA Min. ___ Min. ___ Max. 5 5 0.4 ___ Unit µA µA V V 2654 tbl 05 Output Leakage Current Output Low Voltage Output High Voltage ___ ___ ___ ___ 2.4 2.4 NOTE: 1. At Vcc < 2.0V leakages are undefined. 3 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,4) (VCC = 5V ± 10%) 70121X25 70125X25 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled f = fMAX(2) Version COM'L IND COM'L IND COM'L IND ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) CE"A" and C E"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) COM'L IND COM'L S L S L S L S L S L S L S L S L S L S L Typ. 135 135 ___ ___ 70121X35 70125X35 Com'l & Ind Typ. 135 135 135 135 30 30 30 30 80 80 80 80 1.0 0.2 1.0 0.2 70 70 70 70 Max. 250 210 275 250 65 45 80 65 165 135 190 165 15 5 15 5 160 130 185 160 2654 tbl 06a Max. 260 220 ___ ___ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CE"A" = C E"B" = VIH f = fMAX (2) 30 30 ___ ___ 65 45 ___ ___ mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and C E"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(2) 80 80 ___ ___ 175 145 ___ ___ mA 1.0 0.2 ___ ___ 15 5 ___ ___ mA ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(2) 70 70 ___ ___ 170 140 ___ ___ mA IND 70121X45 70125X45 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled f = fMAX (2) 70121X55 70125X55 Com'l Only Typ. 135 135 ___ ___ Version COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. 135 135 ___ ___ Max. 245 205 ___ ___ Max. 240 200 ___ ___ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CE"A" = CE"B" = VIH f = fMAX (2) 30 30 ___ ___ 65 45 ___ ___ 30 30 ___ ___ 65 45 ___ ___ mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(2) 80 80 ___ ___ 160 130 ___ ___ 80 80 ___ ___ 155 125 ___ ___ mA ISB3 Full Standby Current (Both Ports - CMOS Level Inputs) CE"A" and CE"B" > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) COM'L IND COM'L IND 1.0 0.2 ___ ___ 15 5 ___ ___ 1.0 0.2 ___ ___ 15 5 ___ ___ mA ISB4 Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled, f = fMAX(2) 70 70 ___ ___ 155 125 ___ ___ 70 70 ___ ___ 150 120 ___ ___ mA NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 4. Vcc=5V, TA=+25°C for Typ, and is not production tested. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". 2654 tbl 06b 4 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Data Retention Characteristics (L Version Only) Symbol VDR ICCDR tCDR (3) tR(3) Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2 IND. COM'L. Test Condition Min. 2.0 ___ Typ.(1) ___ Max. ___ Unit V µA 100 100 ___ 4000 1500 ___ ___ tRC(2) V 2654 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed but is not production tested. Data Retention Waveform DATA RETENTION MODE Vcc 4.5V tCDR CE VIH VDR VDR ≥ 2V 4.5V tR VIH 2654 drw 03 AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1 and 2 2654 tbl 08 5V 1250Ω DATAOUT BUSY INT DATAOUT 775Ω 30pF 775Ω 5V 1250Ω 5pF* 2654 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ , tHZ , tWZ, tOW) *Including scope and jig. 5 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) 70121X25 70125X25 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) (1,2) (2) (2) 70121X35 70125X35 Com'l & Ind Min. Max. Unit Parameter Min. Max. 25 ____ ____ 35 ____ ____ ns ns ns ns ns ns ns ns ns 2654 tbl 09a 25 25 12 ____ 35 35 25 ____ ____ ____ ____ ____ 0 0 ____ 0 0 ____ ____ ____ Output High-Z Time 10 ____ 15 ____ Chip Enable to Power Up Time 0 ____ 0 ____ Chip Disable to Power Down Time 50 50 70121X45 70125X45 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) 70121X55 70125X55 Com'l Only Min. Max. Unit Parameter Min. Max. 45 ____ ____ 55 ____ ____ ns ns ns ns ns ns ns ns ns 2654 tbl 09b 45 45 30 ____ ____ 55 55 35 ____ ____ ____ ____ ____ ____ 0 0 ____ 0 0 ____ Output High-Z Time (1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) 20 ____ 30 ____ 0 ____ 0 ____ 50 50 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L). 6 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1,2,4) tRC ADDRESS tAA tOH DATAOUT BUSYOUT 2654 drw 05 tOH DATA VALID PREVIOUS DATA VALID tBDD (3,4) Timing Waveform of Read Cycle No. 2, Either Side(5) tACE CE tAOE (4) tHZ (2) OE tLZ (1) DATAOUT tLZ (1) ICC CURRENT ISS tPU tHZ (2) VALID DATA tPD (4) 50% 50% 2654 drw 06 NOTES: 1. Timing depends on which signal is aserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/ W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW. 7 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70121X25 70125X25 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (4) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width(6) Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (5) (1,3) (1,2,3) 70121X35 70125X35 Com'l & Ind Min. Max. Unit Parameter Min. Max. 25 20 20 0 20 0 12 ____ ____ ____ 35 30 30 0 30 0 20 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2654 tbl 10a ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 10 ____ 15 ____ 0 ____ 0 ____ Write Enable to Output in High-Z Output Active from End-of-Write 10 ____ 15 ____ (1,2,3,5) 0 0 70121X45 70125X45 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (4) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width (6) 70121X55 70125X55 Com'l Only Min. Max. Unit Parameter Min. Max. 45 35 35 0 35 0 20 ____ ____ ____ ____ ____ 55 40 40 0 40 0 20 ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns 2654 tbl 10b ____ ____ ____ ____ ____ ____ Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (5) (1,2,3) 20 ____ 30 ____ 0 ____ 0 ____ Write Enable to Output in High-Z(1,3) Output Active from End-of-Write (1,2,3,5) 20 ____ 30 ____ 0 0 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter guaranteed by device characterization, but is not production tested. 3. For MASTER/SLAVE combination, tWC = t BAA + tWP, since R/W = VIL must occur after tBAA . 4. 'X' in part numbers indicates power rating (S or L). 5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW. 6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 8 6.42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE R/W tAS(6) tWP (2) tHZ (7) tWR(3) tWZ (7) DATAOUT (4) tOW (4) tDW DATAIN tDH 2654 drw 07 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE tAS(6) R/W tDW DATAIN 2654 drw 08 (3) tEW (2) tWR tDH NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or t WP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW . If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 70121X25 70125X25 Com'l Only Symbol BUSY TIMING (For MASTER IDT70121) tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD tWH BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay (1) (1) ____ 70121X35 70125X35 Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 20 20 20 50 35 ____ 20 20 20 20 60 45 ns ns ns ns ____ ____ ____ ____ ____ ____ Write Data Valid to Read Data Delay Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data Write Hold After BUSY (5) (3) 5 ____ ____ 5 ____ ____ ns ns ns 30 ____ 30 ____ 15 20 BUSY INPUT TIMING (For SLAVE IDT70125) tWB tWH tWDD tDDD Write to BUSY Input(4) Write Hold After BUSY(5) Write Pulse to Data Delay (1) (1) 0 15 ____ ____ 0 20 ____ ____ ns ns ns ns 2654 tbl 11a ____ ____ 50 35 60 45 Write Data Valid to Read Data Delay ____ ____ 70121X45 70125X45 Com'l Only Symbol BUSY TIMING (For MASTER IDT 70121) tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD tWH BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Pulse to Data Delay (1) (1) ____ 70121X55 70125X55 Com'l Only Min. Max. Unit Parameter Min. Max. 20 20 20 20 70 55 ____ 30 30 30 30 80 65 ns ns ns ns ____ ____ ____ ____ ____ ____ Write Data Valid to Read Data Delay Arbitration Priority Set-up Time BUSY Disable to Valid Data Write Hold After BUSY(5) (3) (2) 5 ____ ____ 5 ____ ____ ns ns ns 35 ____ 45 ____ 20 20 BUSY INPUT TIMING (For SLAVE IDT 70125) tWB tWH tWDD tDDD Write to BUSY Input(4) Write Hold After BUSY(5) Write Pulse to Data Delay (1) (1) 0 20 ____ ____ ____ 0 20 ____ ____ ____ ns ns ns ns 2654 tbl 11b ____ ____ 70 55 80 65 Write Data Valid to Read Data Delay NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.. 5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 6. 'X' in part numbers indicates power rating (S or L). 610 .42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3) tWC ADDR 'A' MATCH tWP R/W'A' tDW DATAIN'A' tAPS (1) ADDR'B' MATCH tBDA BUSY'B' tWDD DATAOUT 'B' tDDD (4) 2654 drw 09 tDH VALID tBDD VALID NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125). 2. CE L = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite from port "A". Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH (1) R/W"B" (2) 2654 drw 10 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A". Timing Waveform of BUSY Arbritration Controlled by CE Timing(1) ADDR"A and B" (1) ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC BUSY"B" 2654 drw 11 tBDC NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). 11 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of BUSY Arbritration Controlled by Address(1) tRC OR tWC ADDR'A' tAPS(2) ADDR'B' tBAA BUSY'B' NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (70121 only). 2654 drw 12 ADDRESSES MATCH ADDRESSES DO NOT MATCH tBDA AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 70121X25 70125X25 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ 70121X35 70125X35 Com'l & Ind Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ns ns ns ns 2654 tbl 12a ____ ____ 25 25 35 35 ____ ____ 70121X45 70125X45 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ 70121X55 70125X55 Com'l Only Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ns ns ns ns 2654 tbl 12b ____ ____ 40 40 45 45 ____ ____ NOTES: 1. 'X' in part numbers indicates power rating (S or L). 612 .42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Timing Waveform of Interrupt Mode(1) tWC ADDR'A' INTERRUPT SET ADDRESS (2) tAS(3) R/W'A' tINS (3) INT'B' NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 2654 drw 13 tWR(4) Truth Tables Truth Table I. Non-Contention Read/Write Control(4) Left or Right Port(1) R/W X X L H H CE H H L L L OE X X X L H D0-8 Z Z DATAIN DATAOUT Z Function Port Disab le and in Power-Down Mode, ISB2 o r ISB4 CER = C EL = H, Power-DownMode, ISB1 o r ISB3 Data on Port Written Into Memory (2) Data in Memory Output on Port(3) High-Impedance Outputs 2654 tbl 13 NOTES: 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE Truth Table II. Interrupt Flag(1,4) Left Port R/WL L X X X CEL L X X L OEL X X X L A10L-A0L 7FF X X 7FE INTL X X L(3) H(2) R/ WR X X L X CER X L L X Right Port OER X L X X A10R-A0R X 7FF 7FE X INTR L(2) H(3) X X Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 2654 tbl 14 NOTES : 1. Assumes BUSYL = BUSYR = V IH 2. If BUSY L = VIL, then No Change. 3. If BUSY R = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE 13 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Functional Description The IDT70121/125 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70121/125 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. The BUSY outputs on the IDT70121/125 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70121/125 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70121 RAM the BUSY pin is an output of the part, and the BUSY pin is an input of the IDT70125 as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and DECODER BUSYR , 2654 drw 14 Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CE = R/W = VIL per Truth Table II. The left port clears the interrupt by access address location 7FE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (9 bits) at 7FE or 7FF is userdefined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation. CE MASTER Dual Port RAM BUSYL BUSYR CE SLAVE Dual Port RAM BUSYL BUSYR Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by using the IDT70125 (SLAVE). In the IDT70125, the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. BUSYL MASTER CE Dual Port RAM BUSYL BUSYR SLAVE CE Dual Port RAM BUSYR BUSYL Figure 3. Busy and chip enable routing for both width and depth expansion with 70121 (Master) and 70125 (Slave) RAMs. inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. 614 .42 APRIL 05, 2006 IDT70121/IDT70125 High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX X XXX X X X Process/ Temperature Range Device Power Speed Package Type Blank I (1) G J 25 35 45 55 L S 70121 70125 Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Green 52-pin PLCC (J52-1) Commercial Only Commercial & Industrial Commercial Only Commercial Only Low Power Standard Power 18K (2K x 9-Bit) MASTER Dual-Port RAM w/ Interrupt 18K (2K x 9-Bit) SLAVE Dual-Port RAM w/ Interrupt 2654 drw 15 , Speed in nanoseconds NOTE : 1. Industrial temperature: for other speeds, packages and powers contact your sales office. Datasheet Document History 01/06/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Page 3 Changed storage temperature parameter from -55 to +125 to -65 to +150 Clarified TA parameter footnote Page 4 DC Electrical parameters–changed test condition wording from "open" to "disabled" Page 9 Changed ±500mV to 0mV in notes Page 2 Added date revision for pin configuration Page 4, 6, 8,10&12 Added Industrial temp to column headings for 35ns speed to DC and AC Electrical Characteristics Page 4 Removed Industrial temp from 25, 45 & 55ns speeds from DC Electrical Characteristics Page 3, 4, 6, 8,10&12 Removed Industrial temp footnote from all tables Page 10 Corrected error in AC BUSY timing tables changing 71V33 to 70121 and changing 71V43 to 70125 Page 15 Added Industrial temp offering to 35ns ordering information Page 1 & 15 Replaced old TM logo with new TM logo Page 6 Footnote reference 5 removed from AC Electrical Characteristics READ table Page 1 Changed wording of footnote 1 from "INT is totem-pole output" to "INT is non-tr-stated push-pull output" Page 5 Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns Page 1 Added green availability to features Page 15 Added green indicator to ordering information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: 408-284-2794 DualPortHelp@idt.com 06/03/99: 05/28/04: 04/05/06: The IDT logo is a registered trademark of Integrated Device Technology, Inc. 15 APRIL 05, 2006