IDT7014S12PF

HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM Features: x x IDT7014S Description: The IDT7014 is a high-speed 4K x 9 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to high-speed applications which do not rely on BUSY signals to manage simultaneous access. The IDT7014 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. See functional description. The IDT7014 utilitizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using IDT’s high-performance technology, these DualPorts typically operate on only 750mW of power at maximum access times as fast as 12ns. The IDT7014 is packaged in a 52-pin PLCC and a 64-pin thin quad flatpack, (TQFP). x x x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 12/15/20/25ns (max.) – Industrial: 15/20/25ns (max.) Standard-power operation – IDT7014S Active: 750mW (typ.) Fully asynchronous operation from either port TTL-compatible; single 5V (±10%) power supply Available in 52-pin PLCC and a 64-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL R/WR OEL I/O0L- I/O8L I/O CONTROL I/O CONTROL OER I/O0R- I/O8R A0L- A11L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER A0R- A11R 2528 drw 01 MARCH 2000 1 ©2000 Integrated Device Technology, Inc. DSC 2528/13 IDT7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges INDEX A6L A7L A8L A9L A10L A11L OEL VCC R/WL GND I/O8L I/O7L I/O6L 765432 52 51 50 49 48 47 1 46 8 45 9 10 44 43 11 42 12 IDT 7014J 41 13 J52-1(4) 40 14 39 15 52-Pin PLCC (5) 38 16 Top View 37 17 36 18 35 19 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A5L A4L A3L A2L A1L A0L A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R A10R A11R OER GND R/WR GND I/O8R I/O7R I/O6R I/O5R Pin Configuration(1,2,3) I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L I/O0R I/O1R I/O2R I/O3R VCC I/O4R , 2528 drw 02 INDEX A6L A7L A8L A9L A10L A11L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 A5L A4L A3L A2L A1L A0L N/C N/C N/C N/C A0R A1R A2R A3R A4R A5R 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OEL N/C VCC N/C R/WL N/C GND I/O8L I/O7L I/O6L A6R A7R A8R A9R A10R A11R IDT7014PF PN64-1(4) 64-Pin TQFP Top View(5) OER N/C GND N/C R/WR N/C GND I/O8R I/O7R I/O6R NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in. x .17 in. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate the orientation of the actual part-marking I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R 2 2528 drw 03 IDT7014S/L High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Absolute Maximum Ratings (1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Terminal Voltage Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V Maximum Operating Temperature and Supply Voltage(1,2) Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10% 2528 tbl 02 VTERM(2) TBIAS TSTG IOUT -0.5 to +VCC -55 to +125 -55 to +125 50 V o Industrial C C NOTES: 1. This is the parameter TA. o mA 2528 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) Typ. 5.0 0 ____ Max. 5.5 0 6.0(2) 0.8 Unit V V V V 2528 tbl 03 ____ NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7014S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to V CC VOUT = 0V to V CC IOL = + 4mA IOH = -4mA Min. ___ ___ ___ Max. 10 10 0.4 ___ Unit µA µA V V 2528 tbl 04 2.4 NOTE: 1. At VCC < 2.0V input leakages are undefined. 3 6.42 IDT7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5V ± 10%) 7014S12 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Outputs Open f = fMAX(1) Version COM'L IND S S Typ. 160 ____ 7014S15 Com'l & Ind Typ. 160 160 Max 250 260 2528 tbl 05a Max 250 ____ Unit mA 7014S20 Com'l & Ind Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition Outputs Open f = fMAX(1) Version COM'L IND S S Typ. 155 155 Max 245 260 7014S25 Com'l & Ind Typ. 150 150 Max. 240 255 2528 tbl 05b Unit mA NOTES: 1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V. AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3 2528 tbl 06 5V 893Ω DATAOUT 347Ω 30pF DATAOUT 347Ω 5V 893Ω 5pF* 2528 drw 04 2528 drw 05 Figure 1. AC Output Test Load. Capacitance(1) Symbol CIN COUT Figure 2. Output Test Load (for tHZ, tWZ, and t OW) *Including scope and jig. Conditions(2) VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF 2528 tbl 07 (TA = +25°C, f = 1.0MHz) TQFP Package Only Parameter Input Capacitance Output Capacitance 8 7 6 - 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance NOTES: 1. This parameter is determined by device characteristics but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals swith from 0V to 3V or from 3V to 0V. tAA (Typical, ns) 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 2528 drw 06 , Figure 3. Typical Output Derating (Lumped Capacitive Load). 4 IDT7014S/L High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 7014S12 Com'l Only Symbol READ CYCLE tRC tAA tAOE tOH tLZ tHZ Read Cycle Time Address Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) (1,2) 7014S15 Com'l & Ind Min. Max. Unit Parameter Min. Max. 12 ____ ____ ____ 15 ____ ____ ____ ns ns ns ns ns ns 2528 tbl 08a 12 8 ____ ____ 15 8 ____ ____ 3 3 ____ 3 3 ____ Output High-Z Time 7 7 7014S20 Com'l & Ind Symbol READ CYCLE tRC tAA tAOE tOH tLZ tHZ Read Cycle Time Address Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) 7014S25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 ____ ____ ____ 25 ____ ____ ____ ns ns ns ns ns ns 2528 tbl 08b 20 10 ____ ____ 25 12 ____ ____ 3 3 ____ 3 3 ____ Output High-Z Time(1,2) 9 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization, but is not production tested. 5 6.42 IDT7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1,2) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID 2528 drw 07 Timing Waveform of Read Cycle No. 2, Either Side(1, 3) tAOE OE tLZ DATAOUT VALID DATA tHZ NOTES: 1. R/W = VIH for Read Cycles. 2. OE = VIL. 3. Addresses valid prior to OE transition LOW. 2528 drw 08 Timing Waveform of Write with Port-to-Port Read(1,2) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" VALID tDH ADDR"B" MATCH tWDD DATAOUT "B" tDDD VALID 2528 drw 09 NOTES: 1. R/W"B" = VIH, read cycle pass through. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A". 6 IDT7014S/L High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 7014S12 Com'l Only Symbol WRITE CYCLE tWC tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (3) (1,2) 7014S15 Com'l & Ind Min. Max. Unit Parameter Min. Max. 12 10 0 10 1 8 ____ ____ 15 14 0 12 1 10 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 2528 tbl 09a ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 7 ____ 7 ____ 0 ____ 0 ____ Write Enable to Output in High-Z(1,2) Output Active from End-of-Write (1,2,3) Write Pulse to Data Delay (4) (4) 7 ____ 7 ____ 0 ____ 0 ____ 25 22 30 25 Write Data Valid to Read Data Delay ____ ____ 7014S20 Com'l & Ind Symbol WRITE CYCLE tWC tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,2) Data Hold Time (3) Write Enable to Output in High-Z Output Active from End-of-Write Write Pulse to Data Delay (4) (1,2) 7014S25 Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 15 0 15 2 12 ____ ____ 25 20 0 20 2 15 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 2528 tbl 09b ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 9 ____ 11 ____ 0 ____ 0 ____ 9 ____ 11 ____ (1,2,3) 0 ____ 0 ____ 40 30 45 35 Write Data Valid to Read Data Delay (4) ____ ____ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”. 7 6.42 IDT7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle(1,2,3,4,5) ADDRESS OE tAW tAS R/W tWZ (4) DATAOUT (3) tWP (5) tWR tOW tHZ (3) (4) tDW DATAIN tDH NOTES: 1. R/W must be HIGH during all address transitions. 2. tWR is measured from R/W going HIGH to the end of write cycle. 3. During this period, the I/O pins are in the output state, and input signals must not be applied. 4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2). 5. If OE is LOW during a R/ W controlled write cycle, the write pulse width must be the larger of tWP or (t WZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 2528 drw 10 Functional Description The IDT7014 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. It lacks the chip enable feature of CMOS Dual Ports, thus it operates in active mode as soon as power is applied. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. The user application should avoid simultaneous write operations to the same memory location. There is no on-chip arbitration circuitry to resolve write priority and partial data from both ports may be written. READ/WRITE conditions are illustrated in Table 1. Truth Table I – Read/Write Control Left or Right Port(1) R/W L H X OE X L H D0-8 DATAIN Function Data written into memory DATAOUT Data in memory output on port Z High-impedance outputs 2528 tbl 10 NOTE: 1. AOL - A11L is not equal to AOR - A11R. 'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance. 8 IDT7014S/L High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank Commercial (0°C to +70°C) Industrial (-40°C to +85°C) I(1) PF J 12 15 20 25 64-pin TQFP (PN64-1) 52-pin PLCC (J52-1) Commercial Only Commercial & Industrial Commercial & Industrial Commercial & Industrial , Speed in nanoseconds S Standard Power 7014 36K (4K x 9-Bit) Dual-Port RAM 2528 drw 11 Datasheet Document History 1/6/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Added Industrial Temperature Ranges and deleted corresponding notes Replaced IDT logo Page 1 Made corrections to drawing Changed ±200mV to 0mV in notes Page 6 made changes to drawings 6/3/99: 3/10/00: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 6.42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.