IDT7054L25PRF

HIGH-SPEED 4K x 8 FourPortTM STATIC RAM .eatures High-speed access – Commercial: 20/25/35ns (max.) – Industrial: 25ns (max.) – Military: 25/35ns (max.) Low-power operation – IDT7054S Active: 750mW (typ.) Standby: 7.5mW (typ.) – IDT7054L Active: 750mW (typ.) Standby: 1.5mW (typ.) True FourPort memory cells which allow simultaneous access of the same memory locations Fully asynchronous operation from each of the four ports: P1, P2, P3, and P4 x x IDT7054S/L x x TTL-compatible; single 5V (±10%) power supply Available in 128 pin Thin Quad Flatpack and 108 pin PGA packages Industrial temperature range (–40°C to +85°C) is available for selected speeds x Description The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7054 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to x x .unctional Block Diagram R/WP1 CEP1 OEP1 R/WP4 CEP4 OEP4 I/O0P1-I/O7P1 COLUMN I/O COLUMN I/O I/O0P4-I/O7P4 A0P1 - A11P1 PORT 1 ADDRESS DECODE LOGIC PORT 2 ADDRESS DECODE LOGIC MEMORY ARRAY PORT 4 ADDRESS DECODE LOGIC PORT 3 ADDRESS DECODE LOGIC A0P4 - A11P4 A0P2 - A11P2 A0P3 - A11P3 I/O0P2-I/O7P2 OEP2 CEP2 COLUMN I/O COLUMN I/O I/O0P3-I/O7P3 OEP3 CEP3 R/WP2 R/WP3 3241 drw 01 NOVEMBER 2001 1 ©2001 Integrated Device Technology, Inc. DSC 3241/11 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges externally arbitrated or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT7054 provides four independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using IDT’s CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. Low-power (L) versions offer battery backup data retention capability, with each port typically consuming 50µW from a 2V battery. The IDT7054 is packaged in a ceramic 108-pin Pin Grid Array (PGA) and a 128-pin Thin Quad Flatpack (TQFP). The military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Pin Configurations(1,2,3) 11/14/01 81 80 77 74 72 69 68 65 63 60 57 54 R/W P2 84 A11 P2 83 78 A7 P2 76 A5 P2 73 A3 P2 70 A0 P2 67 A0 P3 64 A3 P3 61 A5 P3 59 A7 P3 56 A11 P3 53 R/W P3 NC 50 12 NC 87 86 OE P2 82 A8 P2 79 A10 P2 75 A4 P2 71 A1 P2 66 A1 P3 62 A4 P3 A6 P3 A10 P3 58 55 A8 P3 51 OE P3 A1 P4 49 47 11 A2 P1 90 88 A1 P1 85 CE P2 A0 P1 89 A9 P2 A6 P2 A2 P2 A2 P3 A9 P3 52 CE P3 A0 P4 48 46 A2 P4 A5 P4 45 10 A5 P1 92 91 A3 P1 A6 P1 94 93 A3 P4 A6 P4 43 42 09 A10 P1 95 A4 P1 VCC 98 A4 P4 IDT7054G G108-1(4) 108-Pin PGA Top View(5) 44 A10 P4 A8 P4 41 08 A8 P1 96 97 A7 P1 A11 P1 100 GND 39 40 A7 P4 A11 P4 37 38 07 A9 P1 99 CE CE P1 102 P4 35 A9 P4 R/W P4 36 06 R/W P1 101 OE P1 103 I/O0 P1 106 GND 31 OE 05 P4 34 NC 104 I/O1 P1 105 1 GND 4 8 12 17 21 25 GND 28 I/O7 P4 32 33 NC 04 I/O2 P1 107 2 I/O3 P1 5 I/O6 P1 7 VCC GND 10 VCC 13 16 VCC GND 19 VCC 22 24 I/O2 P4 29 I/O5 P4 I/O3 P4 26 I/O6 P4 30 03 I/O4 P1 108 3 I/O7 P1 6 I/O0 P2 9 I/O2 P2 I/O3 P2 D I/O4 P2 11 I/O6 P2 14 15 I/O1 P3 I/O0 P3 G I/O3 P3 18 I/O5 P3 20 23 I/O7 P3 I/O6 P3 K I/O4 P4 27 02 I/O5 P1 A INDEX NC B I/O1 P2 C I/O5 P2 E I/O7 P2 F I/O2 P3 H I/O4 P3 J I/O0 P4 L I/O1 P4 M 01 3241 drw 02 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.21 in x 1.21 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations 11/14/01 (1,2,3) (con't.) INDEX 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 R/WP2 A11P2 A9P2 A8P2 A7P2 A10P2 A6P2 A5P2 A4P2 A3P2 A2P2 A1P2 A0P2 A0P3 A1P3 A2P3 A3P3 A4P3 A5P3 A6P3 A10P3 A7P3 A8P3 A9P3 A11P3 OEP3 CEP2 OEP2 N/C N/C N/C N/C N/C A0P1 A1P1 A2P1 A3P1 A4P1 A5P1 A6P1 A10P1 VCC A7P1 A8P1 A9P1 A11P1 CEP1 R/WP1 OEP1 N/C N/C N/C N/C N/C N/C I/O0P1 I/O1P1 I/O2P1 I/O3P1 GND I/O4P1 I/O5P1 I/O6P1 I/O7P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IDT7054PRF PK128-1(4) 128-Pin TQFP Top View(5) 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 CEP3 R/WP3 N/C N/C N/C N/C N/C A0P4 A1P4 A2P4 A3P4 A4P4 A5P4 A6P4 A10P4 GND A7P4 A8P4 A9P4 A11P4 CEP4 R/WP4 OEP4 N/C N/C N/C N/C N/C GND N/C I/O7P4 I/O6P4 I/O5P4 GND I/O4P4 I/O3P4 I/O2P4 I/O1P4 . N/C VCC I/O0P2 I/O1P2 I/O2P2 GND I/O3P2 I/O4P2 I/O5P2 VCC I/O6P2 I/O7P2 N/C I/00P3 I/O1P3 VCC I/O2P3 I/O3P3 I/O4P3 GND I/O5P3 I/O6P3 I/O7P3 N/C VCC I/O0P4 3241 drw 03 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 3 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations Symbol A 0 P1 - A11 P1 A 0 P2 - A11 P2 A 0 P3 - A11 P3 A 0 P4 - A11 P4 I/O0 P1 - I/O7 P1 I/O0 P2 - I/O7 P2 I/O0 P3 - I/O7 P3 I/O0 P4 - I/O7 P4 R/ W P1 R/ W P2 R/ W P3 R/ W P4 GND CE P1 CE P2 CE P3 CE P4 OE P1 OE P2 OE P3 OE P4 V CC (1,2) Capacitance(1) Pin Name (TA = +25°C, f = 1.0MHz) TQ.P ONLY Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 0V VOUT = 0V Max. 9 10 Unit pF pF 3241 tbl 03 Address Line s - Port 1 Address Line s - Port 2 Address Line s - Port 3 Address Line s - Port 4 Data I/O - Port 1 Data I/O - Port 2 Data I/O - Port 3 Data I/O - Port 4 Read/Write - Port 1 Read/Write - Port 2 Read/Write - Port 3 Read/Write - Port 4 Ground Chip Enab le - Port 1 Chip Enab le - Port 2 Chip Enab le - Port 3 Chip Enab le - Port 4 Output Enab le - Port 1 Output Enab le - Port 2 Output Enab le - Port 3 Output Enab le - Port 4 Power 3241 tbl 01 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. Maximum Operating Temperature and Supply Voltage(1) Grade Military Commercial Industrial Ambient Temperature -55°C to +125°C 0°C to +70 °C -40°C to +85°C GND 0V 0V 0V Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10% 3241 tbl 04 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. TBIAS TSTG -55 to +125 -65 to +150 50 -65 to +135 -65 to +150 50 o C C o Recommended DC Operating Conditions Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (1) IOUT Unit V V (2) mA 3241 tbl 05 Typ. 5.0 0 ____ Max. 5.5 0 6.0 V V 3241 tbl 02 ____ 0.8 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of V TERM > VCC + 10%. NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 6.42 4 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5) (V CC = 5.0V ± 10%) 7054X20 Com'l Only Symbol ICC1 7054X25 Com'l, Ind & Military TYP. (2) 150 150 150 150 225 195 225 195 60 50 60 50 1.5 0.3 1.5 0.3 Max. 300 250 360 300 350 305 400 340 85 70 115 85 15 1.5 30 4.5 7054X35 Com'l & Military TYP.(2) 150 150 150 150 210 180 210 180 40 35 40 35 1.5 0.3 1.5 0.3 Max. 300 250 360 300 335 290 395 330 75 60 110 80 15 1.5 30 4.5 Unit mA mA mA mA mA mA mA mA 3241 tbl 06 Parameter Operating Power Supply Current (All Ports Active) Condition CE = VIL Outputs Disabled f = 0(3) Version COM'L. MIL. & IND. COM'L. MIL. & IND. COM'L. MIL. & IND. S L S L S L S L S L S L S L S L TYP.(2) 150 150 ____ ____ Max. 300 250 ____ ____ ICC2 Dynamic Operating Current (All Ports Active) CE = VIL Outputs Disabled f = fMAX(4) 240 210 ____ ____ 370 325 ____ ____ ISB Standby Current (All Ports - TTL Level Inputs) CE = VIH f = fMAX(4) 70 60 ____ ____ 95 80 ____ ____ ISB1 Full Standby Current (All Ports - All CMOS Level Inputs) All Ports CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(3) COM'L. MIL. & IND. 1.5 0.3 ____ ____ 15 1.5 ____ ____ NOTES: 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, TA = +25°C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = fMAX , address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7054S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to V CC CE = VIH, VOUT = 0V to V CC IOL = 4mA IOH = -4mA Min. ___ 7054L Max. 10 10 0.4 ___ Min. ___ Max. 5 5 0.4 ___ Unit µA µA V V 2674 tbl 07 ___ ___ ___ ___ 2.4 2.4 NOTE: 1. At Vcc < 2.0V input leakages are undefined. 6.42 5 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2 3241 tbl 08 5V 893Ω DATAOUT 347Ω 30pF DATAOUT 347Ω 5V 893Ω 5pF* 3241 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ , tHZ , tWZ, tOW ) *Including scope and jig Timing Waveform of Read Cycle No. 1, Any Port(1) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID 3241 drw 05 NOTE: 1. R/ W = VIH, OE = VIL, and CE = VIL. 6.42 6 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) 7054X20 Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) 7054X25 Com'l, Ind & Military Min. Max. 7054X35 Com'l & Military Min. Max. Unit Parameter Min. Max. 20 ____ ____ 25 ____ ____ 35 ____ ____ ns ns ns ns ns ns ns ns ns 3241 tbl 09 20 20 10 ____ 25 25 15 ____ 35 35 25 ____ ____ ____ ____ ____ ____ ____ 0 5 ____ 0 5 ____ 0 5 ____ ____ ____ ____ Output High-Z Time (1,2) Chip Enab le to Power Up Time (2) Chip Disable to Power Down Time (2) 12 ____ 15 ____ 15 ____ 0 ____ 0 ____ 0 ____ 20 25 35 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L). Timing Waveform of Read Cycle No. 2, Any Port(1, 2) tACE CE tAOE OE tLZ DATAOUT tLZ tPU ICC CURRENT ISB NOTES: 1. R/ W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. tHZ tHZ VALID DATA tPD 50% 50% 3241 drw 06 6.42 7 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7054X20 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tWDD tDDD Write Cycle Time Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width (3) 7054X25 Com'l, Ind & Military Min. Max. 7054X35 Com'l & Military Min. Max. Unit Parameter Min. Max. 20 15 15 0 15 0 15 ____ ____ 25 20 20 0 20 0 15 ____ ____ 35 30 30 0 30 0 20 ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 3241 tbl 10 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time Write Enable to Output in High-Z (1,2) (1,2) ____ ____ ____ ____ ____ 15 ____ 15 ____ ____ 15 ____ 0 ____ 0 ____ 0 ____ 12 ____ 15 ____ 15 ____ Output Active from End-of-Write (1,2) Write Pulse to Data Delay (4) Write Data Valid to Read Data Delay (4) 0 ____ 0 ____ 0 ____ 35 30 45 35 55 45 ____ ____ ____ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (t WZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = V IH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. 'X' in part number indicates power rating. 6.42 8 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) tWC ADDRESS tAS (6) OE tAW CE tWP(2) R/W tLZ DATAOUT (4) tWR(3) (7) tHZ tWZ (7) tOW (4) tHZ (7) tDW DATAIN tDH 3241 drw 07 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE tAS R/W tDW DATAIN 3241 drw 08 (6) tEW (2) tWR (3) tDH NOTES: 1. R/W or CE = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 6.42 9 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read(1, 2) tWC ADDR"A" R/W"A" tDW DATAIN"A" VALID tDH MATCH tWP ADDR"B" MATCH tWDD DATA"B" tDDD NOTES: 1. OE = VIL for the reading ports. 2. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port. 3241 drw 09 VALID .unctional Description The IDT7054 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table. Table I – Read/Write Control Any Port(1) R/W X X L H X CE H H L L X OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Deselected: Power-Down CEP1=CEP2=CEP3=CEP4 =VIH Power Down Mode ISB o r ISB1 Data on port written into memory (2) Data in memory output on port Outputs Disabled 3241 tbl 11 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance 2. For valid write operation, no more than one port can write to the same address location at the same time. 610 .42 IDT7054S/L High-Speed 4K x 8 FourPort™ Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) B G PRF 20 25 35 L S 7054 NOTE: 1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office. Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML 108-Pin Pin Grid Array (G108-1) 128-Pin Thin Quad Plastic Flatpack (PK128-1) Commercial Only Speed in Commercial, Industrial & Military nanoseconds Commercial & Military Low Power Standard Power 32K (4K x 8) FourPort RAM 3241 drw 10 Datasheet Document History 1/18/99: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Removed Preliminary Replaced IDT logo Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Page 2 & 3 Added date revision for pin configurations Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to 25ns ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 6 Changed 5ns to 3ns in AC Test Conditions table Page 1 & 11 Replace TM logo with ® logo 6/4/99: 9/1/99: 11/10/99: 5/23/00: 10/22/01: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 611 .42