IDT707288L15PF

HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS x IDT707288S/L Features 64K x 16 Bank-Switchable Dual-Ported SRAM Architecture – Four independent 16K x 16 banks – 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15ns User-controlled input pins included for bank selects Independent port controls with asynchronous address & data busses Four 16-bit mailboxes available to each port for interx x x x x x x x processor communications; interrupt option Interrupt flags with programmable masking Dual Chip Enables allow for depth expansion without external logic UB and LB are available for x8 or x16 bus matching TTL-compatible, single 5V (±10%) power supply Available in a 100-pin Thin Quad Flatpack (14mm x 14mm) x Functional Block Diagram MUX R/WL CE0L CE1L UBL LBL OEL 16Kx16 MEMORY ARRAY (BANK 0) MUX I/O8L-15L I/O0L-7L I/O CONTROL MUX 16Kx16 MEMORY ARRAY (BANK 1) MUX I/O CONTROL I/O8R-15R I/O0R-7R R/WR CE0R CE1R UBR LBR OER CONTROL LOGIC CONTROL LOGIC A13L A0L(1) ADDRESS DECODE ADDRESS DECODE A13R A0R(1) BA1L BA0L BANK DECODE MUX 16Kx16 MEMORY ARRAY (BANK 3) MUX BANK DECODE BA1R BA0R BKSEL3(2) BKSEL0(2) BANK SELECT A5L(1) A0L(1) LBL/UBL OEL R/WL CEL MAILBOX INTERRUPT LOGIC A5R(1) A0R(1) LBR/UBR OER R/WR CER MBSELL INTL MBSELR INTR 3592 drw 01 NOTES: 1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs. 2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details. MAY 2000 1 ©2000 Integrated Device Technology, Inc. DSC 3592/7 IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow interprocessor communication. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288 offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP). IV). Once a bank is assigned to a particular port, the port has full access to read and write within that bank. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The IDT707288 provides mailboxes to allow inter-processor communication. Each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. These mailboxes are external to the common SRAM array, and are accessed by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. The interrupted port can clear the interrupt by reading the upper byte. This read will not alter the contents of the mailbox. If desired, any source of interrupt can be independently masked via software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. The information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. Truth Table V gives a detailed explanation of the use of these registers. Functionality The IDT707288 is a high-speed asynchronous 64K x 16 BankSwitchable Dual-Ported SRAM, organized in four 16K x 16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled Bank Select input pins, and each of these pins is associated with a specific bank within the memory array. Access to a specific bank is gained by placing the associated Bank Select pin in the appropriate state: VIH assigns the bank to the left port, and VIL assigns the bank to the right port (See Truth Table 6.42 2 IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges INDEX A6L A7L A8L A9L A10L A11L A13L NC BKSEL0 LBL UBL CE0L CE1L MBSELL Vcc R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 A5L A4L A3L A2L A1L A0L BA1L BA0L A12L NC BKSEL1 INTL GND GND INTR BKSEL2 A12R BA0R BA1R A0R A1R A2R A3R A4R A5R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Configurations (1,2,3) IDT707288PF PN100-1(4) 100-Pin TQFP Top View(5) 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6R A7R A8R A9R A10R A11R A13R NC BKSEL3 LBR UBR CE0R CE1R MBSELR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R 3592 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC , Pin Names A0 - A13(1,6) BA0 - BA1(1) MBSEL(1) BKSEL0-3 R/W OE (1) (2) Address Inputs Bank Address Inputs Mailbox Access Control Gate Bank Select Inputs Read/Write Enable Output Enable Chip Enables I/O Byte Enables (1) CE0, C E1(1) UB, LB (1) (1) I/O0 - I/O15 INT (1) Bidirectional Data Input/Output Interrupt Flag (Output)(3) +5VPower Ground 3592 tbl 01 VCC(4) GND (5) NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table IV for more details. When changing the bank assignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not being reallocted. 3. Generated upon mailbox access. 4. All Vcc pins must be connected to power supply. 5. All GND pins must be connected to ground supply. 6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs (A6-A13 are ignored). 3 6.42 IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I – Chip CE CE0 VIL L < 0.2V VIH H X >VCC -0.2V X Enable(1,2,3,4) CE1 VIH >VCC -0.2V X VIL X