IDT709079S9PFI

HIGH-SPEED 32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Features: ◆ ◆ PRELIMINARY IDT709079S/L ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9/12/15ns (max.) – Industrial: 12ns (max.) Low-power operation – IDT709079S Active: 950mW (typ.) Standby: 5mW (typ.) – IDT709079L Active: 950mW (typ.) Standby: 1mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPER pin Counter enable and reset features ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 66MHz operation in the Pipelined output mode TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100 pin Thin Quad Flatpack (TQFP) Functional Block Diagram R/WL OEL CE0L CE1L R/WR OER CE0R CE1R 1 0 0/1 1 0 0/1 FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER I/O0L - I/O7L I/O Control I/O Control I/O0R - I/O7R A14L A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A14R A0R CLKR ADSR CNTENR CNTRSTR 3495 drw 01 DECEMBER 2002 1 ©2002 Integrated Device Technology, Inc. DSC 3495/8 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges The IDT709079 is a high-speed 32K x 8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Description: With an input data register, the IDT709079 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 950mW of power. Pin Configurations(1,2,3) NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 3 73 4 72 1 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 71 70 69 68 67 03/18/02 Index NC NC A7L A8L A9L A10L A11L A12L A13L A14L NC NC VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC IDT709079PF PN100-1(4) 100-PIN TQFP TOP VIEW(5) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R NC NC GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC 3495 drw 02 , GND NC I/O7L I/O6L I/O5L I/O4L I/O3L NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. I/O2L GND I/OIL I/O0L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC 6.42 2 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A14L I/O0L - I/O7L CLKL ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A14R I/O0R - I/O7R CLKR ADSR CNTENR CNTRSTR FT/PIPER VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power Ground 3495 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE X X X L H CLK ↑ ↑ ↑ ↑ X CE0 H X L L L CE1 X L H H H R/ W X X L H X I/O0-7 High-Z High-Z DIN DOUT High-Z Mode Deselected Deselected Write Read Outputs Disabled 3495 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table II—Address Counter Control(1,2) Address X An An X Previous Address X X Ap Ap Addr Used 0 An Ap Ap + 1 CLK ↑ ↑ ↑ ↑ ADS X L(4) H H CNTEN X X H L (5) CNTRST L (4) I/O(3) DI/O(0) DI/O (n) DI/O(p) DI/O(p+1) Counter Reset to Address 0 External Address Used MODE H H H External Address Blocked—Counter disabled (Ap reused) Counter Enabled—Internal Address generation 3495 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE 1. 3 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature(1) 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10% 3495 tbl 04 Recommended DC Operating Conditions Symbol VCC GND VIH V IL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5 (2) Typ. 5.0 0 ____ ____ Max. 5.5 0 6.0 (1) Unit V V V V 3495 tbl 05 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 0.8 NOTES: 1. V TERM must not exceed VCC +10%. 2. VIL > -1.5V for pulse width less than 10ns. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT(3) Parameter(1) Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF 3495 tbl 07 TBIAS TSTG IOUT -55 to +125 -65 to +150 50 o C C o NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. mA 3495 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. 6.42 4 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Teamperature and Supply Voltage Range (VCC = 5.0V ± 10%) 709079S/L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) Test Conditions VCC = 5.5V, VIN = 0V to V CC CE0 = VIH o r CE1 = VIL, VOUT = 0V to VCC IOL = + 4mA IOH = -4mA Min. ___ ___ ___ Max. 10 10 0.4 ___ Unit µA µA V V 3495 tbl 08 Output Leakage Current Output Low Voltage Output High Voltage 2.4 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%) 709079X9 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CEL and C ER = VIH, Outputs Disabled f = fMAX(1) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(4) 210 210 ____ ____ 709079X12 Com'l & Ind Typ. (4) 200 200 200 200 50 50 50 50 130 130 130 130 1.0 0.2 1.0 0.2 120 120 120 120 Max. 345 305 380 340 110 90 125 105 230 200 245 215 15 5 15 5 205 185 220 200 709079X15 Com'l Only Typ.(4) 190 190 ____ ____ Max. 390 350 ____ ____ Max. 325 285 ____ ____ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and C ER = VIH f = fMAX(1) 50 50 ____ ____ 135 115 ____ ____ 50 50 ____ ____ 110 90 ____ ____ mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Disabled, f=fMAX(1) Both Ports C ER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(1) 140 140 ____ ____ 270 240 ____ ____ 120 120 ____ ____ 220 190 ____ ____ mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) 1.0 0.2 ____ ____ 15 5 ____ ____ 1.0 0.2 ____ ____ 15 5 ____ ____ mA ISB4 Full Standby Current (One Port CMOS Level Inputs) 130 130 ____ ____ 245 225 ____ ____ 110 110 ____ ____ 195 175 ____ ____ mA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ). 5. CEX = V IL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6. 'X' in part number indicates power rating (S or L). 3495 tbl 09 5 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3 3495 tbl 10 5V 893Ω DATAOUT 347Ω 30pF DATAOUT 347Ω 5V 893Ω 5pF* 3495 drw 03 3495 drw 04 Figure 1. AC Output Test load. Figure 2. Output Test Load (For tCKLZ, t CKHZ, tOLZ , and tOHZ ). *Including scope and jig. 8 7 6 ∆ tCD1, ∆ tCD2 -10 pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3495 drw 05 (Typical, ns) , Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 6 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C) 709079X9 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Parameter Clock Cycle Time (Flow-Through)(2) Clock Cycle Time (Pipelined) (2) (2) 709079X12 Com'l & Ind Min. 30 20 12 12 8 8 ____ ____ 709079X15 Com'l Only Min. 35 25 12 12 10 10 ____ ____ Min. 25 15 12 12 6 6 ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z (2) (2) (2) 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 4 1 4 1 4 1 4 1 4 1 4 1 4 1 ____ 12 ____ 12 ____ 15 ____ (1) (1) (2) 2 1 ____ ____ 2 1 ____ ____ 2 1 ____ ____ Output Enable to Output High-Z 7 20 9 ____ 7 25 12 ____ 7 30 15 ____ Clock to Data Valid (Flow-Through) Clock to Data Valid (Pipelined)(2) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z (1) 2 2 2 2 2 2 2 2 2 9 ____ 9 ____ 9 ____ (1) Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time ____ ____ 40 15 ____ ____ 40 15 ____ ____ 50 20 ns ns 3495 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either port. The Right Port uses the Pipelined t CYC2 and tCD2 when FT/PIPE"X" = VIH and the Flow-Through parameters (t CYC1, tCD1) when FT/PIPE"X" = VIL. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE"X". FT/PIPE"X" should be treated as a DC signal, i.e. steady state during operation. 4. 'X' in part number indicates power rating (S or L). 7 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output on Right Port (FT/PIPE"X" = VIL)(3) tCYC1 tCH1 CLK CE0 tSC CE1 tHC tSC (4) tCL1 tHC R/W tSW tSA tHW tHA An + 1 tCD1 tDC Qn tCKLZ (1) Qn + 1 tOHZ (1) ADDRESS (5) An An + 2 An + 3 tCKHZ (1) Qn + 2 tOLZ (1) DATAOUT tDC OE (2) tOE 3495 drw 06 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,6) tCYC2 tCH2 CLK CE0 tSC CE1 tHC tSC (4) tCL2 tHC R/W tSW tSA tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ (1) An + 2 tDC Qn + 1 tOHZ (1) ADDRESS(5) An An + 3 DATAOUT Qn + 2 tOLZ (1) OE (2) tOE NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. "x" denotes Left or Right port. The diagram is with respect to that port. 3495 drw 07 6.42 8 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tSC CE0(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 Q0 tDC tHA A0 tHC tSC tHC tCD2 Q1 tDC tCKLZ (3) tCYC2 tCL2 A1 A2 A3 A4 A5 A6 tCKHZ (3) tCD2 Q3 tCKHZ (3) tSC CE0(B2) tSC tHC tHC tCD2 DATAOUT(B2) tCKLZ (3) Q2 tCKHZ (3) tCD2 tCKLZ (3) Q4 3495 drw 08 Timing Waveform of a Bank Select Flow-Through Read(6) tCH1 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tCD1 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 D0 tDC tCD1 D1 tDC tCKLZ (1) tCYC1 tCL1 A1 A2 A3 A4 A5 A6 CE0(B1) tHC tCKHZ (1) tCD1 D3 tCKHZ (1) tCD1 D5 tCKLZ (1) tSC CE0(B2) tSC tHC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ D2 (1) tCD1 tCKLZ (1) tCKHZ D4 (1) 3495 drw 08a NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709079 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN , and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE 0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = V IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If t CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If t CCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case. 9 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of a Left Port Write Flow-Through Right Port Read(1,2,3,4) CLK "A" tSW R/W "A" tSA ADDRESS "A" tHA NO MATCH tHW MATCH tSD DATAIN "A" tHD VALID tCCS (5) CLK "B" tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA NO MATCH MATCH tCWDD (5) DATAOUT "B" tDC VALID tCD1 VALID tDC 3495 drw 09 NOTES: 1. OE and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN , and CNTRST = VIH. 2. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + t CD1. tCWDD does not apply in this case. 6.42 10 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC CE1 tSW tHW R/W tSW tHW tHC ADDRESS (4) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (2) tCD2 Qn READ tCKHZ (1) tCKLZ(1) tCD2 Qn + 3 DATAOUT NOP (5) WRITE READ 3495 drw 10 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCYC2 tCH2 CLK CE0 tSC CE1 tSW tHW R/W tSW tHW tHC tCL2 ADDRESS DATAIN (4) An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 (2) tCD2 Qn tOHZ(1) Dn + 2 Dn + 3 tCKLZ(1) tCD2 Qn + 4 DATAOUT OE READ WRITE READ 3495 drw 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE 0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 11 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 CLK tCYC1 tCL1 CE0 tSC CE1 tSW tHW R/W tSW tHW tHC ADDRESS (4) tSA DATAIN (2) An tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ(1) (5) NOP tCD1 Qn + 3 tCKLZ WRITE (1) tCD1 DATAOUT tDC READ 3495 drw 12 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSW tHW R/W tSW tHW ADDRESS (4) tSA DATAIN (2) An tHA An +1 An + 2 tSD tHD Dn + 2 An + 3 An + 4 An + 5 Dn + 3 tCD1 Qn tDC tOE tCD1 (1) tCD1 Qn + 4 tDC DATAOUT tOHZ (1) OE READ WRITE tCKLZ READ 3495 drw 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 12 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An tSAD tHAD ADS tSAD tHAD CNTEN tCD2 DATAOUT Qx - 1(2) Qx tDC READ EXTERNAL ADDRESS READ WITH COUNTER Qn tSCN tHCN Qn + 1 Qn + 2(2) Qn + 3 COUNTER HOLD READ WITH COUNTER 3495 drw 14 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 3495 drw 15 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE 0 and OE = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 13 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2 INTERNAL(3) ADDRESS tSAD tHAD ADS An(7) An + 1 An + 2 An + 3 An + 4 CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 3495 drw 16 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCH2 CLK tSA tHA (4) tCYC2 tCL2 ADDRESS INTERNAL(3) ADDRESS R/W ADS tSAD tHAD CNTEN tSCN tHCN tSRST tHRST CNTRST DATAIN (5) An Ax (6) tSW tHW An + 1 An + 2 0 1 An An + 1 tSD tHD D0 Q0 Q1 READ ADDRESS n READ ADDRESS n+1 Qn DATAOUT COUNTER RESET (6) WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 NOTES: 3495 drw 17 1. CE0 and R/W = VIL; CE1 and CNTRST = VIH. CE0 = VIL; CE1 = VIH. 2. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6.42 14 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Functional Description The IDT709079 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the counter registers for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT709079's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. Depth and Width Expansion The IDT709079 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The 709079 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 16-bit or wider applications. A15 IDT709079 CE0 CE1 VCC IDT709079 CE0 CE1 VCC Control Inputs Control Inputs IDT709079 CE1 CE0 IDT709079 CE1 CE0 CNTRST CLK ADS CNTEN R/W LB, UB OE Control Inputs Control Inputs 3495 drw 18 Figure 4. Depth and Width Expansion with IDT709079 15 6.42 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF 100-pin TQFP (PN100-1) 9 12 15 S L Commercial Only Commercial & Industrial Commercial Only Standard Power Low Power Speed in nanoseconds , 709079 256K (32K x 8-Bit) Synchronous Dual-Port RAM 3495 drw 19 NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Preliminary Datasheet: Definition "PRELIMINARY" datasheets contain descriptions for products that are in early release. Datasheet Document History 1/12/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 14 Added Depth & Width section Changed drawing format Page 3 Deleted note 6 for Table II Combined Pipelined 70V9079 family and Flow-through 70V907 family offerings into one data sheet Page 2 Added date revision to pin configurations Page 3 Changed information in Truth Table II Page 4 Increased storage temperature parameter, clarified TA parameter Page 5 Changed DC Electrical parameters–changed wording from "Open" to "Disabled" Continued on page 17 6/7/99: 12/08/02: 6.42 16 IDT709079S/L High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Datasheet Document History (cont'd) 12/08/02: Page 4, 5 & 7 Removed industrial temp footnote from all tables Page 5 & 7 Added 12ns industrial temp to DC & AC Electrical Characteristics Page 7, 8, 11 & 12 Changed ±200mV in waveform notes to 0mV Page 16 Added 12ns industrial temp and industrial temp offering footnote to ordering information Page 1 & 17 Replaced TM logo with ® logo CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 17 6.42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.