IDT7099S15J

HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM Integrated Device Technology, Inc. IDT7099S FEATURES: • High-speed clock-to-data output times — Military: 20/25/30ns (max.) — Commercial: 15/20/25ns (max.) • Low-power operation — IDT7099S Active: 900 mW (typ.) Standby: 50 mW (typ.) • Architecture based on Dual-Port RAM cells — Allows full simultaneous access from both ports — Independent bit/byte Read and Write inputs for control functions • Synchronous operation — 4ns setup to clock, 1ns hold on all control, data, and address inputs — Data input, address, and control registers — Fast 15ns clock to data out — 20ns cycle times, 50MHz operation • Clock enable feature • Guaranteed data output hold times • Available in 68-pin PGA, 68-pin PLCC, and 80-pin TQFP • Military product compliant to MIL-STD-883, Class B • Industrial temperature range (–40°C to +85°C) is available, tested to military electrical specifications DESCRIPTION: The IDT7099 is a high-speed 4K x 9 bit synchronous DualPort RAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach allow systems to be designed with very short realized cycle times. With an input data register, this device has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts. Changing data direction from reading to writing normally requires one dead cycle. These Dual-Ports typically operate on only 900mW of power at maximum high-speed clock-to-data output times as fast as 15ns. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT7099 is packaged in a 68-pin PGA, 68-pin PLCC, and a 80-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM REGISTER REGISTER I/O8L I/O0-7L WRITE LOGIC SENSE AMPS MEMOR MEMORY Y ARRAY ARRAY DECODER DECODER WRITE LOGIC SENSE AMPS I/O8R I/O0-7R BIT OEL BYTE OEL CLKL REG en REG en BIT OER BYTE OER CLKR CLKEN CLKENR Write Control Logic REG A0L-A11L A0R-A11R Write Control Logic BIT R/ REG WL BYTE R/WL BIT R/ WR BYTE R/WR CER 3007 drw 01 CEL The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391. OCTOBER 1996 DSC-3007/3 6.23 1 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS (1,2) A0R A1R A2R A3R A4R A5R A6R 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A5L A4L A3L A2L A1L A0L INDEX 9 8 7 6 5 4 3 CLKL CLKR 2 1 A6L A7L A8L A9L A10L A11L BYTE OE L BIT OEL VCC BYTE R/ WL BIT R/ WL N/C CE L 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 68 67 66 65 64 63 62 61 60 CLKEN R CLKENL IDT7099 J68-1 68-Pin PLCC Top View (3) A7R A8R A9R A10R A11R BYTE OER BIT OER GND GND BYTE R/ WR BIT R/ WR N/C CE R GND I/O8L I/O7L I/O6L GND I/O8R I/O7R I/O6R 3007 drw 03 A A 53 0R 1R 51 50 N/C I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R 48 46 44 42 40 38 36 A5L 52 A4L 49 A2L 47 A0L 45 CLKL 43 CLKENR 41 A1R 39 A3R 37 A5R 35 34 A7L 55 54 A6L A3L A1L CLKENL CLKR A0R A2R A4R A6R 32 33 A7R A9L 57 56 A8L A9R 30 A8R 31 A11L 59 58 A10L A11R 28 A10R 29 OEL 61 BIT BYTE OEL 60 IDT7099 G68-1 68-Pin PGA Top View (3) OER 26 BIT BYTE OER 27 BYTE R/ L W VCC 62 GND 24 GND 25 63 NC 65 BIT R/ L W BIT R/ R W BYTE R/ R W 64 22 23 GND 67 66 CEL I/O8L 1 3 5 7 9 11 13 15 CER 20 21 NC I/O7L 68 I/O8R 18 GND 19 I/O6L 2 NC 4 VCC 6 I/O3L 8 I/O1L GND 10 I/O0R 12 I/O2R 14 VCC 16 I/O6R 17 I/O7R I/O5L INDEX A B I/O4L C I/O2L D I/O0L E GND F I/O1R G I/O3R H I/O4R J I/O5R K L 3007 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. This text does not indicate orientation of the actual part-marking. 6.23 2 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS (CONT'D) (1,2) N/C N/C A5L A4L A3L A2L A1L A0L CLKL CLKR Reference CLKENL CLKEN R N/C A6L A7L A8L A9L A10L A11L N/C BYTE OE L BIT OE L VCC BYTE R/ W L BIT R/ WL N/C CE L 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 A0R A1R A2R A3R A4R A5R A6R N/C 53 52 51 50 49 48 47 46 45 44 43 42 41 IDT7099 PN80-1 80-Pin TQFP Top View (3) N/C A7R A8R A9R A10R A11R N/C BYTE OE R BIT OE R GND GND BYTE R/ W R BIT R/ W R N/C CE R GND I/O 8L I/O 7L I/O 6L N/C GND I/O 8R I/O 7R I/O 6R N/C 3007 drw 04 NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. This text does not indicate the orientaion of the actual part-marking. N/C N/C I/O5L VCC I/O 4L I/O 3L I/O2L I/O1L I/O 0L GND GND I/O 0R I/O 1R I/O2R I/O3R VCC I/O 4R I/O5R N/C N/C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Military Commercial Ambient Temperature –55°C to +125°C 0°C to +70°C GND 0V 0V VCC 5.0V ± 10% 5.0V ± 10% 3007 tbl 02 ABSOLUTE MAXIMUM RATINGS Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Terminal Voltage Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial (1) Military Unit V –0.5 to +7.0 –0.5 to +7.0 RECOMMENDED DC OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 –0.5(1) Typ. 5.0 0 — — Max. 5.5 0 6.0 (2) 0.8 Unit V V V V 3007 tbl 03 VTERM TA (3) –0.5 to VCC –0.5 to VCC 0 to +70 –55 to +125 V °C °C °C mA GND VIH VIL TBIAS TSTG IOUT –55 to +125 –65 to +135 –55 to +125 –65 to +150 50 50 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. CAPACITANCE(1) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Symbol Parameter CIN COUT Input Capacitance Output Capacitance Condition(2) VIN = 3dV VOUT = 3dV Max. Unit 9 10 pF pF NOTES: 3007 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V. 3007 tbl 04 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 6.23 3 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%) IDT7099S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Low Voltage Output High Voltage (1) Test Condition VCC = 5.5V, VIN = 0V to VCC Min. — — — 2.4 Max. 10 10 0.4 — Unit µA µA V V 3007 tbl 05 Output Leakage Current CE = VIH, VOUT = 0V to VCC IOL = 4mA IOL = –4mA NOTE: 1. Input leakages are undefined at VCC ≤ 2.0V. DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) (VCC = 5V ± 10%) IDT7099S15 Com'l. Only Symbol ICC Parameter Test Conditions Version Typ. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. — 180 — 90 — 160 — 10 — 155 Max. — 300 — 140 — 210 — 15 — 200 Typ. 170 170 85 85 150 150 10 10 145 145 Max. 310 290 140 130 210 200 20 — 200 190 Typ. 160 160 80 80 140 140 10 10 135 135 Max. 290 270 130 110 200 180 20 — 190 170 Dynamic CE = VIL Operating Outputs Open Current (Both f = fmAX(1) Ports Active) Standby CEL and Current (Both CER = VIH Ports—TTL f = fmAX(1) Level Inputs) Standby Current (One Port—TTL Level Inputs) Full Standby Current (Both Ports—CMOS Level Inputs) Full Standby Current (One Port—CMOS Level Inputs) IDT7099S20 IDT7099S25 IDT7099S30 Mil Only Typ. 160 — 80 — 140 — 10 — 135 — 170 — 3007 tbl 06 Max. 270 — 110 — 180 — 20 Unit mA ISB1 mA ISB2 CE'A' = VIL and CE'B' = VIH (3) Active Port Outputs Open, f = fmAX(1) Both Ports CER and CEL ≥ VCC – 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0(2) -0.2V(3), VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs Open, f = fmAX(1) mA ISB3 mA ISB4 CE'A' VCC mA NOTES: 1. At f = fmax, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of the 1/tCLK, using "AC TEST CONDITIONS" of input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ). AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1, 2, and 3 3007 tbl 07 6.23 4 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 8 5V 893Ω DATAOUT 347Ω 30pF DATAOUT 347Ω 5pF 5V 893Ω 7 6 ∆tCD (Typical, ns) 5 4 3 2 - 10pF is the I/O capacitance of this device, and 3pF is the AC Test Load Capacitance 3007 drw 05 3007 drw 06 Figure 1. AC Output Test load. Figure 2. Output Test Load (For tCLZ, tCHZ, tOLZ, and tOHZ). Including scope and jig. 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3007 drw 07 Figure 3. Typical Output Derating (Lumped Capacitive Load). AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGE — (READ AND WRITE CYCLE TIMING) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C) Commercial 7099S15 Symbol tCYC tCH tCL tCD tS tH tDC tCKLZ tCKHZ tOE tOLZ tOHZ tSCK tHCK tCWDD Parameter Clock Cycle Time Clock High Time Clock Low Time Clock High to Output Valid Registered Signal Set-up Time Registered Signal Hold Time Data Output Hold After Clock High Clock High to Output Low-Z(1,2) Clock High to Output High-Z(1,2) Output Enable to Output Valid Output Enable to Output Low-Z (1,2) Military 7099S25 25 10 10 — 6 1 3 2 — — 0 — 6 2 — — — — 25 — — — — 12 12 — 11 — — 45 7099S20 20 8 8 — 5 2 3 2 — — 0 — 5 3 — — — — 20 — — — — 9 10 — 9 — — 35 7099S25 25 10 10 — 6 2 3 2 — — 0 — 6 3 — — — — 25 — — — — 12 12 — 11 — — 45 7099S30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3007 tbl 08 7099S20 20 8 8 — 5 1 3 2 — — 0 — 5 2 — — — — 20 — — — — 9 10 — 9 — — 35 Min. Max. Min. Max. 20 6 6 — 4 1 3 2 — — 0 — 4 2 — — — — 15 — — — — 7 8 — 7 — — 30 Min. Max. Min. Max. Min. Max. Min. Max. 30 12 12 — 7 2 3 2 — — 0 — 7 3 — — — — 30 — — — — 15 15 — 14 — — 55 Output Disable to Output High-Z(1,2) Clock Enable, Disable Set-up Time Clock Enable, Disable Hold Time Write Port Clock High to Read Data Delay Port-to-Port Delay NOTES: 1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 6.23 5 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE, EITHER SIDE tCYC CLK tCH tCL tSCK tHCK tSCK CLKEN tS tH CE BYTE R/ or BIT R/ W W An tCD An + 1 tDC Qn Qn + 1 tOHZ (1) ADDRESS An + 2 An + 3 tCKHZ(1) Qn + 1 tOLZ tOE 3007 drw 08 (1) DATAOUT tCKLZ(1) BYTE OE or BIT OE NOTE: 1. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ (1,2,3) CLK "A" R/ W "A" (4) ADDR "A" MATCH NO MATCH DATAIN "A" VALID CLK "B" R/ W "B" MATCH NO MATCH ADDR "B" tCWDD DATAOUT "B" VALID tCD VALID NOTES: 1. CEL = CER = VIL, CLKENL = CLKENR = VIL 2. OE = VIL for the reading port, port 'B'. 3. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A". 4. R/W'A' was active (VIL) during the previous CLK'A', when enabled the write path. tDC 3007 drw 09 6.23 6 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 1, CE = VIH (2) CE tCYC CLK tCH tCL tCH tCYC tCL CLKEN tS tH CE BYTE R/ or BIT R/ W W An An + 1 An + 2 An + 3 ADDRESS DATAIN (3) Dn + 2 tCD tCKHZ Qn Dn + 3 DATAOUT tCKLZ (3) 3007 drw 10 TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO. 2, CE = VIL(2) CE tCYC CLK tCH tCL tCH tCYC tCL CLKEN tS tH CE BYTE R/ or BIT R/ (1) W W An An + 1 An + 1 (1) ADDRESS An + 2 DATAIN (3) Dn + 1 tCD tCKHZ Qn (1) Dn + 2 DATAOUT tCKLZ (3) 3007 drw 11 NOTES: 1. During dead cycle, if CE = VIL, then invalid data will be written into array. The An+1 must be rewritten on the following cycle. 2. OE low throughout. 3. Transition is measured +/-200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 6.23 7 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION The IDT7099 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent on the low to high transitions of the clock signal allowing the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. The data inputs are gated to control on-chip noise in bussed applications. The user must guarantee that the BYTE R/W and BIT R/W pins are low for at least one clock cycle before any write is attempted. A High on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. The device has separate Bit Write, Byte Write, Bit Enable, and Byte Enable pins to allow for independent control. TRUTH TABLE I – READ/WRITE CONTROL(1) Inputs Synchronous CLK (3) Asynchronous Bit R/W h h l l h h l l l h h h h Byte OE OE X X X X X X L H X L H L H Bit OE OE X X X X L H X X X L L H H Outputs I/O0-7 High-Z DATAIN High-Z DATAIN DATAIN High-Z DATAIN I/O8 High-Z High-Z DATAIN DATAIN High-Z DATAIN DATAIN Mode Deselected, Power Down, Data I/O Disabled Deselected, Power Down, Byte Data Input Enabled Deselected, Power Down, Bit Data Input Enabled Deselected, Power Down, Data Input Enabled Write Byte, Read Bit Write Byte Only Read Byte, Write Bit Write Bit Only Write Byte, Write Bit Read Byte, Read Bit Read Bit Only Read Byte Only Data I/O Disabled 3007 tbl 09 CE h h h h l l l l l l l l l Byte R/W h l h l l l h h l h h h h DATAIN DATAOUT DATAOUT DATAIN DATAOUT DATAOUT High-Z DATAOUT DATAOUT High-Z High-Z High-Z TRUTH TABLE II – CLOCK ENABLE FUNCTION TABLE Inputs Operating Mode Load "1" Load "0" Hold (do nothing) X CLK(3) (1) Register Outputs ADDR H L NC NC DATAOUT H L NC NC Register Inputs CLKEN(2) l l h H ADDR h l X X DATAIN h l X X NOTES: 3007 tbl 10 1. 'H' = High voltage level steady state, 'h' = High voltage level one set-up time prior to the low-to-high clock transition, 'L' = Low voltage level steady state 'l' = Low voltage level one set-up time prior to the Low-to-High clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are low, a write cycle is initiated on the low-to-high transition of the CLK. Termination of a write cycle is done on the next low-to-high transistion of the CLK. 6.23 8 IDT7099S HIGH-SPEED 4K x 9 SYNCHRONOUS DUAL-PORT RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank B J G PF 15 20 25 30 S 7099 Commercial (0°C to +70°C) Military (–55°C to +125°C) Compliant to MIL-STD-883, Class C 68-pin PLCC (J68-1) 68-pin PGA (G68-1) 80-pin TQFP (PN80-1) Commercial Only Speed in nanoseconds Military Only Standard Power 36K (4K x 9-Bit) Synchronous Dual-Port RAM 3007 drw 12 6.23 9