IDT70P24755BYI

VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ PRELIMINARY IDT70P257/247L ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Industrial: 55ns (max.) Low-power operation IDT70P257/247L Active: 27mW (typ.) Standby: 3.6µW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT70P257/247 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ M/S = VDD for BUSY output flag on Master M/S = VSS for BUSY input on Slave Input Read Register Output Drive Register BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 1.8V (±100mV) power supply Available in 100 Ball 0.5mm-pitch BGA Industrial temperature range (-40°C to +85°C) Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O0L-I/O7L BUSYL (2,3) I/O8R-I/O15R I/O Control I/O Control I/O0R-I/O7R BUSYR (2,3) , A12L(1) A0L Address Decoder MEMORY ARRAY Address Decoder A12R(1) A0R CEL OEL R/WL IRR0,IRR1 INPUT READ REGISTER AND OUTPUT DRIVE REGISTER SFEN 13 13 CER OER R/WR ODR 0 - ODR4 CEL OEL R/WL SEML (3) INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR INTR(3) 5684 drw 01 M/S NOTES: 1. A12X is a NC for IDT70P247. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. FEBRUARY 2004 1 DSC-5684/1 ©2004 Integrated Device Technology, Inc. IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Description The IDT70P257/247 is a very low power 8K/4K x 16 Dual-Port Static RAM. The IDT70P257/247 is designed to be used as a stand-alone 128/64K-bit Dual-Port SRAM or as a combination MASTER/SLAVE DualPort SRAM for 32-bit-or-more word systems. Using the IDT MASTER/ SLAVE Dual-Port SRAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 27mW of power. The IDT70P257/247 is packaged in a 100 ball 0.5mm- pitch Ball Grid Array. The package is a 1mm thick and designed to fit in wireless handset applications. Pin Configurations(2,3,4) 70P257/247BY BY-100 02/04/04 100-Ball 0.5mm Pitch BGA Top View(5) A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 A5R B1 A8R B2 A11R B3 UBR B4 Vss B5 SEMR I/O15R I/O12R I/O10R B6 B7 B8 B9 Vss B10 A3R C1 A4R C2 A7R C3 A9R C4 CER C5 R/WR C6 OER C7 VDD C8 I/O9R I/O6R C9 C10 A0R D1 A1R D2 A2R D3 A6R D4 LBR D5 IRR 1 D6 I/O14R I/O11R I/O7R D7 D8 D9 Vss D10 ODR4 ODR2 BUSYR INT R E1 E2 E3 E4 A10R E5 A12R(1) E6 I/O13R I/O8R E7 E8 I/O5R E9 I/O2R E10 Vss F1 M/S F2 ODR3 F3 INTL F4 Vss F5 Vss F6 I/O4R F7 VDD F8 I/O1R F9 Vss F10 SFEN ODR1 BUSYL G1 G2 G3 A1L G4 VDD G5 Vss G6 I/O3R G7 I/O0R I/O15L VDD G8 G9 G10 ODR 0 H1 A 2L H2 A5L H3 A12L(1) H4 OEL H5 I/O3L I/O11L I/O12L I/O14L I/O13L H6 H7 H8 H9 H10 , A0L J1 A4L J2 A9L J3 LB L J4 CEL J5 I/O1L J6 VDD J7 NC J8 NC J9 I/O10L J10 A3L K1 A7L K2 A10L K3 IRR0 K4 VDD K5 Vss K6 I/O4L K7 I/O6L K8 I/O8L K9 I/O9L K10 A 6L A8L A 11L UBL SEML R/W L I/O0L I/O2L I/O5L I/O7L 5684 drw 02b NOTES: 1. A12X is a NC for IDT70P247. 2. All VDD pins must be connected to power supply. 3. All V SS pins must be connected to ground supply. 4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 2 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Pin Names Left Port CEL R/ WL OEL A0L - A12L(1) I/O0L - I/O15L SEML UBL LBL INTL BUSYL CER R/WR OER A 0R - A 12R(1) I/O0R - I/O15R SEMR UBR LBR INTR BUSYR IRR0, IRR1 ODR0 - ODR4 SFEN(2) M/S VDD VSS Right Port Names Chip Enable (Input) Read/Write Enable (Input) Output Enable (Input) Address (Input) Data Input/Output Semaphore Enable (Input) Upper Byte Select (Input) Lower Byte Select (Input) Interrupt Flag (Output) Busy Flag Input Read Register (Input) Output Drive Register (Output) Special Function Enable (Input) Master or Slave Select (Input) Power (1.8V) (Input) Ground (0V) (Input) 5684 tbl 01 NOTE: 1. A12X is a NC for IDT70P247. 2. SFEN is active when either CEL = V IL or CER = VIL. SFEN is inactive when CEL = CER = VIH. Truth Table I: Non-Contention Read/Write Control Inputs(1) CE H X L L L L L L X R/ W X X L L L H H H X OE X X X X X L L L H UB X H L H L L H L X LB X H H L L H L L X SEM H H H H H H H H X I/O8-15 High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z Outputs I/O0-7 High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Mode Deselected: Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled 5684 tbl 02 NOTE: 1. A0L — A12L ≠ A0R — A12R for IDT70P257; A0L — A11L ≠ A0R — A11R for IDT70P247. 6.42 3 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Truth Table II: Semaphore Read/Write Control(1) Inputs CE H X H X L L R/W H H ↑ ↑ X X OE L L X X X X UB X H X H L X LB X H X H X L SEM L L L L L L I/O8-15 DATAOUT DATAOUT DATAIN DATAIN ____ ____ Outputs I/O0-7 DATAOUT DATAOUT DATAIN DATAIN ____ ____ Mode Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed 5684 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0-A2. Absolute Maximum Ratings(1) Symbol VTERM(2) TBIAS(3) TSTG TJN IOUT Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Industrial -0.5 to VDDMAX +0.3V -55 to +125 -65 to +150 +150 20 Unit V o C C C o o mA 5684 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over VTERM = VDD + 0.3V. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. 6.42 4 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Capacitance Symbol CIN COUT (TA = +25°C, f = 1.0MHz) Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 11 Unit pF pF 5684 tbl 07 Maximum Operating Temperature and Supply Voltage(1) Grade Industrial Ambient Temperature -40OC to +85OC GND 0V VDD 1.8V + 100mV 5684 tbl 05 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions Symbol VDD VSS VIH VIL Parameter Supply Voltage(3) Ground Input High Voltage Input Low Voltage Min. 1.7 0 1.2 -0.2 Typ. 1.8 0 ___ Max. 1.9 0 VDD + 0.2 0.4 Unit V V V V 5684 tbl 06 ___ NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VDD + 0.3V. 3. M/S operates at the VDD and VSS voltage levels. 6.42 5 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV) Symbol ILI ILO VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VDD = 1.8V, VIN = 0V to VDD CE = VIH, VOUT = 0V to VDD IOL = +0.1mA IOH = -0.1mA Min. ___ Max. 1 1 0.2 ___ Unit µA µA V V 5684 tbl 08 ___ ___ VDD - 0.2V DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 1.8V ±100mV) 70P257/247 Ind'l Only Symbol IDD ISB1 ISB2 ISB3 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports TTL Level Inputs) Standby Current (One Port TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CE = VIL, Outputs Open f = fMAX(2) CE R and CEL = VIH, SEM = VIH f = fMAX(2) CE "A" = V IL and CE"B" = VIH(4), Active Port Outputs Open f = fMAX(2) Both Ports CEL and CER > VDD - 0.2V, SEML and SEMR > V DD - 0.2V, V IN > VDD - 0.2V or V IN < 0.2V f = fMAX(2), M/ S = V DD o r V SS(4) CE "A" < 0.2V and CE "B" > VDD - 0.2V (4) V IN > V DD - 0.2V or V IN < 0.2V, Active Port Outputs Open f = fMAX(2) Test Condition Version IND'L IND'L IND'L IND'L L L L L Typ. (1) 15 2 8.5 Max. 25 8 14 Unit mA µA mA µA 2 8.5 8 14 ISB4 IND'L L mA NOTES: 1. VDD = 1.8V, TA = +25°C, and are not production tested. IDD DC = 15mA (typ.) 2. At f = fMAX , address and control lines are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. If M/ S = V SS, then f BUSYL = fBUSYR = 0 for full standby mode. 5684 tbl 09 6.42 6 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 1.8V 3ns Max. 0.9V 0.9V Figure 1 5684 tbl 10 1.8V R1 1.8V R1 R2 13500Ω 10800Ω 5684 tbl 10_5 30pF R2 5684 drw 03 Figure 1. AC Output Test Load (5pF for tLZ , tHZ, tWZ, tOW ) Timing of Power-Up Power-Down CE ICC ISB tPU 50% tPD 50 % , 5684 drw 04 6.42 7 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70P257/247 Ind'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time (3) (3) Parameter Min. Max. Unit 55 ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 5684 tbl 11 55 55 55 30 ____ ____ Output Enable Access Time (3) Output Hold from Address Change Output Low-Z Time (1,2,5) (1,2,5) (1,2) (1,2) 5 5 ____ Output High-Z Time 25 ____ Chip Enable to Power Up Time 0 ____ Chip Disable to Power Down Time 55 ____ Semaphore Flag Update Pulse (OE o r SEM) Semaphore Address Access (3) 15 ____ 55 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH, and SEM = VIL. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW . 5. At any given temperature and voltage condition, t HZ is less than tLZ for any given device. 6.42 8 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Waveform of Read Cycles(5) tRC ADDR tAA (4) (4) tACE tAOE OE tABE UB, LB (4) (4) CE R/W tLZ DATAOUT (1) tOH VALID DATA (4) (2) tHZ BUSYOUT tBDD (3,4) , 5684 drw 05 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB , or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 6.42 9 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(4) 70P257/247 Ind'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time (1,2) Data Hold Time (4) (1,2) (3) Parameter Min. Max. Unit 55 45 45 0 40 0 30 ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 5684 tbl 12 25 ____ 0 ____ Write Enable to Output in High-Z Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window 25 ____ ____ ____ (1,2,4) 0 10 10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = V IH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW . 6.42 10 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE CE or SEM (9) tAW CE or SEM (9) tAS (6) R/W tWZ (7) DATAOUT (4) tWP (2) tWR (3) tOW (4) tDW DATAIN tDH , 5684 drw 06 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS CE or SEM (9) tAW UB or LB (9) tAS(6) tEW (2) tWR(3) R/W tDW DATAIN 5684 drw 07 ,, tDH NOTES: 1. R/W or CE or UB & LB must be high during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W going HIGH (or SEM going LOW) to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output Test Load. 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB and LB = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 611 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tWR tAW tEW SEM I/O0 tAS R/W tSWRD OE Write Cycle Read Cycle 5684 drw 08 , tO H VALID ADDRESS tACE tDW DATAIN VALID tWP tDH tSOP DATA OUT VALID(2) tAOE NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O 0-I/O15)equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" MATCH SIDE (2) "B" R/W"B" SEM"B" 5684 drw 09 NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or Both UB & LB = V IH. 2. All timing is the same for left or right port. “A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied there is no guarantee which side will be granted the semaphore flag. 6.42 12 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P257/247 Ind'l Only Symbol BUSY TIMING (M/ S = VDD) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable LOW BUSY Disable Time from Chip Enable HIGH Arbitration Priority Set-up Time BUSY Disable to Valid Data(3) Write Hold After BUSY(5) (2) ____ ____ ____ ____ Parameter Min. Max. Unit 45 45 45 45 ____ ns ns ns ns ns ns ns 5 ____ 40 ____ 35 BUSY TIMING (M/ S = VSS) tWB tWH BUSY Input to Write (4) Write Hold After BUSY(5) 0 35 ____ ____ ns ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ ____ 80 65 ns ns 5684 tbl 13 NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VDD)" or "Timing Waveform of Write With Port-To-Port Delay (M/S = VSS)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 613 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATA OUT "B" tDDD(3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VSS (slave), BUSY is an input. Then for this example BUSY "A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A". 5684 drw 10 (1) tDH VALID MATCH tBDA tBDD VALID , Timing Waveform of Slave Write (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH(1) R/W"B" NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. Busy is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the “slave” version. (2) 5684 drw 11 , 6.42 14 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC BUSY"B" 5684 drw 12 tBDC , Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" tAPS ADDR"B" (2) ADDRESS "N" MATCHING ADDRESS "N" tBAA tBDA , 5684 drw 13 BUSY"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P257/247 Ind'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ ____ ____ Parameter Min. Max. Unit ns ns ns ns 5684 tbl 14 45 45 615 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Waveform of Interrupt Timing(1) tWC ADDR"A" tAS (3) CE"A" INTERRUPT SET ADDRESS (2) tWR (4) R/W"A" tINS INT"B" 5684 drw 14 , (3) tRC ADDR"B" tAS (3) CE"B" INTERRUPT CLEAR ADDRESS (2) OE"B" tINR(3) INT"B" 5684 drw 15 , NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal ( CE or R/W) is de-asserted first. 6.42 16 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Truth Table III — Interrupt Flag(1) Left Port R/WL L X X X CEL L X X L OEL X X X L A12L-A0L 1FFF X X 1FFE (4) Right Port INTL X X L(3) H(2) R/ WR X X L X CER X L L X OER X L X X A12R-A0R(4) X 1FFF 1FFE X INTR L (2) Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 5684 tbl 15 H(3) X X NOTES: 1. Assumes BUSYL = BUSY R = VIH. 2. If BUSY L = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A12X is a NC for IDT70P247, therefore Interrrupt Addresses are FFF and FFE. Truth Table IV — Address BUSY Arbitration Inputs CEL X H X L CER X X H L A0L-A12L A0R-A12R (4) Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 5684 tbl 16 NO MATCH MATCH MATCH MATCH NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70P257/247 are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A0L — A11L and A 0R — A11R for IDT70P247. 617 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D15 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D15 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 5684 tbl 17 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P257/247. 2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O0-I/O15 ). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Truth Table VI — Input Read Register Operation(3) SFEN H L CE L L R/W H H OE L L UB L(1) X LB L(1) L ADDR x0000 - Max x0000 I/O0-I/O1 VALID(1) VALID(2) I/O2-I/O15 VALID(1) X Mode Standard Memory Access IRR Read (3) 5684 tbl 18 NOTES: 1. UB or LB = VIL. If LB = VIL, then I/O0 - I/O 7 are VALID. If UB = VIL, then I/O 8 - I/O15 are VALID. 2. LB must be active (LB = VIL) for these bits to be valid. 3. SFEN = V IL to activate IRR reads. Truth Table VII — Output Drive Register Operation(5) SFEN H L L CE L L L R/ W H L H OE X (1) UB L (2) LB L (2) ADDR x0000 - Max x0001 x0001 I/O0-I/O4 VALID (2) I/O5-I/O15 VALID X X (2) Mode Standard Memory Access ODR Write (4,5) ODR Read (5) 5684 tbl 19 X L X X L L VALID(3) VALID (3) NOTES: 1. Output enable must be low (OE = Vil) during reads for valid data to be output. 2. UB or LB = VIL. If LB = VIL, then I/O0 - I/O 7 are VALID. If UB = V IL, then I/O8 - I/O15 are VALID. 3. LB must be active (LB = VIL) for these bits to be valid. 4. During ODR writes data will also be written to the memory. 5. SFEN = VIL to activate ODR reads and writes. 6.42 18 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Device 1 Device 2 IRR0 IRR1 Input Read Register (ADDRESS x0000) A0L - A12L(1) I/O0L - I/O15L Address & I/O Control A0R - A12R(1) I/O0R - I/O15R Memory Array 5684 drw 16 Figure 3. Input Read Register Device 2 Device 1 Device 4 Device 5 Device 3 ODR0 ODR1 ODR2 ODR3 ODR4 Output Drive Register (ADDRESS x0001) A0L - A12L(1) I/O0L - I/O15L Address & I/O Control A0R - A12R(1) I/O0R - I/O15R Memory Array Figure 4. Output Drive Register NOTE: 1. A12X is a NC for IDT70P247. 5684 drw 17 619 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM DECODER Preliminary Industrial Temperature Range MASTER Dual Port SRAM BUSYL CE BUSYR SLAVE Dual Port SRAM BUSYL CE BUSYR BUSYL MASTER Dual Port SRAM BUSYL CE BUSYR SLAVE Dual Port SRAM BUSYL CE BUSYR BUSYR , 5684 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P257/247 SRAMs. The IDT70P257/247 provides two ports with separate control, address and I/O pins that permit independent access to any location in memory. The IDT70P257/247 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Functional Description The busy outputs on the IDT 70P257/247 SRAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX) (FFE for IDT70P247), where a write is defined as the CE=R/W=VIL per Truth Table III. The left port clears the interrupt by accessing address location 1FFE when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) (FFF for IDT70P247) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (16 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Interrupts Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attemp-ted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. Busy Logic When expanding an IDT70P257/247 SRAM array in width while using busy logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70P257/247 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = VDD), and the BUSY pin is an input if the part used as a slave (M/S pin = VSS) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. The Input Read Register (IRR) of the IDT70P257/247 captures the status of two external binary input devices connected to the Input Read pins (e.g. DIP switches). The contents of the IRR are read as a standard memory access to address x0000 from either port and the data is output via the standard I/Os (Truth Table VI). During Input Register reads I/O0 - I/O1 are valid bits and I/O2 - I/O15 are "Dont' Care". Writes to address x0000 are not allowed from either port. When SFEN = VIL, the IRR is active and address x0000 is not available for standard memory operations. When SFEN = VIH, the IRR is inactive and address x0000 can be used as part of the main memory. The IRR supports inputs up to 3.5V (VIL < 0.4V, VIH > 1.4V). Refer to Figure 3 and Truth Table VI for Input Read Register operation. Width Expansion with BUSY Logic Master/Slave Arrays Input Read Register 6.42 20 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range The Output Drive Register (ODR) of the IDT70P257/247 determines the state of up to five external binary-state devices by providing a path to VSS for the external circuit. The five external devices supported by the ODR can operate at different voltages (1.5V < VSUPPLY < 3.5V), but the combined current of the devices must not exceed 40 mA (8mA IMAX for each external device). The status of the ODR bits is set using standard write accesses from either port to address x0001with a “1” corresponding to “on“ and a “0” corresponding to “off”. The status of the ODR bits can also be read (without changing the status of the bits) via a standard read to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for standard memory operations. When SFEN = VIH, the ODR is inactive and address x0001 can be used as part of the main memory. During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 I/O15 are "Don't Care". Refer to Figure 4 and Truth Table VII for Output Drive Register operation. Output Drive Register The IDT70P257/247 is an extremely fast Dual-Port 8K/4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are LOW. Systems which can best use the IDT70P257/247 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70P257/247's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70P257/247 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. Semaphores The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active HIGH. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70P257/247 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the How the Semaphore Flags Work 621 .42 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM Preliminary Industrial Temperature Range subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ SEMAPHORE READ 5684 drw 19 , Figure 4. IDT70P257/247 Semaphore Logic Perhaps the simplest application of semaphores is their application as resource markers for the IDT70P257/247’s Dual-Port SRAM. Say the 8K/ 4K x 16 SRAM was to be divided into two 4K/2K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K/2K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would Using Semaphores—Some Examples assume control of the lower 4K/2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K/2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K/2K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned SRAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. 6.42 22 IDT70P257/247L Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM P reliminary Industrial Temperature Range Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Industrial (-40°C to +85°C) I BY 100 Ball 0.5mm-pitch BGA(BY100) 55 Industrial Only Speed in nanoseconds L Low Power 70P257 70P247 128K (8K x 16) 1.8V Dual-Port SRAM 64K (4K x 16) 1.8V Dual-Port SRAM 5684 drw 20 Preliminary Datasheet: Definition "PRELIMINARY' datasheets contain descriptions for products that are in early release. Datasheet Document History 02/04/04: Initial Datasheet CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 623 .42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.