IDT70P35L25BYI

HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ADVANCED IDT70P35/34L IDT70P25/24L ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access IDT70P35/34L (IDT70P25/24L) – Commercial: 20/25ns (max.) – Industrial: 25ns (max.) Low-power operation IDT70P35/34L (IDT70P25/24L) Active: 30.6mW (typ.) Standby: 5.4mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT70P35/34L (IDT70P25/24L) easily expands data bus width to 36 bits (32 bits) or more using the Master/Slave ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 1.8V (±100mV) power supply Available in a 100-pin Thin Quad Flatpack (TQFP) package, 100-pin 0.8mm pitch Ball Grid Array (fpBGA), and 100-pin 0.5mm pitch BGA (fpBGA) Industrial temperature range (-40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL R/WR UBR LB CEL L OEL LBR CER OER , I/O9L-I/O17L(5) I/O0L-I/O8L(4) BUSYL A12L(1) A0L (2,3) I/O9R-I/O17R(5) I/O Control I/O Control I/O0R-I/O8R(4) BUSYR (2,3) Address Decoder 13 MEMORY ARRAY 13 Address Decoder A12R(1) A0R CEL OEL R/WL SEML (3) INTL NOTES: 1. A12 is a NC for IDT70P34 and IDT70P24. 2. (MASTER): BUSY is output; (SLAVE): BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull. 4. I/O0x - I/O 7x for IDT70P25/24. 5. I/O8x - I/O15 x for IDT70P25/24. ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR INTR(3) 5683 drw 01 M/S FEBRUARY 2004 1 DSC-5683/2 ©2004 Integrated Device Technology, Inc. IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges The IDT70P35/34L (IDT70P25/24L) is a high-speed 8/4K x 18 (8/4K x 16) Dual-Port Static RAM. The IDT70P35/34L (IDT70P25/24L) is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit (32-bit) or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for Description reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 30.6mW of power. The IDT70P35/34L (IDT70P25/24L) is packaged in a plastic 100-pin Thin Quad Flatpack, a 100-pin fine pitch Ball Grid Array, and a 100-pin 0.5mm pitch fpBGA. IDT70P35/34 Pin Configurations(1,2,3,4) 12/17/03 Index N/C N/C I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L Vss I/O15L I/O16L VDD Vss I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R N/C N/C 100 99 98 9796 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74 73 72 71 70 69 68 67 I/O10L I/O9L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L Vss I/O1L I/O0L OEL VDD R/W L SEML CEL UBL LBL A12L(1) A11L A10L A9L A8L A7L A6L IDT70P35/34PF PN100-1(5) 100-Pin TQFP Top View(6) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL Vss M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C , 5683 drw 02 NOTES: 1. A12 is a NC for IDT70P34. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part marking. I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R Vss I/O16R OER R/WR Vss SEMR CER UBR LBR A12R (1) A11R A10R A9R A8R A7R A6R A5R 6.42 2 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges IDT70P35/34 Pin Configurations(cont'd) (1,2,3,4) IDT70P35/34BF BF100(5) 100-Pin fpBGA Top View(6) 12/16/03 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A6R B1 A9R B2 A12R(1) B3 CER B4 VSS B5 VSS B6 VSS B7 I/O13R I/O10R I/O7R B8 B9 B10 NC C1 NC C2 A8R C3 A10R SEMR R/WR C4 C5 C6 OER I/O12R I/O9R I/O6R C7 C8 C9 C10 A3R D1 A4R D2 A 5R D3 A7R D4 UBR D5 I/O16R I/O15R I/O11R I/O8R I/O3R D6 D7 D8 D9 D10 A1R E1 INTR E2 A2R E3 NC E4 A11R E5 LBR I/O14R I/O17R I/O5R E6 E7 E8 E9 I/O1R E10 M/S BUSYR A 0R F1 F2 F3 A1L F4 VSS F5 VSS F6 I/O4R I/O2R I/O0R F7 F8 F9 VDD F10 VSS G1 BUSYL G2 A0L G3 NC G4 VDD G5 VSS G6 VDD G7 I/O14L I/O15L I/O16L G8 G9 INTL H1 A3L H2 A6L H3 NC H4 VSS H5 I/O3L H6 NC H7 I/O12L H8 VSS H9 ,I/O13L H10 G10 A2L J1 A5L J2 A10L J3 LBL J4 CEL J5 I/O1L J6 I/O7L J7 I/O8L I/O17L I/O11L J8 J9 J10 A4L K1 A8L K2 A 11L SEML R/WL K3 K4 K5 OEL K6 I/O4L I/O6L K7 K8 VSS K9 I/O10L K10 A7L A9L A12L(1) UBL VDD VDD I/O0L I/O2L I/O5L I/O9L 5683 drw 03 NOTES: 1. A12 is a NC for IDT70P34. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part marking. 6.42 3 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges IDT70P25/24 Pin Configurations(1,2,3,4) Index N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L VSS I/O14L I/O15L VDD VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L OEL VDD R/WL SEML CEL UBL LBL A12L(1) A11L A10L A9L A8L A7L A6L IDT70P25/24PF PN100-1(5) 100-Pin TQFP Top View(6) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 12/17/03 N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL VSS M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C 5683 drw 04 . NOTES: 1. A12 is a NC for IDT70P24. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground. 4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part marking. I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R VSS I/O15R OER R/WR VSS SEMR CER UBR LBR A12R (1) A11R A10R A9R A8R A7R A6R A5R 6.42 4 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges IDT70P25/24 Pin Configurations(cont'd) (1,2,3,4) IDT70P25/24BF BF100(5) 100-Pin fpBGA Top View(6) 12/16/03 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A6R B1 A9R B2 A 12R(1) CER B3 B4 VSS B5 VSS B6 VSS B7 I/O12R I/O9R I/O7R B8 B9 B10 NC C1 NC C2 A8R C3 A10R SEMR R/WR OER I/O11R I/O8R I/O6R C4 C5 C6 C7 C8 C9 C10 A3R D1 A4R D2 A5R D3 A7R D4 UBR I/O15R I/O14R I/O10R D5 D6 D7 D8 NC D9 I/O3R D10 A1R E1 INTR E2 A2R E3 NC E4 A11R E5 LBR E6 I/O13R E7 NC E8 I/O5R I/O1R E9 E10 M/S F1 BUSYR F2 A0R F3 A1L F4 VSS F5 VSS F6 I/O4R I/O2R I/O0R F7 F8 F9 VDD F10 VSS G1 BUSYL G2 A0L G3 NC G4 VDD G5 VSS G6 VDD G7 I/O13L I/O14L I/O15L G8 G9 G10 INTL H1 A3L H2 A6L H3 NC H4 VSS H5 I/O3L H6 NC H7 I/O11L H8 VSS H9 I/O12L H10 , A2L J1 A5L J2 A10L J3 LBL J4 CEL J5 I/O1L J6 I/O7L J7 NC J8 NC J9 I/O10L J10 A4L K1 A8L K2 A11L K3 SEML R/W L K4 K5 OE L K6 I/O4L K7 I/O6L K8 VSS K9 I/O9L K10 A7L A9L A12L(1) UBL VDD VDD I/O0L I/O2L I/O5L I/O8L 5683 drw 05 NOTES: 1. A12 is a NC for IDT70P24. 2. All V DD pins must be connected to power supply. 3. All V SS pins must be connected to ground. 4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part marking. 6.42 5 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges IDT70P25/24 Pin Configurations(1,2,3,4) 70P25/24BY BY-100(5) 100-Ball 0.5mm Pitch BGA Top View(6) 12/17/03 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A5R B1 A8R B2 A11R B3 UBR B4 Vss B5 SEMR I/O15R I/O12R I/O10R Vss B6 B7 B8 B9 B10 A3R C1 A4R C2 A7R C3 A9R C4 CER C5 R/ WR C6 OER C7 VDD C8 I/O9R I/O6R C9 C10 A0R D1 A 1R D2 A2R D3 A6R D4 LBR D5 NC D6 I/O14R I/O11R I/O7R D7 D8 D9 Vss D10 NC E1 NC E2 BUSYR INT R E3 E4 A10R E5 A12R(1) E6 I/O13R I/O8R I/O5R I/O2R E7 E8 E9 E10 Vss F1 M/S F2 NC F3 INTL F4 Vss F5 Vss F6 I/O4R F7 VDD F8 I/O1R F9 Vss F10 Vss G1 NC G2 BUSYL G3 A1L G4 VDD G5 Vss G6 I/O3R I/O0R I/O15L V DD G7 G8 G9 G10 NC H1 A2L H2 A5L H3 A12L(1) H4 OEL H5 I/O3L I/O11L I/O12L I/O14L I/O13L H6 H7 H8 H9 H10 A0L J1 A4L J2 A9L J3 LBL J4 CEL J5 I/O1L J6 VDD J7 NC J8 NC J9 I/O10L J10 A3L K1 A7L K2 A10L K3 NC K4 VDD K5 Vss K6 I/O4L K7 I/O6L I/O8L I/O9L K8 K9 K10 A6L A8L A11L UBL SEML R/WL I/O0L I/O2L I/O5L I/O7L 5683 drw 06 NOTES: 1. A12X is a NC for IDT70P24. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. BY100-1 package body is approximately 6mm x 6mm x 1mm, ball pitch 0.5mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 6 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Pin Names Left Port CEL R/ WL OEL A 0L - A12L(1) I/O0L - I/O17L SEML UBL LBL INTL BUSYL (2) Right Port CER R/WR OER A 0R - A12R(1) I/O0R - I/O17R SEMR UBR LBR INTR BUSYR M/S VDD VSS (2) Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select(3) Lower Byte Select(4) Interrupt Flag Busy Flag Master or Slave Select Power (1.8V) Ground (0V) 5683 tbl 01 NOTE: 1. A12 is a NC for IDT70P34 and IDT70P24. 2. I/O0x - I/O15 x for IDT70P25/24. 3. IDT70P35/34L: UBx controls I/O9x - I/O17x IDT70P25/24L: UBx controls I/O8x - I/O15x 4. IDT70P35/34L: LBx controls I/O0x - I/O8x IDT70P25/24L: LBx controls I/O0x - I/O 7x 6.42 7 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Inputs(1) CE H X L L L L L L X R/W X X L L L H H H X OE X X X X X L L L H UB X H L H L L H L X LB X H H L L H L L X SEM H H H H H H H H X I/O9-17 Outputs (3) I/O0-8(2) High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Deselected: Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Mode High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z NOTE: 1. A0L — A12L ≠ A0R — A12R for IDT70P35 and IDT70P25; A0L — A11L ≠ A0R — A11R for IDT70P34 and IDT70P24. 2. Outputs for IDT70P25/24 are I/O0x - I/O7x. 3. Outputs for IDT70P25/24 are I/O8x - I/O 15x. 5683 tbl 02 Truth Table II: Semaphore Read/Write Control(1) Inputs CE H X H X L L R/ W H H ↑ ↑ X X OE L L X X X X UB X H X H L X LB X H X H X L SEM L L L L L L I/O9-17(1) DATAOUT DATAOUT DATAIN DATAIN ____ ____ Outputs I/O0-8(1) DATAOUT DATAOUT DATAIN DATAIN ____ ____ Mode Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed 5683 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0-I/O17 for IDT70P35/34 and I/O0-I/O15 for IDT70P25/24). These eight semaphores are addressed by A0-A2. 6.42 8 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM TBIAS TSTG TJN IOUT (2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to VDDMAX + 0.3V -55 to +125 -65 to +150 +150 20 Unit V Maximum Operating Temperature and Supply Voltage(1) Grade Commercial Ambient Temperature 0OC to +70OC -40 C to +85 C O O GND 0V 0V VDD 1.8V + 100mV 1.8V + 100mV 5683 tbl 05 o C C C Industrial o o NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. mA 5683 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected. Recommended DC Operating Conditions Symbol V DD V SS V IH Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 1.7 0 1.2 -0.2 (1) Typ. 1.8 0 ____ ____ Max. 1.9 0 VDD+0.2 0.4 Unit V V V V 5683 tbl 06 Capacitance(1) (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 11 Unit pF pF 5683 tbl 07 VIL NOTES: 1. VIL > -1.5V for pulse width less than 10ns. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV) 70P35/34L (70P25/24L) Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Currentt Output Low Voltage Output High Voltage Test Conditions VDD = 1.8V, VIN = 0V to VDD CE = VIH, VOUT = 0V to VDD IOL = + 0.1mA IOH = -0.1mA Min. ___ ___ ___ Max. 1 1 0.2 ___ Unit µA µA V V 5683 tbl 08 VDD - 0.2 6.42 9 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV) 70P35/34L20 (70P25/24L20) Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CER and CEL = V IH SEMR = SEML = V IH f = fMAX(3) CE"A" = V IL and CE"B" = V IH Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = V IH Both Ports CEL and CER > V DD - 0.2V, V IN > V DD - 0.2V or V IN < 0.2V, f = 0(4) SEMR = SEML > V DD-0.2V CE"A" < 0.2V and CE"B" > VDD - 0.2V (1) SEMR = SEML > V DD-0.2V V IN > V DD - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) (1) 70P35/34L25 (70P25/24L25) Com'l & Ind Typ. (2) 20 20 2.2 2.2 12 12 3 3 12 Max. 32 38 3.5 4.6 20 26 5 5 20 mA mA mA mA Unit mA Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L L L L L L L L L L L Typ. (2) 25 25 3.5 3.5 15 15 4.5 4.5 15 Max. 40 46 5.6 6.0 25 32 7.5 7.5 25 ISB1 ISB2 ISB3 ISB4 Full Standby Current (One Port CMOS Level Inputs) IND 15 32 12 26 5683 tbl 09 NOTES: 1. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. VDD = 1.8V, TA = +25°C, and are not production tested. IDD dc = 15mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 1.8V AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 1.8V 3ns Max. 0.9V 0.9V Figure 1 30pF 13500Ω 10800Ω 5683 drw 07 5683 tbl 10 Figure 1. AC Output Test Load *(For tLZ , tHZ, tWZ, tOW) Timing of Power-Up Power-Down CE ICC ISB tPU 50% 6.42 10 tPD 50% 5683 drw 07 , IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P35/34L20 (70P25/24L20) Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time (3) Byte Enable Access Time (3) Output Enable Access Time (3) 70P35/34L25 (70P25/24L25) Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 ____ ____ ____ 25 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 5683 tbl 11 20 20 20 12 ____ 25 25 25 13 ____ ____ ____ ____ ____ Output Hold from Address Change Output Low-Z Time (1,2) Output High-Z Time (1,2) Chip Enable to Power Up Time (1,2) Chip Disable to Power Down Time (1,2) Semaphore Flag Update Pulse (OE o r SEM) Semaphore Address Access (3) 3 3 ____ 3 3 ____ ____ ____ 12 ____ 15 ____ 0 ____ 0 ____ 20 ____ 25 ____ 10 ____ 10 ____ 20 25 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = V IH, and SEM = VIL. Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE OE tABE UB, LB (4) (4) (4) CE R/W tLZ DATAOUT (1) t OH VALID DATA (4) (2) t HZ BUSYOUT tBDD (3,4) 5683 drw 09 , NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE , tAA or tBDD . 5. SEM = VIH. 611 .42 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 70P35/34L20 (70P25/24L20) Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time (4) Write Enable to Output in High-Z Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window (1,2) (1,2) (3) 70P35/34L25 (70P25/24L25) Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 15 15 0 15 0 15 ____ ____ ____ ____ ____ ____ ____ ____ 25 20 20 0 20 0 15 ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns 5683 tbl 12 12 ____ 15 ____ 0 ____ 0 ____ 12 ____ ____ ____ 15 ____ ____ ____ (1,2,4) 0 5 5 0 5 5 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although t DH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 6.42 12 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ OE tAW CE or SEM (9) (7) CE or SEM (9) (6) (2) (3) tAS R/W tWP tWR tWZ DATAOUT (4) (7) tOW (4) tDW DATAIN tDH 5683 drw 10 , Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) tAS(6) UB or LB (9) tEW (2) tWR (3) R/W tDW DATAIN 5683 drw 11 , tDH NOTES: 1. R/W or CE or UB & LB must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or t WP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition the outputs remain in the HIGH-impedance state. 6. Timing depends on which enable signal is asserted last, CE , R/W, or UB or LB. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load (Figure 1). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required t DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP. 9. To access SRAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB and LB = VIH, and SEM = V IL. tEW must be met for either condition. 613 .42 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0 - A2 VALID ADDRESS tAW SEM tEW tDW DATA0 tAS R/W tSWRD OE Write Cycle tOH VALID ADDRESS tWR tACE tSOP DATA OUT VALID(2) DATAIN VALID tWP tDH tAOE tSOP Read Cycle 5683 drw 12 . NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O17 for IDT70P35/34) and (I/O0-I/O15 for IDT70P25/24) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) MATCH SIDE "B" R/W"B" SEM"B" NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM "A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 5683 drw 13 , 6.42 14 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P35/34L20 (70P25/24L20) Com'l Only Symbol BUSY TIMING (M/ S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable LOW BUSY Disable Time from Chip Enable HIGH Arbitration Priority Set-up Time BUSY Disable to Valid Data Write Hold After BUSY (5) (3) (2) ____ ____ ____ ____ 70P35/34L25 (70P25/24L25) Com'l & Ind Min. Max. Unit Parameter Min. Max. 20 20 20 17 ____ ____ ____ ____ ____ 20 20 20 17 ____ ns ns ns ns ns ns ns 5 ____ 5 ____ 30 ____ 30 ____ 15 17 BUSY TIMING (M/ S = VIL) tWB tWH BUSY Input to Write (4) Write Hold After BUSY (5) 0 15 ____ ____ 0 17 ____ ____ ns ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ ____ 45 35 ____ ____ 50 35 ns ns 5683 tbl 13 NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = V IH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT "B" tDDD NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”. (3) (1) tDH VALID MATCH tBDA tBDD VALID , 5683 drw 14 615 .42 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY tWP R/W"A" tWB BUSY"B" (3) tWH (1) R/W"B" NOTES: 1. tWH must be met for both master BUSY input (slave) and output (master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the slave version. (2) 5683 drw 15 , Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC BUSY"B" 5683 drw 16 tBDC , Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR "A" tAPS ADDR "B" (2) ADDRESS "N" MATCHING ADDRESS "N" tBAA tBDA , 5683 drw 16 BUSY"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 6.42 16 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70P35/34L20 (70P25/24L20) Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ ____ ____ 70P35/34L25 (70P25/24L25) Com'l & Ind Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ____ ____ ns ns ns ns 5683 tbl 14 20 20 20 20 Waveform of Interrupt Timing(1) tWC ADDR"A" tAS CE"A" (3) INTERRUPT SET ADDRESS (2) (4) tWR R/W"A" tINS (3) INT"B" 5683 drw 18 , tRC ADDR"B" tAS(3) CE"B" INTERRUPT CLEAR ADDRESS (2) OE"B" tINR INT"B" 5683 drw 19 (3) , NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag Truth Table III. 3. Timing depends on which enable signal (CE or R/ W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 617 .42 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Truth Table III — Interrupt Flag(1) Left Port R/WL L X X X CEL L X X L OEL X X X L A12L-A0L 1FFF X X 1FFE (4) Right Port INTL X X L (3) (2) R/WR X X L X CER X L L X OER X L X X A12R-A0R(4) X 1FFF 1FFE X INTR L (2) (3) Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 5683 tbl 15 H X X H NOTES: 1. Assumes BUSYL = BUSYR = VIH . 2. If BUSY L = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A12 is a NC for IDT70P34 and IDT70P24, therefore Interrupt Addresses are FFF and FFE. Truth Table IV — Address BUSY Arbitration Inputs CEL X H X L CER X X H L A12L-A0L A12R-A0R (4) Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 5683 tbl 16 NO MATCH MATCH MATCH MATCH NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70P35/34L (IDT70P25/24L) are push pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSY L and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A12 is a NC for IDT70P34 and IDT70P24. Address comparison will be for A0 - A11 . Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D17 Left(2) 1 0 0 1 1 0 1 1 1 0 1 D0 - D17 Right(2) 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 5683 tbl 17 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70P35/34L (IDT70P25/24L). 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 for IDT70P35/34 and I/O 0-I/O15 for IDT70P25/24). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Tables. 6.42 18 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges MASTER Dual Port SRAM BUSYL CE BUSYR SLAVE CE Dual Port SRAM BUSYR BUSYL BUSYL MASTER CE Dual Port SRAM BUSYR BUSYL SLAVE CE Dual Port SRAM BUSYR BUSYL BUSYR , 5683 drw 20 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70P35/34L (IDT70P25/24L) SRAMs. The IDT70P35/34L (IDT70P25/24L) provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70P35/34L (IDT70P25/24L) has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Functional Description operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70P35/34L (IDT70P25/24L) SRAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these SRAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX)(FFF for IDT70P34 and IDT70P24), where a write is defined as the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt by an address location 1FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port interrupt flag (INTR) is set when the left port writes to memory location 1FFF (HEX) (FFF for IDT70P34 and IDT70P24) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message to the interrupt mail box is userdefined, since it is an addressable SRAM location. If the interrupt function is not used, the interrupt address locations are not used as mail boxes but as part of the random access memory. Interrupts Busy Logic Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write When expanding an IDT70P35/34L (IDT70P25/24L) SRAM array in width while using BUSY logic, one master part is used to decide which side of the SRAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70P35/34L (IDT70P25/24L) SRAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Width Expansion with Busy Logic Master/Slave Arrays The IDT70P35/34L (IDT70P25/24L) is an extremely fast Dual-Port 8/4K x 18 (8/4K x 16) CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor Semaphores 619 .42 DECODER IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be accessed at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the nonsemaphore portion of the Dual-Port SRAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT70P35/34L (IDT70P25/24L) contain multiple processors or controllers and are typically very highspeed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70P35/ 34L (IDT70P25/24L)'s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70P35/34L (IDT70P25/24L) does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70P35/34L (IDT70P25/24L) in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on How the Semaphore Flags Work the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to 6.42 20 IDT70P35/34L (IDT70T25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT70P35/34L (IDT70P25/24L)’s DualPort SRAM. Say for example, the 8K x 18 SRAM was to be divided into two 4K x 18 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ SEMAPHORE READ , 5683 drw 21 Figure 4. IDT70P35/34L (IDT70P25/24L) Semaphore Logic 621 .42 IDT70P35/34L(IDT70P25/24L) High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM ADVANCED Industrial and Commercial Temperature Ranges Ordering Information(1) IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I PF BF BY Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 100-pin TQFP (PN100-1) 100-pin 0.8mm pitch fpBGA (BF100) 100-pin 0.5mm pitch fpBGA(BY100)(1) , 20 25 Commercial Only Commercial & Industrial , Speed in Nanoseconds L 70P35 70P34 70P25 70P24 NOTE: 1. Available only for IDT70P25/24. Low Power 144K (8K x 18-Bit) 1.8V Dual-Port RAM 72K (4K x 18-Bit) 1.8V Dual-Port RAM 128K (8K x 16-Bit) 1.8V Dual-Port RAM 64K (4K x 16-Bit) 1.8V Dual-Port RAM 5683 drw 22 Advanced Datasheet: Definition "ADVANCED"datasheets contain descriptions for products that are in early release. Datasheet Document History 01/26/04: 02/25/04: Initial Datasheet Page 1 Corrected standby power from 18µW to 5.4mW for low-power operation CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6.42 22 for Tech Support: 831-754-4613 DualPortHelp@idt.com