IDT70T633S12DDI

Features ◆ ◆ HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ ◆ ◆ ◆ PRELIMINARY IDT70T633/1S ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T633/1 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags ◆ ◆ ◆ ◆ ◆ ◆ Full hardware support of semaphore signaling between ports on-chip On-chip port arbitration logic Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 in BGA-208 and BGA-256 packages Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 256-ball Ball Grid Array, 144-pin Thin Quad Flatpack and 208-ball fine pitch Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds UB R LB R Functional Block Diagram UBL LBL R/W L B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE1L CE0R CE1R OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R OER 512/256K x 18 MEMORY ARRAY I/O0L - I/O17L Din_L Din_R I/O0R - I/O17R A18L(1) A 0L Address Decoder ADDR_L ADDR_R Address Decoder A18R (1) A0R TDI OEL CE0L CE1L R/ WL ARBITRATION INTERRUPT SEMAPHORE LOGIC OER CE0R CE1R TDO JTAG TCK TMS TRST R/WR BUSYL(2,3) SEM L INTL(3) (4) BUSYR(2,3) M/ S SEM R INTR(3) NOTES: 1. Address A 18x is a NC for IDT70T631. 2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 3 BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. ZZL ZZ CONTROL LOGIC ZZR (4) 5670 drw 01 NOVEMBER 2003 DSC-5670/3 1 ©2003 Integrated Device Technology, Inc. I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down Description feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T651/9 has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performance levels. The 70T633/1 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 2.5V. 2 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3) 70T633/1BC BC-256(5,6) 256-Pin BGA Top View A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 03/13/03 A1 NC B1 TDI B2 NC B3 A17L B4 A 14L B5 A11L B6 A8L B7 NC B8 CE1L B9 OEL B10 INT L B11 A5L B12 A2L B13 A0L B14 NC B15 NC B16 NC C1 NC C2 TDO A18L(4) A15L C3 C4 C5 A12L C6 A9L C7 UBL C8 CE0L R/WL C9 C10 NC C11 A4L C12 A1L C13 NC C14 NC C15 NC C16 NC D1 I/O9L D2 VSS D3 A16L D4 A13L D5 A10L D6 A7L D7 NC D8 LBL D9 SEML BUSYL D10 D11 A6L D12 A3L D13 OPTL D14 NC D15 I/O8L D16 NC E1 I/O9R E2 NC E3 VDD VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 NC E14 NC E15 I/O8R E16 I/O10R I/O 10L F1 F2 NC F3 VDDQL VDD F4 F5 VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VDD F11 VDD VDDQR F12 F13 NC F14 I/O7L I/O7R F15 F16 I/O11L G1 NC G2 I/O11R VDDQL VDD G3 G4 G5 NC G6 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VDD VDDQR I/O6R G12 G13 G14 NC G15 I/O6L G16 NC H1 NC H2 I/O12L VDDQR VSS H3 H4 H5 VSS H6 VSS H7 VSS H8 VSS H9 VSS H10 VSS H11 VSS H12 VDDQL I/O5L H13 H14 NC H15 NC H16 NC J1 I/O12R J2 J3 NC VDDQR VSS J4 J5 VSS J6 VSS J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VDDQL J13 NC J14 NC J15 I/O5R J16 I/O13L I/O 14R I/O13R VDDQL ZZ R K1 K2 K3 K4 K5 VSS K6 VSS K7 VSS K8 VSS K9 VSS K10 VSS K11 ZZL VDDQR I/O4R I/O3R I/O 4L K12 K13 K14 K15 K16 NC L1 NC L2 I/O14L VDDQL VSS L3 L4 L5 VSS L6 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VDDQR NC L13 L14 NC L15 I/O3L L16 I/O15L M1 NC M2 I/O15R VDDQR VDD M3 M4 M5 NC M6 VSS M7 VSS M8 VSS M9 VSS M10 VSS M11 VDD M12 VDDQL I/O2L M13 M14 NC M15 I/O2R M16 I/O16R I/O 16L N1 N2 NC N3 VDDQR N4 VDD N5 VDD N6 VSS N7 VSS N8 VSS N9 VSS N10 VDD N11 VDD VDDQL I/O1R I/O1L N12 N13 N14 N15 NC N16 NC P1 I/O17R P2 NC P3 VDD VDDQR VDDQR VDDQL VDDQL VDDQR V DDQR VDDQL VDDQL VDD P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 NC P14 I/O0R P15 NC P16 NC R1 I/O 17L TMS R2 R3 A16R R4 A13R R5 A10R R6 A7R R7 NC R8 LBR SEMR BUSYR R9 R10 R11 A6R R12 A3R R13 NC R14 NC R15 I/O 0L R16 NC T1 NC T2 TRST A18R(4) A15R T3 T4 T5 A12R T6 A9R T7 UBR T8 CE0R R/WR T9 T10 M/ S T11 A4R T12 A1R T13 OPTR T14 NC T15 NC T16 , NC TCK NC A17R A14R A11R A8R NC CE1R OER INT R A5R A2R A0R NC NC 5670 drw 02c NOTES: 1. All VDD pins must be connected to 2.5V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3. All VSS pins must be connected to ground supply. 4. A18X is a NC for IDT70T631. 5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. This package code is used to reference the package diagram. , 3 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3,8) (con't.) 03/13/03 VSS VDDQR VSS I/O9L I/O9R I/O10L I/O10R I/O11L I/O11R VDDQL VSS I/O12L I/O12R VDDQR ZZR VDD VDD VSS VSS VDDQL VSS I/O13R I/O13L I/O14R I/O14L VDDQR VSS I/O15R I/O15L I/O16R I/O16L I/O17R I/O17L VSS VDDQL NC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD NC NC A18L(4) A17L A16L A15L A14L A13L A12L A11L A10L A9L A8L A7L UBL LBL CE1L CE0L VDD VSS SEML OEL R/WL BUSYL INTL NC A6L A5L A4L A3L A2L A1L A0L VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 70T633/1DD DD-144(5,6,7) 144-Pin TQFP Top View(8) 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 OPTL VDDQR VSS I/O8L I/O8R I/O7L I/O7R I/O6L I/O6R VSS VDDQL I/O5L I/O5R VSS VDDQR VDD VDD VSS VSS ZZL VDDQL I/O4R I/O4L I/O3R I/O3L VSS VDDQR I/O2R I/O2L I/O1R I/O1L I/O0R I/O0L VSS VDDQL OPTR VDD NC NC A18R(4) A17R A16R A15R A14R A13R A12R A11R A10R A9R A8R A7R UBR LBR CE1R CE0R VDD VSS SEMR OER R/WR BUSYR INTR M/S A6R A5R A4R A3R A2R A1R A0R VDD VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 , 5670 drw 02a NOTES: 1. All VDD pins must be connected to 2.5V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3. All VSS pins must be connected to ground. 4. A18X is a NC for IDT70T631. 5. Package body is approximately 20mm x 20mm x 1.4mm. 6. This package code is used to reference the package diagram. 7. 8ns Commercial and 10ns Industrial speed grades are not available in the DD-144 package. 8. This text does not indicate orientation of the actual part-marking. 9. Due to the restricted number of pins, JTAG is not supported in the DD-144 package. 4 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3)(con't.) 03/12/03 1 A B C D E F G H J K L M N P R T U I/O 9L 2 NC 3 VS S 4 TDO 5 NC 6 A16L 7 A 12L 8 A 8L 9 NC 10 11 VDD 12 INTL 13 14 A4L A0L 15 OPTL 16 17 NC VSS SEML A B C D E F G H J K L M N P R T U NC VS S NC TDI A 17L A13L A 9L NC CE0L VSS BUSYL A5L A 1L VS S VDD QR I/O 8L NC V DD QL I/O 9R VDDQR V DD A18L (4 ) A14 L A1 0L UBL CE1L VSS R/WL A6L A2L VDD I/O 8R NC VSS NC VSS I/O 10L NC A 15 L A 11L A7 L LBL V DD OE L NC A 3L VDD NC VD DQL I/O 7L I/O7 R I/O11L NC VD DQ R I/O 10 R I/O6L NC V SS NC V DD QL I/O 11R NC VSS VS S I/O 6R NC VD DQ R NC VS S I/O 12L NC NC V DD QL I/O 5L NC VDD NC VD DQ R I/O 12R 70T633/1BF BF-208(5,6) 208-Ball BGA Top View(7) VD D NC VSS I/O5R VDD QL VD D VSS ZZR ZZ L V DD VSS V DDQ R I/O14R VS S I/O 13R VS S I/O3R VD DQL I/O 4R V SS NC I/O14L VD DQ R I/O 13L NC I/O 3L V SS I/O4L V DD QL NC I/O 15R V SS VS S NC I/O 2R VDDQ R NC VS S NC I/O 15 L I/O 1R V DD QL NC I/O2L I/O16R I/O 16L VD DQ R NC TRST A16R A 12R A 8R NC VD D SEM R INTR A 4R NC I/O 1L V SS NC VS S NC I/O 17 R TCK A17R A13R A9R NC CE0R VS S BUSYR R/ WR A5R A1R VS S VD DQ L I/O0R VDDQR NC I/O 17L VD DQ L TMS A18R (4) A14R A1 0R UB R CE1R VS S A6R A2R VS S NC V SS NC VS S NC VDD NC A15R A11R A7R LBR VDD OE R M/S A 3R A0R VDD OPT R NC I/O0L 5670 drw 02b NOTES: 1. All VDD pins must be connected to 2.5V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3. All VSS pins must be connected to ground. 4. A18X is a NC for IDT70T631. 5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 5 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A18L (1) Right Port CE0R, CE1R R/WR OER A0R - A18R (1) Names Chip Enables (Input) Read/Write Enable (Input) Output Enable (Input) Address (Input) Data Input/Output Semaphore Enable (Input) Interrupt Flag (Output) Busy Flag (Output) Upper Byte Select (Input) Lower Byte Select (Input) I/O0L - I/O17L SEML INTL BUSYL UBL LBL VDDQL OPTL ZZL I/O0R - I/O17R SEMR INTR BUSYR UBR LBR VDDQR OPTR ZZR M/S VDD VSS TDI TDO TCK TMS TRST Power (I/O Bus) (3.3V or 2.5V)(2) (Input) Option for selecting VDDQX(2,3) (Input) Sleep Mode Pin(4) (Input) Master or Slave Select (Input)(5) Power (2.5V)(2) (Input) Ground (0V) (Input) Test Data Input Test Data Output Test Logic Clock (10MHz) (Input) Test Mode Select (Input) Reset (Initialize TAP Controller) (Input) 5670 tbl 01 NOTES: 1. Address A18x is a NC for IDT70T631. 2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 3. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode. 5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/ S =V IH). 6 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1) OE X X X X X X L L L H X SEM H H H H H H H H H H X CE0 H X L L L L L L L L X CE 1 X L H H H H H H H H X UB X X H H L L H L L L X LB X X H L H L L H L L X R/ W X X X L L L H H H X X ZZ L L L L L L L L L L H Upper Byte I/O9-17 High-Z High-Z High-Z High-Z DIN DIN High-Z DOUT DOUT High-Z High-Z Lower Byte I/O0-8 High-Z High-Z High-Z DIN High-Z DIN DOUT High-Z DOUT High-Z High-Z MODE Deselected–Power Down Deselected–Power Down Both Bytes Deselected Write to Lower Byte Write to Upper Byte Write to Both Bytes Read Lower Byte Read Upper Byte Read Both Bytes Outputs Disabled High-Z Sleep Mode 5670 tbl 02 NOTE: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. Truth Table II – Semaphore Read/Write Control(1) Inputs(1) CE(2) H H L R/W H ↑ X OE L X X UB L X X LB L L X SEM L L L I/O1-17 DATAOUT X ______ Outputs I/O0 DATAOUT DATAIN ______ Mode Read Data in Semaphore Flag (3) Write I/O0 into Semaphore Flag Not Allowed 5670 tbl 03 NOTES: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A 0-A2. 2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL. 3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL. 7 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature 0 C to +70 C O O Recommended DC Operating Conditions with VDDQ at 2.5V Symbol Parameter Core Supply Voltage I/O Supply Voltage (3) Ground Input High Volltage (Address, Control & Data I/O Inputs)(3) Input High Voltage _ JTAG Input High Voltage ZZ, OPT, M/S Input Low Voltage Input Low Voltage ZZ, OPT, M/S Min. 2.4 2.4 0 1.7 Typ. 2.5 2.5 0 ____ Max. 2.6 2.6 0 V DDQ + 100mV(2) Unit V V V V GND 0V 0V VDD 2.5V + 100mV 2.5V + 100mV 5670 tbl 04 VDD VDDQ VSS VIH -40OC to +85OC NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. VIH VIH VIL 1.7 VDD - 0.2V -0.3(1) -0.3 (1) ____ VDD + 100mV (2) VDD + 100mV (2) 0.7 0.2 V V V V 5670 tbl 05 ____ Absolute Maximum Ratings Symbol VTERM (V DD) VTERM(2) (V DDQ) VTERM(2) (INPUTS and I/O's) TBIAS(3) TSTG TJN Rating VDD Terminal Voltage with Respect to GND VDDQ Terminal Voltage with Respect to GND Input and I/O Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature (1) Unit V V V o ____ Commercial & Industrial -0.5 to 3.6 -0.3 to V DDQ + 0.3 -0.3 to V DDQ + 0.3 -55 to +125 -65 to +150 +150 50 40 VIL ____ NOTES: 1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less. 2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is less. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be supplied as indicated above. C C C o o IOUT(For V DDQ = 3.3V) DC Output Current IOUT(For V DDQ = 2.5V) DC Output Current mA mA 5670 tbl 07 Recommended DC Operating Conditions with VDDQ at 3.3V Symbol V DD VDDQ V SS VIH Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address, Control &Data I/O Inputs)(3) Input High Voltage JTAG _ (3) Min. 2.4 3.15 0 2.0 Typ. 2.5 3.3 0 ____ Max. 2.6 3.45 0 VDDQ + 150mV(2) Unit V V V V NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. VIH VIH VIL VIL 1.7 VDD - 0.2V -0.3(1) -0.3(1) ____ VDD + 100mV (2) VDD + 100mV (2) 0.8 0.2 V V V V 5670 tbl 06 Input High Voltage ZZ, OPT, M/S Input Low Voltage Input Low Voltage ZZ, OPT, M/S ____ ____ ____ Capacitance Symbol CIN COUT (3) (1) Conditions VIN = 3dV VOUT = 3dV (2) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Parameter Input Capacitance Output Capacitance Max. 8 10.5 Unit pF pF 5670 tbl 08 NOTES: 1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less. 2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is less. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated above. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 8 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV) 70T633/1S Symbol |ILI| |ILI| |ILO| VOL (3.3V) VOH (3.3V) VOL (2.5V) VOH (2.5V) Parameter Input Leakage Current (1) (1,2) Test Conditions VDDQ = Max., VIN = 0V to VDDQ VDD = Max., VIN = 0V to VDD CE0 = V IH o r CE 1 = VIL, VOUT = 0V to VDDQ IOL = + 4mA, VDDQ = Min. IOH = -4mA, VDDQ = Min. IOL = + 2mA, VDDQ = Min. IOH = -2mA, VDDQ = Min. Min. ___ ___ ___ ___ Max. 10 +30 10 0.4 ___ Unit µA µA µA V V V V 5670 tbl 09 JTAG & ZZ Input Leakage Current Output Leakage Current Output Low Voltage (1) Output High Voltage Output Low Voltage (1) (1,3) 2.4 ___ (1) (1) 0.4 ___ Output High Voltage 2.0 NOTES: 1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details. 2. Applicable only for TMS, TDI and TRST inputs. 3. Outputs tested in tri-state mode. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV) 70T633/1S8(6) Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled f = fMAX(1) CEL = CER = VIH f = fMAX(1) CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f = fMAX(1) (5) 70T633/1S10 Com'l & Ind(6) Typ.(4) 300 300 90 90 200 200 2 2 200 200 2 2 Max. 405 445 120 145 265 290 10 20 265 290 10 20 70T633/1S12 Com'l & Ind Typ.(4) 300 300 75 75 180 180 2 2 180 180 2 2 Max. 355 395 105 130 230 255 10 20 230 255 10 20 70T633/1S15 Com'l Only Typ.(4) 225 ____ Version COM'L IND COM'L IND COM'L IND COM'L IND S S S S S S S S S S S S Typ.(4) 350 ____ Max. 475 ____ Max. 305 ____ Unit mA ISB1(6) 115 ____ 140 ____ 60 ____ 85 ____ mA ISB2 (6) 240 ____ 315 ____ 150 ____ 200 ____ mA ISB3 Full Standby Current Both Ports CEL and (Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V Level Inputs) or VIN < 0.2V, f = 0(2) Full Standby Current (One Port - CMOS Level Inputs) Sleep Mode Current (Both Ports - TTL Level Inputs) 2 ____ 10 ____ 2 ____ 10 ____ mA ISB4(6) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) COM'L VIN > VDD - 0.2V or VIN < 0.2V, Active IND Port, Outputs Disabled, f = fMAX(1) ZZL = ZZR = VIH f = fMAX(1) COM'L IND 240 ____ 315 ____ 150 ____ 200 ____ mA IZZ 2 ____ 10 ____ 2 ____ 10 ____ mA 5670 tbl 10 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS". 2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby. 3. VDD = 2.5V, TA = 25°C for Typ. values, and are not production tested. IDD DC(f=0) = 100mA (Typ). 4. CE X = VIL means CE0X = VIL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = V IL CE X < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V CE X > V DDQX - 0.2V means CE 0X > V DDQX - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 5. ISB1, ISB2 and ISB4 will all reach full standby levels (I SB3) on the appropriate port(s) if ZZL and /or ZZ R = VIH. 6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only. 9 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ = 3.3V/2.5V) Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V / GND to 2.5V 2ns Max. 1.5V/1.25V 1.5V/1.25V Figure 1 5670 tbl 11 50Ω DATAOUT 50Ω 1.5V/1.25 10pF (Tester) , 5670 drw 03 Figure 1. AC Output Test load. 4 3.5 3 ∆ tAA/tACE (Typical, ns) 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 140 160 ∆ Capacitance (pF) from AC Test Load 5670 drw 04 Figure 3. Typical Output Derating (Lumped Capacitive Load). 10 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70T633/1S8(5) Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tLZOB tHZ tPU tPD tSOP tSAA tSOE Read Cycle Time Address Access Time Chip Enable Access Time (3) Byte Enable Access Time (3) 70T633/1S10 Com'l & Ind(5) Min. Max. 70T633/1S12 Com'l & Ind Min. Max. 70T633/1S15 Com'l Only Min. Max. Unit Parameter Min. Max. 8 ____ ____ ____ ____ ____ 10 ____ ____ ____ ____ ____ 12 ____ ____ ____ ____ ____ 15 ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5670 tbl 12 8 8 4 4 ____ ____ ____ 10 10 5 5 ____ ____ ____ 12 12 6 6 ____ ____ ____ 15 15 7 7 ____ ____ ____ Output Enable Access Time Output Hold from Address Change Output Low-Z Time Chip Enable and Semaphore (1,2) Output Low-Z Time Output Enable and Byte Enable Output High-Z Time(1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) (1,2) 3 3 0 0 0 ____ ____ 3 3 0 0 0 ____ ____ 3 3 0 0 0 ____ ____ 3 3 0 0 0 ____ ____ 3.5 ____ 4 ____ 6 ____ 8 ____ 7 4 8 5 8 4 10 5 8 6 12 6 12 8 15 7 Semaphore Flag Update Pulse (OE o r SEM) Semaphore Address Access Time Semaphore Output Enable Access Time 2 ____ 2 ____ 2 ____ 2 ____ AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(4) 70T633/1S8(5) Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write (3) Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window (1,2) (3) 70T633/1S10 Com'l & Ind(5) Min. Max. 70T633/1S12 Com'l & Ind Min. Max. 70T633/1S15 Com'l Only Min. Max. Unit Parameter Min. Max. 8 6 6 0 6 0 4 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ 10 7 7 0 7 0 5 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ 12 9 9 0 9 0 7 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ 15 12 12 0 12 0 10 0 ____ ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 5670 tbl 13 3.5 ____ ____ ____ 4 ____ ____ ____ 6 ____ ____ ____ 8 ____ ____ ____ (1,2) 3 4 4 3 5 5 3 5 5 3 5 5 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when CE0 = VIL and CE1 = VIH. CE = VIH when CE 0 = VIH and/or CE1 = VIL. 4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only. 11 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE OE tABE (4) UB, LB (4) (4) CE (6) R/W tLZ/tLZOB DATAOUT (1) tOH VALID DATA (4) (2) . tHZ BUSYOUT tBDD (3,4) 5670 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB or UB . 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD. 5. SEM = VIH. 6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL. Timing of Power-Up Power-Down CE tPU ICC 50% 50% 5670 drw 07 tPD . ISB 12 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ OE tAW CE or SEM (9) (7) UB, LB (9) (6) (2) tAS R/W tWP tWR (3) tWZ (7) DATAOUT (4) tOW (7) (4) tDW DATAIN tDH 5670 drw 10 . Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8) tWC ADDRESS tAW CE or SEM (9) (6) tAS UB, LB(9) tEW (2) tWR(3) R/W tDW DATAIN 5670 drw 11 . tDH . NOTES: 1. R/W or CE or UB or LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/ W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 1). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL. 13 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges RapidWrite Mode Write Cycle Unlike other vendors' Asynchronous Random Access Memories, the IDT70T651/9 is capable of performing multiple back-to-back write operations without having to pulse the R/W, CE, or BEn signals high during address transitions. This RapidWrite Mode functionality allows the system designer to achieve optimum back-to-back write cycle performance without the difficult task of generating narrow reset pulses every cycle, simplifying system design and reducing time to market. During this new RapidWrite Mode, the end of the write cycle is now defined by the ending address transition, instead of the R/W or CE or BEn transition to the inactive state. R/W, CE, and BEn can be held active throughout the address transition between write cycles. Care must be taken to still meet the Write Cycle time (tWC), the time in which the Address inputs must be stable. Input data setup and hold times (tDW and tDH) will now be referenced to the ending address transition. In this RapidWrite Mode the I/O will remain in the Input mode for the duration of the operations due to R/W being held low. All standard Write Cycle specifications must be adhered to. However, tAS and tWR are only applicable when switching between read and write operations. Also, there are two additional conditions on the Address Inputs that must also be met to ensure correct address controlled writes. These specifications, the Allowable Address Skew (tAAS) and the Address Rise/Fall time (tARF), must be met to use the RapidWrite Mode. If these conditions are not met there is the potential for inadvertent write operations at random intermediate locations as the device transitions between the desired write addresses. Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3) tWC ADDRESS tWC (4) tWC CE or SEM(6) tEW (2) BEn tWR R/W tWP tWZ (5) tOW tDH tDW tDW tDH tDW tDH (5) DATAOUT DATAIN 5670 drw 08 NOTES: 1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state. 2. A write occurs during the overlap (tEW or tWP) of a CE = V IL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE , BEn, and R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence. 3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes. 5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 1). 6. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL and CE1 = VIH. CE = V IH when CE0 = VIH and/or CE1 = VIL. 14 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics over the Operating Temperature Range and Supply Voltage Range for RapidWrite Mode Write Cycle(1) Symbol tAAS tARF Parameter Allowable Address Skew for RapidWrite Mode Address Rise/Fall Time for RapidWrite Mode Min ____ Max 1 ____ Unit ns V/ns 5670 tbl 14 1.5 NOTE: 1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle. Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle A0 tAAS tARF A18 NOTE: 1. A17 for IDT70T631. (1) tARF 5670 drw 09 15 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW SEM(1) tEW tOH tDW I/O tAS R/W tSWRD OE Write Cycle VALID ADDRESS tACE tWR tSOP DATA OUT(2) VALID DATA IN VALID tWP tDH tSOE tSOP Read Cycle 5670 drw 12 . NOTES: 1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for appropriate UB/LB controls. 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17 ) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2"B" MATCH SIDE (2) "B" R/W"B" SEM"B" 5670 drw 13 . NOTES: 1. DOR = D OL = VIL, CE 0L = CE0R = VIH; CE 1L = CE1R = VIL. Refer also to Truth Table II for appropriate UB/LB controls. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag. 16 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70T633/1S8(6) Com'l Only Symbol BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Access Time from Chip Enable Low BUSY Disable Time from Chip Enable High Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data Write Hold After BUSY (5) (3) ____ ____ ____ ____ Parameter 70T633/1S10 Com'l & Ind(6) Min. Max. 70T633/1S12 Com'l & Ind Min. Max. 70T633/1S15 Com'l Only Min. Max. Unit Min. Max. 8 8 8 8 ____ ____ ____ ____ ____ 10 10 10 10 ____ ____ ____ ____ ____ 12 12 12 12 ____ ____ ____ ____ ____ 15 15 15 15 ____ ns ns ns ns ns ns ns 2.5 ____ 2.5 ____ 2.5 ____ 2.5 ____ 8 ____ 10 ____ 12 ____ 15 ____ 6 7 9 12 BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY(5) 0 6 ____ ____ 0 7 ____ ____ 0 9 ____ ____ 0 12 ____ ____ ns ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ ____ 12 12 ____ ____ 14 14 ____ ____ 16 16 ____ ____ 20 20 ns ns 5670 tbl 15 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH )". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2,3) 70T633/1S8(4) Com'l Only Symbol SLEEP MODE TIMING (ZZx=V IH) tZZS tZZR tZZPD tZZPU Sleep Mode Set Time Sleep Mode Reset Time Sleep Mode Power Down Time (5) Sleep Mode Power Up Time (5) 8 8 8 ____ ____ ____ ____ Parameter 70T633/1S10 Com'l & Ind(4) Min. Max. 70T6331S12 Com'l & Ind Min. Max. 70T633/1S15 Com'l Only Min. Max. Min. Max. 10 10 10 ____ ____ ____ ____ 12 12 12 ____ ____ ____ ____ 15 15 15 ____ ____ ____ ____ 0 0 0 0 5670 tbl 15a NOTES: 1. Timing is the same for both ports. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundary scan not be operated during sleep mode. 3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only. 5. This parameter is guaranteed by device characterization, but is not production tested. 17 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT "B" tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CE0L = CE0R = VIL; CE1L = CE1R = VIH. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 5670 drw 14 (1) tDH VALID MATCH tBDA tBDD VALID . Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B" NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB only applies to the slave mode. (2) . 5670 drw 15 18 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1) ADDR"A" and "B" CE"A"(3) tAPS (2) ADDRESSES MATCH CE"B"(3) tBAC BUSY"B" tBDC . 5670 drw 16 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1,3,4) ADDR"A" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA BUSY"B" 5670 drw 17 ADDRESS "N" tBDA NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. CEX = VIL when CE0X = V IL and CE1X = VIH. CEX = VIH when CE 0X = VIH and/or CE1X = VIL. 4. CE0X = OEX = LBX = UBX = VIL. CE1X = V IH. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) 70T633/1S8(3) Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0 ____ ____ ____ ____ 70T633/1S10 Com'l & Ind(3) Min. Max. 70T633/1S12 Com'l & Ind Min. Max. 70T633/1S15 Com'l Only Min. Max. Unit Parameter Min. Max. 0 0 ____ ____ ____ ____ 0 0 ____ ____ ____ ____ 0 0 ____ ____ ____ ____ ns ns ns ns 5670 tbl 16 8 8 10 10 12 12 15 15 NOTES: 1. Timing is the same for both ports. 2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only. 19 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC ADDR"A" tAS(4) CE"A"(3) INTERRUPT SET ADDRESS (2) tWR(5) R/W"A" tINS INT"B" . 5670 drw 18 (4) tRC ADDR"B" CE"B"(3) INTERRUPT CLEAR ADDRESS tAS (4) (2) OE"B" tINR (4) INT"B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. Refer to Interrupt Truth Table. 3. CEX = V IL means CE0X = VIL and CE 1X = V IH. CEX = VIH means CE0X = VIH and/or CE1X = VIL. 4. Timing depends on which enable signal (CE or R/ W) is asserted last. 5. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5670 drw 19 . Truth Table III — Interrupt Flag(1,4) Left Port R/WL L X X X CEL L X X L OEL X X X L A18L-A0L(5) 7FFFF X X 7FFFE INTL X X L (3) (2) Right Port R/WR X X L X CER X L L X OER X L X X A18R-A0R(5) X 7FFFF 7FFFE X INTR L(2) H (3) Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 5670 tbl 17 X X H NOTES: 1. Assumes BUSYL = BUSYR =VIH. CEX = L means CE0X = VIL and CE1X = VIH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 5. A18x is a NC for IDT70T631. Therefore, Interrupt Addresses are 3FFFF and 3FFFE. 20 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs CEL(5) CER(5) X H X L X X H L A0L-A18L(4) A0R-A18R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 5670 tbl 18 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70T633/1 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A18 is a NC for IDT70T631. Address comparison will be for A0 - A 17. 5. CEX = L means CE 0X = V IL and CE 1X = V IH. CEX = H means CE0X = VIH and/or CE1X = V IL. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D17 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D17 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 5670 tbl 19 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T633/1. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17 ). These eight semaphores are addressed by A0 - A2. 3. CE0 = VIH, CE1 = SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. The IDT70T633/1 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70T633/1 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted. Functional Description Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt 21 flag (INTL) is asserted when the right port writes to memory location 7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFFF. The message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T631) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFFE and 7FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70T633/1 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Busy Logic address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. A19 CE0 MASTER Dual Port RAM BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR CE1 MASTER Dual Port RAM BUSYL BUSYR CE1 SLAVE Dual Port RAM BUSYL BUSYR . 5670 drw 20 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70T633/1 Dual-Port RAMs. When expanding an IDT70T633/1 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70T633/1 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and 22 Width Expansion with Busy Logic Master/Slave Arrays The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and SEM, the semaphore enable. The CE0, CE1, and SEM pins control onchip power down circuitry that permits the respective port to go into standby mode when not selected. Systems which can best use the IDT70T633/1 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the hardware semaphores of the IDT70T633/1, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70T633/1 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. Semaphores The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then How the Semaphore Flags Work IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70T633/1 in a separate memory space from the Dual-Port RAM array. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE0, CE1, R/W and LB/UB) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE signals need to be active. (Please refer to Truth Table II). Furthermore, the read value is latched into one side’s output register when that side's semaphore select (SEM, BEn) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been 23 used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the opposite side HIGH. This condition will continue until a one is written to the same semaphore request latch. If the opposite side semaphore request latch has been written to zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first request latch. The L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ SEMAPHORE READ Figure 4. IDT70T633/1 Semaphore Logic 5670 drw 21 opposite side flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Timing Waveform of Sleep Mode(1,2) Normal Operation No new reads or writes allowed Sleep Mode No reads or writes allowed Normal Operation CE0 tZZS tZZR ZZ , I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM 24 VALID ADDRESS VALID DATA tZZPD IZZ ADDRESS DATA IDD 5670 drw 22 tZZPU Preliminary Industrial and Commercial Temperature Ranges NOTES: 1. CE1 = V IH. 2. All timing is same for Left and Right ports. IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges The IDT70T633/1 is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will have the lowest possible power consumption. The sleep mode timing diagram demonstrates the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For a period of time prior to sleep mode and after recovering from sleep Sleep Mode mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). During sleep mode the RAM automatically deselects itself and disconnects its internal buffer. All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle, but the RAM will not be selected and will not perform any reads or writes. JTAG Timing Specifications tJF TCK tJCL tJCYC tJR tJCH Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO TRST 5670 drw 23 tJH tJDC tJRSR tJCD x tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4,5) 70T633/1 Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40 ____ ____ Max. ____ ____ ____ Units ns ns ns ns ns ns ns ns ns ns ns 5670 tbl 20 3 3 (1) (1) 50 50 ____ ____ ____ 25 ____ ____ ____ 0 15 15 NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 5. JTAG cannot be tested in sleep mode. 25 I DT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70T631 is 0x33C. Value 0x0 0x33B (1) Description Reserved for version number Defines IDT part number 70T633 Allows unique identification of device vendor as IDT Indicates the presence of an ID register 5670 tbl 21 0x33 1 Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size 4 1 32 Note (3) 5670 tbl 22 System Interface Parameters Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. 5670 tbl 23 HIGHZ CLAMP SAMPLE/PRELOAD 0011 0001 RESERVED All other codes NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 26 IDT70T633/1S High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Blank I BC DD BF 256-ball BGA (BC-256) 144-pin TQFP (DD-144) 208-ball fpBGA (BF-208) 8 10 12 15 Commercial Only(1) Commercial & Industrial(1) Commercial & Industrial Commercial Only . Speed in nanoseconds S Standard Power 70T633 9Mbit (512K x 18) 2.5V Asynchronous Dual-Port RAM 70T631 4Mbit (256K x 18) 2.5V Asynchronous Dual-Port RAM 5670 drw 24 NOTE: 1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only Preliminary Datasheet: Definition "PRELIMINARY' datasheets contain descriptions for products that are in early release. Datasheet Document History: 04/25/03: 10/01/03: Initial Datasheet Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only Page 10 Added Capacitance Derating Drawing Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table Page 12 Added tLZOB to the Waveform of Read Cycles Drawing Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms Page 15 Corrected tARF to 1.5V/ns Min. 10/20/03: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 27